典。
-- DDFS.vhd--------------------------------------- Direct Digital Freq. Synthesis ----------------------------------------- (c) Bert Cuzeau, ALSE - info@-- May be reproduced provided that copyright above remains.-- We use one of the symetries in the sine function,-- so the lookup table is re-used twice (128 entries table)-- The Sine Table is built by a C program...--------------------------------------- Design IOs :-- Clk : Global Clock input-- Rst : Global Reset input-- Freq_data : 8-bit frequency control vector-- from DIP switches on the board.-- Dout : is signed 8-bit output to the DAC.-- -----------------------------------------------library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;-- -----------------------------------------------Entity DDFS is-- -----------------------------------------------Port ( CLK : in std_logic;RST : in std_logic;Freq_Data : in std_logic_vector (7 downto 0);Dout : out std_logic_vector (7 downto 0));end DDFS;-- -----------------------------------------------Architecture RTL of DDFS is-- -----------------------------------------------signal Address : unsigned (6 downto 0);signal Result : std_logic_vector (7 downto 0);signal Accum : unsigned (28 downto 0); -- we want very low Frequencies ! signal Sign : std_logic;begin-- Signed Accumulator-- ------------------Acc: process (CLK,RST)beginif RST='1' thenAccum '0');elsif rising_edge(CLK) thenAccum <= Accum + unsigned(Freq_Data);end if;END process acc;Sign <= Accum(Accum'high); -- MSB-- Lookup Table Index calculation-- ------------------------------Address <= unsigned(Accum(Accum'high-1 downto Accum'high-Address'length)); -- SINE Look-Up TABLE-- --------------------- Inference of an Asynchronous Rom.-- A synchronous one would be better, but we register the output.-- This table has been built by GENVEC.exe (C program)-- We use only positive values ! (sign comes from quadrant info)-- This could be further optimized by coding only one quadrant...lookup: process (Address)subtype SLV8 is std_logic_vector (7 downto 0);type Rom128x8 is array (0 to 127) of SLV8; -- 0 to 2**Address'length - 1 constant Sinus_Rom : Rom128x8 := (x"00", x"03", x"06", x"09", x"0c", x"0f", x"12", x"15",x"18", x"1b", x"1e", x"21", x"24", x"27", x"2a", x"2d",x"30", x"33", x"36", x"39", x"3b", x"3e", x"41", x"43",x"46", x"49", x"4b", x"4e", x"50", x"52", x"55", x"57",x"59", x"5b", x"5e", x"60", x"62", x"64", x"66", x"67",x"69", x"6b", x"6c", x"6e", x"70", x"71", x"72", x"74",x"75", x"76", x"77", x"78", x"79", x"7a", x"7b", x"7b",x"7c", x"7d", x"7d", x"7e", x"7e", x"7e", x"7e", x"7e",x"7f", x"7e", x"7e", x"7e", x"7e", x"7e", x"7d", x"7d",x"7c", x"7b", x"7b", x"7a", x"79", x"78", x"77", x"76",x"75", x"74", x"72", x"71", x"70", x"6e", x"6c", x"6b",x"69", x"67", x"66", x"64", x"62", x"60", x"5e", x"5b",x"59", x"57", x"55", x"52", x"50", x"4e", x"4b", x"49",x"46", x"43", x"41", x"3e", x"3b", x"39", x"36", x"33",x"30", x"2d", x"2a", x"27", x"24", x"21", x"1e", x"1b",x"18", x"15", x"12", x"0f", x"0c", x"09", x"06", x"03" );beginResult '0');elsif rising_edge(CLK) thenif Sign='1' thenDout <= Result;elseDout <= std_logic_vector (- signed(Result));end if;end if;。
VHDL语言实例例1：设计一七段显示译码器，用它来驱动七段发光管LED显示十六进制数字0到9和字母A到F。
LED显示数码管为共阳极。
LIBRARYieee;USE ieee.std_logic_1164.all;ENTITY HEX2LEDISPORT(HEX :IN std_logic_vector(3 DOWNTO0);LED : OUT std_logic_vector(6 TO0));ENDHEX2LED; 图例1 七段显示译码器实体ARCHITECTURE HEX2LED_arc OF HEX2LED IS BEGIN-- HEX-TO-SEVEN-SEGMENT DECODER-- SEGMENT ENCODING---------- 5 ||1-- ---- <--6-- 4 ||2--------3WITH HEX SELECTLED<= "1111001" when "0001","0100100" when "0010","0110000" when "0011","0011001" when "0100","0010010" when "0101","0000010" when "0110","1111000" when "0111","0000000" when "1000","0010000" when "1001","0001000" when "1010","0000011" when "1011","1000110" when "1100","0100001" when "1101","0000110" when "1110","0001110" when "1111","1000000" when others;END HEX2LED_arc;例2：设计一个八选一数据选择器1）s是通道选择信号, d0,d1,d2,d3,d4,d5,d6,d7数据输入 out1是数据输出ENTITY sels ISPORT(d0,d1,d2,d3,d4,d5,d6,d7:INBIT;s :INTEGER RANGE0 TO 7;out1 :OUT BIT);END sels;图例2（a) 八选一数据选择器实体ARCHITECTURE sels_arc OF sels ISBEGINWITH s SELECTout1 <= d0 WHEN 0,d1 WHEN 1,d2 WHEN 2,d3 WHEN 3,d4 WHEN 4,d5 WHEN 5,d6 WHEN 6,d7 WHEN 7;END sels_arc;2)A,B,C是通道选择信号, I0,I1,I2,I3,I4,I5,I6,I7数据输入 Q是数据输出LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY mux8 ISPORT(I0,I1,I2,I3,I4,I5,I6,I7,A,B,C:INstd_logic;Q :OUT std_logic);END mux8;图例2（b) 八选一数据选择器实体SIGNAL sel :INTEGER ；BEGINQ <= I0 AFTER 10 ns WHEN sel= 0 ELSEI1 AFTER 10 ns WHEN sel= 1 ELSEI2 AFTER 10 ns WHEN sel= 2 ELSEI3 AFTER 10 ns WHEN sel= 3 ELSEI4 AFTER 10 ns WHEN sel= 4 ELSEI5 AFTER 10 ns WHEN sel= 5 ELSEI6 AFTER 10 ns WHEN sel= 6 ELSEI7 AFTER 10 ns ;sel <= 0 WHEN A= ‘0’ AND B= ‘0’ AND C= ‘0’ ELSE1 WHEN A= ‘1’ AND B= ‘0’ AND C= ‘0’ ELSE2 WHEN A= ‘0’ AND B= ‘1’ AND C= ‘0’ ELSE3 WHEN A= ‘1’ AND B= ‘1’ AND C= ‘0’ ELSE4 WHEN A= ‘0’ AND B= ‘0’ AND C= ‘1’ EL SE5 WHEN A= ‘1’ AND B= ‘0’ AND C= ‘1’ ELSE6 WHEN A= ‘0’ AND B= ‘0’ AND C= ‘1’ ELSE7;END mux8_arc;例3：设计一D触发器d是输入端，clk是时钟信号控制端，q是触发器的输出端。
VHDL 数字逻辑电路设计19例第1章组合逻辑电路8例1. 2-4译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ymq24 ISPORT (EN,A,B:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(3 downto 0 ));END ENTITY ymq24 ;ARCHITECTURE rt1 OF ymq24 ISSIGNAL T:STD_LOGIC_vector(1 downto 0 );BEGINT<=A & B;process(EN,T)beginIF EN='1' THEN YN<="1111";ELSIF T="00" THEN YN<="1110";ELSIF T="01" THEN YN<="1101";ELSIF T="10" THEN YN<="1011";ELSE YN<="0111";END IF;End process;END ARCHITECTURE rt1;2. 3-8译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ymq38 ISPORT (G1,G2N,G3N,A,B,C:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 )); END ENTITY ymq38 ;ARCHITECTURE rt1 OF ymq38 ISSIGNAL T1,T2:STD_LOGIC_vector(2 downto 0 );BEGINT1<=A & B & C;T2<=G1 & G2N & G3N;process(G1,G2N,G3N,T1,T2)beginIF T2/="100" THEN YN<="11111111";ELSIF T1="000" THEN YN<="11111110";ELSIF T1="001" THEN YN<="11111101";ELSIF T1="010" THEN YN<="11111011";ELSIF T1="011" THEN YN<="11110111";ELSIF T1="100" THEN YN<="11101111";ELSIF T1="101" THEN YN<="11011111";ELSIF T1="110" THEN YN<="10111111";ELSE YN<="01111111";END IF;End process;END ARCHITECTURE rt1;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xzq41 ISPORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);a0,a1: IN STD_LOGIC;y: out STD_LOGIC);END ENTITY xzq41;ARCHITECTURE rt1 OF xzq41 ISsignal s: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINS<= a1 & a0;Process(S,D,gn)beginif gn='0' thenCASE (S) ISWHEN "00"=> Y<=d(0);WHEN "01"=> Y<=d(1);WHEN "10"=> Y<=d(2);WHEN "11"=> Y<=d(3);WHEN OTHERS =>NULL;END CASE;else y<='0';end if;End process;END ARCHITECTURE rt1;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xzq81 ISPORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);a0,a1,a2: IN STD_LOGIC;y: out STD_LOGIC);END ENTITY xzq81;ARCHITECTURE rt1 OF xzq81 ISsignal s: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGINS<= a2 & a1 & a0;Process(S,D,gn)beginif gn='0' thenCASE (S) ISWHEN "000"=> Y<=d(0);WHEN "001"=> Y<=d(1);WHEN "010"=> Y<=d(2);WHEN "011"=> Y<=d(3);WHEN "100"=> Y<=d(4);WHEN "101"=> Y<=d(5);WHEN "110"=> Y<=d(6);WHEN "111"=> Y<=d(7);WHEN OTHERS =>NULL;END CASE;else y<='0';end if;End process;END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l75 ISPORT (A,B,C:IN STD_LOGIC;d,g : OUT STD_LOGIC);END ENTITY l75 ;ARCHITECTURE rt1 OF l75 ISCOMPONENT ymq38PORT (G1, G2N, G3N, A, B, C: IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 )); END COMPONENT ;signal ynt : STD_LOGIC_vector(7 downto 0 );BEGINU1 :ymq38 PORT MAP ('1','0','0',a,b,c,YNt(7 DOWNTO 0));d<=not(ynt(1) and ynt(2) and ynt(4) and ynt(7));g<=not(ynt(1) and ynt(2) and ynt(3) and ynt(7));END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l76 ISPORT (A,B,C,D:IN STD_LOGIC;F : OUT STD_LOGIC);END ENTITY l76 ;ARCHITECTURE rt1 OF l76 ISCOMPONENT ymq38PORT (G1,G2N,G3N,A,B,C:IN STD_LOGIC;YN : OUT STD_LOGIC_vector(7 downto 0 ));END COMPONENT ;signal yn1t:STD_LOGIC_vector(7 downto 0 );signal yn2t:STD_LOGIC_vector(7 downto 0 );BEGINU1 :ymq38 PORT MAP ('1',A,'0',B,C,D,YN1t(7 DOWNTO 0));U2 :ymq38 PORT MAP (A,'0','0',B,C,D,YN2t(7 DOWNTO 0));F<=not( yn1t(2) and yn1t(4) and yn1t(6) and yn2t(0) and yn2t(2) and yn2t(4) and yn2t(6)); END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l78 ISPORT (A,B,C:IN STD_LOGIC;f : OUT STD_LOGIC);END ENTITY l78 ;ARCHITECTURE rt1 OF l78 ISCOMPONENT xzq81PORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);a0,a1,a2: IN STD_LOGIC;y: out STD_LOGIC);END COMPONENT ;BEGINU1 :xzq81 PORT MAP ('0',"01101100",c,b,a,f);END ARCHITECTURE rt1;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY l78 ISPORT (A,B,C:IN STD_LOGIC;f : OUT STD_LOGIC);END ENTITY l78 ;ARCHITECTURE rt1 OF l78 ISCOMPONENT xzq41PORT(gn: IN STD_LOGIC;d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);a0,a1: IN STD_LOGIC;y: out STD_LOGIC);END COMPONENT ;signal t:STD_LOGIC;signal dt:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINt<= not c;dt<=t & c & '1' & '0';U1 :xzq41 PORT MAP ('0',dt,b,a,f);【作业】以下所有题目必须用VHDL代码实现。
