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锁相环的工作原理锁相环（PLL）是一种常见的控制系统，它被广泛应用于通信、电子、自动控制等领域。
它的工作原理基于信号的频率比较和相位调整，能够使输出信号与输入信号保持稳定的频率和相位关系。
下面将详细介绍锁相环的工作原理。
首先，锁相环的核心部分是相位比较器。
相位比较器用来比较输入信号和反馈信号的相位差，然后输出一个误差信号。
这个误差信号的大小和方向表示了输入信号和反馈信号之间的相位差，是锁相环调节的依据。
其次，误差信号经过环路滤波器，得到一个平滑的控制电压。
环路滤波器的作用是去除误差信号中的高频噪声，使得控制电压更加稳定。
这个控制电压将作为VCO（Voltage Controlled Oscillator）的输入，控制VCO的输出频率。
接着，VCO是锁相环中的另一个重要组成部分。
VCO的输出频率受控制电压的影响，当控制电压增大时，VCO的输出频率也增大；反之，控制电压减小时，VCO的输出频率减小。
通过这种方式，VCO能够实现对输出频率的精确调节。
最后，VCO的输出信号经过分频器，得到反馈信号。
这个反馈信号与输入信号经过相位比较器进行比较，产生误差信号，闭环控制系统开始工作。
通过不断调节VCO的控制电压，使得输入信号和反馈信号的相位差趋近于零，从而实现了锁相环的稳定工作。
总结一下，锁相环的工作原理是通过相位比较器比较输入信号和反馈信号的相位差，产生误差信号；经过环路滤波器得到控制电压，控制VCO的输出频率；VCO的输出信号经过分频器得到反馈信号，闭环控制系统开始工作，不断调节VCO的控制电压，使得输入信号和反馈信号的相位差趋近于零，实现了锁相环的稳定工作。
通过对锁相环的工作原理进行了解，我们可以更好地应用它在通信、电子、自动控制等领域，实现信号的稳定控制和处理。
希望本文能够帮助大家更好地理解锁相环的工作原理，为相关领域的工程应用提供帮助。
锁相环原理及应用PLL（Phaze Locked Loop）锁相环自1932年问世以来，其应用领域遍及频率相位跟踪控制的各个领域，如通信、雷达、航天、测量、电视、控制等。
随着集成技术的发展，其应用的重要性已成为从事检测、通信、控制工作人员非常重要的应用工具手段，成为电子设备中常用的一种基本部件。
鉴于上述情况，非常有必要学习和掌握这门技术。
它是什么器件有如此大的威力呢？锁相环：是一个闭环的相位控制系统，它跟踪输入信号的相位，并自动锁定。
实现对输入信号频率和相位的自动跟踪。
它跟踪固定频率的输入信号时无频差，跟踪信号的相位时（锁相控制）精度很高；跟踪信号的频率变化的输入信号时（收音机）精度也很高。
它对输入信号恰似一个窄带跟踪滤波器，能够跟踪淹没在噪声之中的微弱信号。
鉴于上述种种独特功能，它在电子设备中越来越广泛地被采用。
它的窄带跟踪滤波和低门限特性，使它成为从噪声中检测调频调相合调幅信号的最佳方法之一。
§1 锁相环工作原理一、组成：锁相环由三个基本部件组成：鉴相器（PD）、低通滤波器（LF）和压控振荡器（VCO）构成。
与相敏检测器的不同之处在于参考信号由输出的信号闭环形成。
1.鉴相器：是一个相位比较环节，它把输入信号与压控振荡器输出信号的相位进行比较，产生对应两信号相位差的误差电压。
是两信号相位差鉴相器特性可以是多种多样的，有正弦形、方波、三角形、锯齿形特性。
它的电路有各种形式，主要有两类：1）相乘器电路2）序列电路：它的输出电压是输入信号过零点与反馈电压过零点之间时间差的函数。
这类鉴相器的输出只与波形的边沿有关，适用于方波，通常用电路构成。
2.低通滤波器（环路）：具有低通特性，滤除中的变频成分和噪声，以保证环路要求的性能，增加环路的稳定性，产生对应的一个直流控制电压。
常用的环路滤波器有：RC积分滤波器、无源比例积分滤波器和有源比较积分滤波器3.VCO（Voltage Controlled Oscillator）：它是一个电压—频率转换器，由控制产生相应频率，使其频率朝着输入信号的频率靠拢，由于相位负反馈的作用直至消除频差实现环路锁定。
锁相环工作原理锁相环（Phase-Locked Loop，简称PLL）是一种常用的电子电路，用于在信号处理和通信系统中实现频率合成、时钟恢复、频率解调等功能。
它可以通过自动调整输出信号的相位和频率，使其与输入信号保持稳定的相位关系。
锁相环主要由相位比较器、环路滤波器、电压控制振荡器（Voltage-Controlled Oscillator，简称VCO）和分频器组成。
1. 相位比较器（Phase Detector）：相位比较器是锁相环的核心部件之一，它用于比较输入信号与反馈信号的相位差，并产生相应的误差信号。
常见的相位比较器有边沿触发型、恒幅型和恒频型等。
2. 环路滤波器（Loop Filter）：环路滤波器用于对相位比较器输出的误差信号进行滤波和放大处理，以提供稳定的控制电压给VCO。
它通常由滤波电容和滤波电阻组成，根据需要可以采用不同的滤波器结构。
3. 电压控制振荡器（Voltage-Controlled Oscillator）：VCO是锁相环的另一个关键组成部份，它根据输入的控制电压来产生相应频率的输出信号。
VCO的频率与控制电压成正比关系，通过调节控制电压可以实现对输出频率的精确控制。
4. 分频器（Divider）：分频器用于将VCO的输出信号分频，以产生反馈信号供相位比较器使用。
分频器通常采用可编程分频比，可以根据需要设置不同的分频比。
锁相环的工作原理如下：1. 初始状态下，输入信号经过相位比较器与反馈信号进行比较，产生误差信号。
2. 误差信号经过环路滤波器进行滤波和放大处理，得到控制电压。
3. 控制电压作用于VCO，调节VCO的频率，使其与输入信号保持稳定的相位关系。
4. VCO的输出信号经过分频器分频后，形成反馈信号，与输入信号进行比较，闭环控制。
5. 通过不断调节VCO的频率，使得输入信号与反馈信号的相位差趋近于零，锁定相位关系。
6. 一旦锁定相位关系后，VCO的输出信号就可以作为同步信号或者频率合成信号使用。
锁相环的工作原理讲解锁相环（Phase-locked loop，简称PLL）是一种常用的控制系统，它通过对输入信号进行频率和相位的调整，使其与参考信号同步。
锁相环广泛应用于通信、测量、数据采集等领域，具有高精度、稳定性好等优点。
锁相环的工作原理可以简单地描述为三个主要步骤：相比较、滤波和控制。
首先，输入信号和参考信号经过相比较器进行相位比较，产生一个误差信号。
然后，误差信号经过滤波器进行滤波处理，得到一个稳定的控制信号。
最后，控制信号通过控制器对振荡器进行调整，使得输出信号与参考信号同步。
在锁相环中，相比较器是关键的元件之一。
相比较器将输入信号与参考信号进行相位比较，产生一个差异信号。
这个差异信号代表了输入信号与参考信号之间的相位偏差。
根据这个相位偏差，锁相环可以控制振荡器的频率和相位，使得输入信号与参考信号同步。
滤波器是另一个重要的组成部分。
它的作用是对误差信号进行滤波处理，去除高频噪声和杂散信号，得到一个稳定的控制信号。
滤波器通常采用低通滤波器的形式，只允许通过低频信号，抑制高频信号的干扰。
滤波器的设计要考虑到系统的带宽和稳定性。
控制器根据滤波后的误差信号来调整振荡器的频率和相位。
控制器通常采用比例-积分-微分（PID）控制算法，根据误差信号的大小和变化率来调整振荡器的输出。
PID控制器具有响应快、稳定性好的特点，可以使锁相环快速跟踪参考信号。
除了上述的基本组成部分，锁相环还可以包括频率分频器、倍频器、反相器等附加元件，用于实现更复杂的功能。
例如，频率分频器可以将输入信号的频率降低到锁相环的工作范围内；倍频器可以将振荡器的输出信号进行倍频，得到更高频率的信号。
这些附加元件可以根据具体的应用需求进行选择和配置。
锁相环具有很多应用，其中一个典型的应用是频率合成器。
频率合成器可以通过锁相环的频率调整功能，将多个不同频率的信号合成为一个特定频率的信号。
这在通信系统中非常常见，可以用于频率调制、解调、时钟同步等方面。
锁相环基本原理锁相环基本原理⼀个典型的锁相环（PLL ）系统，是由鉴相器（PD ），压控荡器（VCO ）和低通滤波器（LPF ）三个基本电路组成，如图1，Ud = Kd (θi –θo) U F = Ud F （s ）θiθo 图1⼀．鉴相器（PD ）构成鉴相器的电路形式很多，这⾥仅介绍实验中⽤到的两种鉴相器。
异或门的逻辑真值表⽰于表1，图2是逻辑符号图。
表1图2从表1可知，如果输⼊端A 和B 分别送 2π⼊占空⽐为50%的信号波形，则当两者存在相位差?θ时，输出端F 的波形的占空⽐与?θ有关，见图3。
将F 输出波形通过积分器平滑，则积分器输出波形的平均值，它同样与?θ有关，这样，我们就可以利⽤异或门来进⾏相位到电压 ?θ的转换，构成相位检出电路。
于是经积图3分器积分后的平均值（直流分量）为： UU=Vdd*?θ/π (1) Vcc不同的?θ，有不同的直流分量Vd 。
?θ与V 的关系可⽤图4来描述。
从图中可知，两者呈简单线形关 1/2Vcc 系：Ud = Kd *?θ (2)1/2ππ?θ Kd 为鉴相灵敏度图4FO o U K dtd =θVPDLPFVCOUiUoVA B F__F = A B + A B F B A2．边沿触发鉴相器前已述及，异或门相位⽐较器在使⽤时要求两个作⽐较的信号必须是占空⽐为50%的波形，这就给应⽤带来了⼀些不便。
⽽边沿触发鉴相器是通过⽐较两输⼊信号的上跳边沿（或下跳边沿）来对信号进⾏鉴相，对输⼊信号的占空⽐不作要求。
⼆．压控振荡器（VCO ）压控振荡器是振荡频率ω0受控制电压U F （t ）控制的振荡器，即是⼀种电压——频率变换器。
VCO 的特性可以⽤瞬时频率ω0（t ）与控制电压U F （t ）之间的关系曲线来表⽰。
未加控制电压时（但不能认为就是控制直流电压为0，因控制端电压应是直流电压和控制电压的叠加），VCO 的振荡频率，称为⾃由振荡频率ωom ，或中⼼频率，在VCO 线性控制范围内，其瞬时⾓频率可表⽰为：ωo （t ）= ωom + K 0U F （t ）式中，K 0——VCO 控制特性曲线的斜率，常称为VCO 的控制灵敏度，或称压控灵敏度。
一文让你彻底明白“什么是锁相环PLL及其工作原理”锁相环（Phase-Locked Loop，简称PLL）是一种广泛应用于通信、数据传输、时钟同步等领域的电子电路。
它在这些应用中起着重要的作用，可以解决信号同步、频率合成、相位调制等问题。
本文将详细介绍什么是锁相环、它的工作原理，以及一些常见的应用场景。
一、什么是锁相环锁相环是一种反馈控制系统，通过比较输入信号的相位与参考信号的相位之间的差异来调整输出信号的相位和频率，使得输出信号与参考信号保持相位和频率的一致。
原理上，锁相环通过不断采样输入信号，并将其与参考信号进行比较，然后根据比较结果调整输出信号的相位和频率。
通过这种方式，锁相环可以将输入信号的频率和相位稳定在与参考信号一致的状态下。
一般来说，锁相环由锁相检测器、低通滤波器、电压控制振荡器和频率分割器等主要组成。
二、锁相环的工作原理1. 锁相检测器（Phase Detector）：锁相检测器是锁相环的核心部分。
它用于比较输入信号的相位差异，并产生一个误差信号。
常见的锁相检测器有相位比较器、采样比较器等。
相位比较器将输入信号和参考信号进行比较，并输出一个高电平或低电平的信号，表示输入信号相位与参考信号的相位关系。
2. 低通滤波器（Low Pass Filter）：低通滤波器用于平滑锁相检测器输出的误差信号，减小噪声的影响。
它通过将误差信号经过滤波器，然后输出平滑后的信号给电压控制振荡器。
3. 电压控制振荡器（Voltage-Controlled Oscillator，简称VCO）：电压控制振荡器是锁相环的另一个关键组件。
它的输出频率与输入电压成线性关系，即输出频率随着输入电压的变化而变化。
通过改变电压控制振荡器的输入电压，即通过低通滤波器输出的信号，可以调整输出信号的频率，从而使得输出信号与参考信号的频率一致。
4. 频率分割器（Frequency Divider）：频率分割器用于将电压控制振荡器的输出频率分割成较低的频率。
锁相环(PLL)的工作原理1．锁相环的基本组成许多电子设备要正常工作，通常需要外部的输入信号与内部的振荡信号同步，利用锁相环路就可以实现这个目的。
锁相环路是一种反馈控制电路，简称锁相环（PLL,Phase-Locked Loop）。
锁相环的特点是：利用外部输入的参考信号控制环路内部振荡信号的频率和相位。
因锁相环可以实现输出信号频率对输入信号频率的自动跟踪，所以锁相环通常用于闭环跟踪电路。
锁相环在工作的过程中，当输出信号的频率与输入信号的频率相等时，输出电压与输入电压保持固定的相位差值，即输出电压与输入电压的相位被锁住，这就是锁相环名称的由来。
锁相环通常由鉴相器（PD,Phase Detector）、环路滤波器（LF,Loop Filter）和压控振荡器（VCO,Voltage Controlled Oscillator）三部分组成，锁相环组成的原理框图如图8-4-1所示。
锁相环中的鉴相器又称为相位比较器，它的作用是检测输入信号和输出信号的相位差，并将检测出的相位差信号转换成u D（t）电压信号输出，该信号经低通滤波器滤波后形成压控振荡器的控制电压u C（t），对振荡器输出信号的频率实施控制。
2．锁相环的工作原理锁相环中的鉴相器通常由模拟乘法器组成，利用模拟乘法器组成的鉴相器电路如图8-4-2所示。
鉴相器的工作原理是：设外界输入的信号电压和压控振荡器输出的信号电压分别为：（8-4-1）（8-4-2）式中的ω0为压控振荡器在输入控制电压为零或为直流电压时的振荡角频率，称为电路的固有振荡角频率。
则模拟乘法器的输出电压u D为：用低通滤波器LF将上式中的和频分量滤掉，剩下的差频分量作为压控振荡器的输入控制电压u C （t）。
即u C（t）为：（8-4-3）式中的ωi为输入信号的瞬时振荡角频率，θi（t）和θO（t）分别为输入信号和输出信号的瞬时位相，根据相量的关系可得瞬时频率和瞬时位相的关系为：即（8-4-4）则，瞬时相位差θd为:（8-4-5）对两边求微分，可得频差的关系式为（8-4-6）上式等于零，说明锁相环进入相位锁定的状态，此时输出和输入信号的频率和相位保持恒定不变的状态，u c（t）为恒定值。
锁相环基本原理一个典型的锁相环（PLL ）系统，是由鉴相器（PD ），压控荡器（VCO ）和低通滤波器（LPF ）三个基本电路组成，如图1，Ud = Kd (θi –θo) U F = Ud F （s ）θi θo图1一．鉴相器（PD ）构成鉴相器的电路形式很多，这里仅介绍实验中用到的两种鉴相器。
异或门的逻辑真值表示于表1，图2是逻辑符号图。
表1 图2从表1可知，如果输入端A 和B 分别送 2π 入占空比为50%的信号波形，则当两者存在相位差∆θ时，输出端F 的波形的 占空比与∆θ有关，见图3。
将F 输出波 形通过积分器平滑，则积分器输出波形的平均值，它同样与∆θ有关，这样，我们就可以利用异或门来进行相位到电压 ∆θ 的转换，构成相位检出电路。
于是经积 图3 分器积分后的平均值（直流分量）为： UU = Vdd * ∆θ/ π (1) Vcc不同的∆θ，有不同的直流分量Vd 。
∆θ与V 的关系可用图4来描述。
从图中可知，两者呈简单线形关 1/2Vcc 系：Ud = Kd *∆θ (2)1/2π π ∆θ Kd 为鉴相灵敏度 图4FO oU K dtd =θVPD LP F VC O Ui Uo VA B F__F = A B + A B F BA2． 边沿触发鉴相器 前已述及，异或门相位比较器在使用时要求两个作比较的信号必须是占空比为50%的波形，这就给应用带来了一些不便。
而边沿触发鉴相器是通过比较两输入信号的上跳边沿（或下跳边沿）来对信号进行鉴相，对输入信号的占空比不作要求。
二． 压控振荡器（VCO ）压控振荡器是振荡频率ω0受控制电压U F （t ）控制的振荡器，即是一种电压——频率变换器。
VCO 的特性可以用瞬时频率ω0（t ）与控制电压U F （t ）之间的关系曲线来表示。
未加控制电压时（但不能认为就是控制直流电压为0，因控制端电压应是直流电压和控制电压的叠加），VCO 的振荡频率，称为自由振荡频率ωom ，或中心频率，在VCO 线性控制范围内，其瞬时角频率可表示为： ωo （t ）= ωom + K 0 U F （t ）式中，K 0——VCO 控制特性曲线的斜率，常称为VCO 的控制灵敏度，或称压控灵敏度。
MT-086TUTORIALFundamentals of Phase Locked Loops (PLLs)FUNDAMENTAL PHASE LOCKED LOOP ARCHITECTUREA phase-locked loop is a feedback system combining a voltage controlled oscillator (VCO) and a phase comparator so connected that the oscillator maintains a constant phase angle relative to a reference signal. Phase-locked loops can be used, for example, to generate stable output high frequency signals from a fixed low-frequency signal.Figure 1A shows the basic model for a PLL. The PLL can be analyzed as a negative feedback system using Laplace Transform theory with a forward gain term, G(s), and a feedback term, H(s), as shown in Figure 1B. The usual equations for a negative feedback system apply.(B) STANDARD NEGATIVE FEEDBACKCONTROL SYSTEM MODEL(A) PLL MODEL ERROR DETECTOR LOOP FILTER VCOFEEDBACK DIVIDER PHASE DETECTOR CHARGEPUMP F O = N F REFFigure 1: Basic Phase Locked Loop (PLL) ModelThe basic blocks of the PLL are the Error Detector (composed of a phase frequency detector and a charge pump ), Loop Filter , VCO , and a Feedback Divider . Negative feedback forces the error signal, e(s), to approach zero at which point the feedback divider output and the reference frequency are in phase and frequency lock, and F O = N FREF .Referring to Figure 1, a system for using a PLL to generate higher frequencies than the input, the VCO oscillates at an angular frequency of ωO . A portion of this signal is fed back to the error detector, via a frequency divider with a ratio 1/N. This divided down frequency is fed to one input of the error detector. The other input in this example is a fixed reference signal. The error detector compares the signals at both inputs. When the two signal inputs are equal in phase and frequency, the error will be constant and the loop is said to be in a “locked” condition.PHASE FREQUENCY DETECTOR (PFD)Figure 2 shows a popular implementation of a Phase Frequency Detector (PFD), basically consisting of two D-type flip flops. One Q output enables a positive current source; and the other Q output enables a negative current source. Assuming that, in this design, the D-type flip flop is positive-edge triggered, the possible states are shown in the logic table.+IN −IN CP (A) OUT OF FREQUENCY LOCK AND PHASE LOCK (B) IN FREQUENCY LOCK, BUTSLIGHTLY OUT OF PHASE LOCK 0+I +I0UP 100DOWN 010CP OUT + I −I 0+IN −IN OUT 0+I −I (C) IN FREQUENCY LOCK AND PHASE LOCKFigure 2: Phase/Frequency Detector (PFD) Driving Charge Pump (CP)Consider now how the circuit behaves if the system is out of lock and the frequency at +IN is much higher than the frequency at –IN, as shown in Figure 2A. Since the frequency at +IN is much higher than that at –IN, the UP output spends most of its time in the high state. The first rising edge on +IN sends the output high and this is maintained until the first rising edge occurs on –IN. In a practical system this means that the output, and thus the input to the VCO, is driven higher, resulting in an increase in frequency at –IN. This is exactly what is desired. If the frequency on +IN were much lower than on –IN, the opposite effect would occur. The output at OUT would spend most of its time in the low condition. This would have the effect of driving the VCO in the negative direction and again bring the frequency at –IN much closer to that at +IN, to approach the locked condition.Figure 2B shows the waveforms when the inputs are frequency-locked and close to phase-lock. Since +IN is leading –IN, the output is a series of positive current pulses. These pulses will tend to drive the VCO so that the –IN signal become phase-aligned with that on +IN. When this occurs, if there were no delay element between U3 and the CLR inputs of U1 and U2, it would be possible for the output to be in high-impedance mode, producing neither positive nor negative current pulses. This would not be a good situation.The VCO would drift until a significant phase error developed and started producing either positive or negative current pulses once again. Over a relatively long period of time, the effect of this cycling would be for the output of the charge pump to be modulated by a signal that is a sub-harmonic of the PFD input reference frequency. Since this could be a low frequency signal, it would not be attenuated by the loop filter and would result in very significant spurs in the VCO output spectrum, a phenomenon known as the "backlash" or "dead zone" effect.The delay element between the output of U3 and the CLR inputs of U1 and U2 ensures that it does not happen. With the delay element, even when the +IN and –IN are perfectly phase-aligned, there will still be a current pulse generated at the charge pump output as shown in Figure 2C. The duration of this delay is equal to the delay inserted at the output of U3 and is known as the anti-backlash pulse width.Note that if the +IN frequency is lower than the −IN frequency and/or the +IN phase lags the −IN phase, then the output of the charge pump will be a series of negative current pulses—the reverse of the condition shown in (A) and (B) in Figure 2.PRESCALERSIn the classical Integer-N synthesizer, the resolution of the output frequency is determined by the reference frequency applied to the phase detector. So, for example, if 200 kHz spacing is required (as in GSM phones), then the reference frequency must be 200 kHz. However, getting a stable 200 kHz frequency source is not easy. A sensible approach is to take a good crystal-based high frequency source and divide it down. For example, the desired frequency spacing could be achieved by starting with a 10 MHz frequency reference and dividing it down by 50. This approach is shown in Figure 3A.(A)(B)REFERENCEDIVIDER÷R REFERENCEDIVIDER÷RPRESCALER÷PFigure 3: Adding an Input Reference Divider and a Prescaler to the Basic PLLThe "N counter," also known as the N divider, is the programmable element that sets the relationship between the input and output frequencies in the PLL. The complexity of the N counter has grown over the years. In addition to a straightforward N counter, it has evolved to include a prescaler, which can have a dual modulus. This structure has grown as a solution to the problems inherent in using the basic divide-by-N structure to feed back to the phase detector when very high-frequency outputs are required. For example, let’s assume that a 900 MHz output is required with 10 Hz spacing. A 10 MHz reference frequency might be used, with the R-Divider set at 1000. Then, the N-value in the feedback would need to be of the order of 90,000. This would mean at least a 17-bit counter capable of dealing with an input frequency of 900 MHz. To handle this range, it makes sense to precede the programmable counter with a fixed counter element to bring the very high input frequency down to a range at which standard CMOS will operate. This counter, called a prescaler, is shown in Figure 3B.However, note that using a standard prescaler as shown reduces the system resolution to F1×P. This issue can be addressed by using a dual-modulus prescaler which has the advantages of a standard prescaler, but without loss of resolution. A dual-modulus prescaler is a counter whose division ratio can be switched from one value to another by an external control signal. It's use is described shown in Figure 4.=, THEREFOREFigure 4: Adding a Dual Modulus Prescaler to the PLLBy using the dual-modulus prescaler with an A and B counter, one can still maintain output resolution of F1. However, the following conditions must be met:1.The output signals of both counters are High if the counters have not timed out.2.When the B counter times out, its output goes Low, and it immediately loads bothcounters to their preset values.3.The value loaded to the B counter must always be greater than that loaded to the Acounter.Assume that the B counter has just timed out and both counters have been reloaded with the values A and B. Let’s find the number of VCO cycles necessary to get to the same state again.As long as the A counter has not timed out, the prescaler is dividing down by P + 1. So, both the A and B counters will count down by 1 every time the prescaler counts (P + 1) VCO cycles. This means the A counter will time out after ((P + 1) × A) VCO cycles.At this point the prescaler is switched to divide-by-P. It is also possible to say that at this time the B counter still has (B – A) cycles to go before it times out. How long will it take to do this: ((B – A) × P).The system is now back to the initial condition where we started.The total number of VCO cycles needed for this to happen is :N = [A × (P + 1)] + [(B – A) × P]= AP + A + BP – AP= BP + A.Therefore, F OUT = (F REF/R) × (BP + A), as in Figure 4.There are many specifications to consider when designing a PLL. The input RF frequency range and the channel spacing determine the value of the R and N counter and the prescaler parameters.The loop bandwidth determines the frequency and phase lock time. Since the PLL is a negative feedback system, phase margin and stability issues must be considered.Spectral purity of the PLL output is specified by the phase noise and the level of the reference-related spurs.Many of these parameters are interactive; for instance, lower values of loop bandwidth lead to reduced levels of phase noise and reference spurs, but at the expense of longer lock times and less phase margin.Because of the many tradeoffs involved, the use of a PLL design program such as the Analog Devices' ADIsimPLL™ allows these tradeoffs to be evaluated and the various parameters adjusted to fit the required specifications. The program not only assists in the theoretical design, but also aids in parts selection and determines component values.OSCILLATOR/PLL PHASE NOISEA PLL is a type of oscillator, and in any oscillator design, frequency stability is of critical importance. We are interested in both long-term and short-term stability. Long-term frequencystability is concerned with how the output signal varies over a long period of time (hours, days, or months). It is usually specified as the ratio, Δf/f for a given period of time, expressed as a percentage or in dB.Short-term stability, on the other hand, is concerned with variations that occur over a period of seconds or less. These variations can be random or periodic. A spectrum analyzer can be used to examine the short-term stability of a signal. Figure 5 shows a typical spectrum, with random and discrete frequency components causing a broad skirt and spurious peaks.o mOUTPUTFREQUENCYFigure 5: Oscillator Phase Noise and SpursThe discrete spurious components could be caused by known clock frequencies in the signal source, power line interference, and mixer products. The broadening caused by random noise fluctuation is due to phase noise. It can be the result of thermal noise, shot noise, and/or flicker noise in active and passive devices.The phase noise spectrum of an oscillator shows the noise power in a 1 Hz bandwidth as a function of frequency. Phase noise is defined as the ratio of the noise in a 1 Hz bandwidth at a specified frequency offset, fm, to the oscillator signal amplitude at frequency f o.It is customary to characterize an oscillator in terms of its single-sideband phase noise as shown in Figure 6, where the phase noise in dBc/Hz is plotted as a function of frequency offset, f m, with the frequency axis on a log scale. Note the actual curve is approximated by a number of regions, each having a slope of 1/f X, where x = 0 corresponds to the "white" phase noise region (slope = 0 dB/decade), and x = 1, corresponds to the "flicker" phase noise region (slope = –20 dB/decade). There are also regions where x = 2, 3, 4, and these regions occur progressively closer to the carrier frequency.PHASE NOISE (dBc/Hz)FREQUENCY OFFSET, f m , (LOG SCALE)f OUTPUTFigure 6: Phase Noise in dBc/Hz Versus Frequency Offset from Output FrequencyNote that the phase noise curve is somewhat analogous to the input voltage noise spectral density of an amplifier. Like amplifier voltage noise, low 1/f corner frequencies are highly desirable in an oscillator.In some cases, it is useful to convert phase noise into time jitter. This can be done by basically integrating the phase noise plot over the desired frequency range. (See Tutorial MT-008, Converting Oscillator Phase Noise to Time Jitter ). The ability to perform this conversion between phase noise and time jitter is especially useful when using the PLL output to drive an ADC sampling clock. Once the time jitter is known, its effect on the overall ADC SNR can be evaluated. The ADIsimPLL™ program (to be discussed shortly) performs the conversion between phase noise and time jitter.FRACTIONAL-N PHASE LOCKED LOOPSFractional-N PLLs have been utilized since the 1970s. As has been discussed, the resolution at the output of an integer-N PLL is limited to steps of the PFD input frequency as shown in Figure 7A, where the PFD input is 0.2 MHz.Fractional-N allows the resolution at the PLL output to be reduced to small fractions of the PFD frequency as shown in Figure 7B, where the PFD input frequency is 1 MHz. It is possible to generate output frequencies with resolutions of 100s of Hz, while maintaining a high PFD frequency. As a result the N-value is significantly less than for integer-N."N" = N INTEGER + N FRACTIONN MODULUS= 900 +N FRACTION5Figure 7: Integer-N Compared to Fractional-N SynthesizerSince noise at the charge pump is multiplied up to the output at a rate of 20logN, significant improvements in phase noise are possible. For a GSM900 system, the fractional-N ADF4252 offers phase noise performance of –103 dBc/Hz, compared with –93 dBc/Hz for the ADF4106 integer-N PLL.Also offering a significant advantage is the lock-time improvement made possible by fractional-N. The PFD frequency set to 20 MHz and loop bandwidth of 150 kHz will allow the synthesizer to jump 30 MHz in less than 30 µs. Current base stations require two PLL blocks to ensure that LOs can meet the timing requirements for transmissions. With the super-fast lock times of fractional-N, future synthesizers will have lock time specs that allow the two “ping-pong” PLLs to be replaced with a single fractional-N PLL block.The downside of fractional-N PLLs is higher spurious levels. A fractional-N divide by 900.2 (See Figure 7B) consists of the N-divider dividing by 900 80% of the time, and by 901 20% of the time. The average division is correct, but the instantaneous division is incorrect. Because of this, the PFD and charge pump are constantly trying to correct for instantaneous phase errors. The heavy digital activity of the sigma-delta modulator, which provides the averaging function, creates spurious components at the output. The digital noise, combined with inaccuracies in matching the hard-working charge pump, results in spurious levels greater than those allowable by most communications standards. Only recently have fractional-N parts, such as the ADF4252, made the necessary improvements in spurious performance to allow designers to consider their use in traditional integer-N markets.SIMPLIFYING PLL DESIGN USING ADIsimPLL™The ADIsimPLL™ software is a complete PLL design package which can be downloaded from the Analog Devices' website. The software has a user-friendly graphical interface, and a complete comprehensive tutorial for first-time users.Traditionally, PLL Synthesizer design relied on published application notes to assist in the design of the PLL loop filter. It was necessary to build prototype circuits to determine key performance parameters such as lock time, phase noise, and reference spurious levels. Optimization was accomplished by "tweaking" component values on the bench and repeating lengthy measurements.ADIsimPLL both streamlines and improves the traditional design process. Starting with the “new PLL wizard,” a designer constructs a PLL by specifying the frequency requirements of the PLL, selecting an integer-N or fractional-N implementation, and then choosing from a library of PLL chips, library or custom VCO, and a loop filter from a range of topologies. The program designs a loop filter and displays key parameters including phase noise, reference spurs, lock time, lock detect performance, and others.ADIsimPLL operates with spreadsheet-like simplicity and interactivity. The full range of design parameters such as loop bandwidth, phase margin, VCO sensitivity, and component values can be altered with real-time updates of the simulation results. This allows the user to easily optimize the design for specific requirements. Varying the bandwidth, for example, enables the user to observe the tradeoff between lock time and phase noise in real-time, and with bench-measurement accuracy.ADIsimPLL includes accurate models for phase noise, enabling reliable prediction of the synthesizer closed-loop phase noise. Users report excellent correlation between simulation and measurement. If required, the designer can work directly at the component level and observe the effects of varying individual component values.The basic design process using ADIsimPLL can be summarized as follows:1.Choose reference frequency, output frequency range, and channel spacing2.Select PLL chip from list3.Select VCO4.Select loop filter configuration5.Select loop filter bandwidth and phase margin6.Run simulation7.Evaluate time and frequency domain results8.OptimizeADIsimPLL works for integer-N or fractional-N PLLs, but does not simulate fractional-N spurs. Phase noise prediction for fractional-N devices assumes the device is operating in the "lowest phase noise" mode.REFERENCES1.Mike Curtin and Paul O'Brien, "Phase-Locked Loops for High-Frequency Receivers and Transmitters"Part 1, Analog Dialogue, 33-3, Analog Devices, 1999Part 2, Analog Dialogue, 33-5, Analog Devices, 1999Part 3, Analog Dialogue, 33-7, Analog Devices, 19992.Roland E. Best, Phase Locked Loops, 5th Edition, McGraw-Hill, 2003, ISBN: 0071412018.3.Floyd M. Gardner, Phaselock Techniques, 2nd Edition, John Wiley, 1979, ISBN: 0471042943.4.Dean Banerjee, PLL Performance, Simulation and Design, 3rd Edition, Dean Banerjee Publications, 2003,ISBN: 0970820712 .5.Bar-Giora Goldberg, Digital Frequency Synthesis Demystified, Newnes, 1999, ISBN: 1878707477.6.Brendan Daly, "Comparing Integer-N and Fractional-N Synthesizers," Microwaves and RF, September2001, pp. 210-215.7.Adrian Fox, "Ask The Applications Engineer-30 (Discussion of PLLs)," Analog Dialogue, 36-3, 2002.8.Hank Zumbahlen, Basic Linear Design, Analog Devices, 2006, ISBN: 0-915550-28-1. Also available asLinear Circuit Design Handbook, Elsevier-Newnes, 2008, ISBN-10: 0750687037, ISBN-13: 978-0750687034. Chapter 4.9.Walt Kester, Analog-Digital Conversion, Analog Devices, 2004, ISBN 0-916550-27-3, Chapter 6. Alsoavailable as The Data Conversion Handbook, Elsevier/Newnes, 2005, ISBN 0-7506-7841-0, Chapter 6.10.Walt Kester, "Converting Oscillator Phase Noise to Time Jitter," Tutorial MT-008, Analog Devices11.Design Tool: ADIsimPLL, Analog Devices, Inc.12.Analog Devices PLL Product Portfolio: /pllCopyright 2009, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application of customers’ products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Tutorials.。
