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BQ3285LDSS;中文规格书,Datasheet资料

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Features

®ACPI-compliantday-of-monthalarm

®Directclock/calendarreplace-mentforIBM®AT-compatible

computersandotherapplications

®2.7–5.5Voperation(bq3285LD);4.5–5.5Voperation(bq3285ED)

®242bytesofgeneralnonvolatilestorage

®Dedicated32.768kHzoutputpin

®Systemwake-upcapability—alarminterruptoutputactivein

battery-backupmode

®Lessthan0.55µAloadunderbat-teryoperation

®SelectableIntelorMotorolabustiming

®24-pinplasticSSOPGeneralDescription

TheCMOSbq3285ED/LDisalow-

powermicroprocessorperipheralpro-

vidingatime-of-dayclockand100-

yearcalendarwithalarmfeatures

andbatteryoperation.Thearchitec-

tureisbasedonthebq3285/7RTC

withaddedfeatures:low-voltageop-

eration,32.768kHzoutput,128addi-

tionalbytesofCMOS,andaday-of-

monthalarmtobecompliantwith

theACPIRTCspecification.

A32.768kHzoutputisavailablefor

sustainingpower-managementac-

tivities.Thebq3285ED/LD32kHz

outputisalwaysonwheneverVCCis

valid.InVCCstandbymode,the

32kHzisactive,andthebq3285LD

typicallydraws100µAwhilethe

bq3285EDtypicallydraws300µA.

Wake-upcapabilityisprovidedby

analarminterrupt,whichisactive

inbattery-backupmode.Inbattery-

backupmode,currentdrainisless

than550nA.Thebq3285ED/LDwrite-protectsthe

clock,calendar,andstorageregisters

duringpowerfailure.Abackup

batterythenmaintainsdataandoper-

atestheclockandcalendar.

Thebq3285ED/LDisafullycom-

patiblereal-timeclockforIBMAT-

compatiblecomputersandotherap-

plications.Theonlyexternalcompo-

nentsarea32.768kHzcrystalanda

backupbattery.

Thebq3285EDisintendedforusein

5Vsystems.Thebq3285LDisin-

tendedforusein3Vsystems;the

bq3285LD,however,mayalsooper-

ateat5Vandthengointoa3V

power-downstate,write-protecting

asifina3Vsystem.

1Real-TimeClock(RTC)bq3285ED/LD

1

PN3285ED/LD.eps 24-Pin SSOP

23

4 5

6

7

824

2322

21

20

19

18

17

9

1016

15

11

1214

13VCC

32kEXTRAM

BCINT

RST

DS

VSSR/W

AS

CSMOT

X1X2

AD0AD1AD2AD3AD4AD5AD6

AD7VSSRCLPinConnectionsPinNames

July1997AD0–AD7Multiplexedaddress/

datainput/output

MOTBustypeselectinput

CSChipselectinput

ASAddressstrobeinput

DSDatastrobeinput

R/WRead/writeinput

INTInterruptrequestoutput

RSTResetinput32K32.768kHzoutput

EXTRAMExtendedRAMenable

RCLRAMclearinput

BC3Vbackupcellinput

X1–X2Crystalinputs

VCCPowersupply

VSSGround

http://oneic.com/BlockDiagram

PinDescriptions

MOTBustypeselectinput

MOTselectsbustimingforeitherMotorola

orIntelarchitecture.Thispinshouldbe

tiedtoVCCforMotorolatimingortoVSSfor

Inteltiming(seeTable1).Thesetting

shouldnotbechangedduringsystemopera-

tion.MOTisinternallypulledlowbya30K

Ωresistor.AD0–AD7Multiplexedaddress/data

input/output

Thebq3285ED/LDbuscycleconsistsoftwo

phases:theaddressphaseandthedata-

transferphase.Theaddressphasepre-

cedesthedata-transferphase.Duringthe

addressphase,anaddressplacedon

AD0–AD7andEXTRAMislatchedintothe

bq3285ED/LDonthefallingedgeoftheAS

signal.Duringthedata-transferphaseof

thebuscycle,theAD0–AD7pinsserveasa

bidirectionaldatabus.

ASAddressstrobeinput

ASservestodemultiplextheaddress/data

bus.ThefallingedgeofASlatchesthead-

dressonAD0–AD7andEXTRAM.Thisde-

multiplexingprocessisindependentoftheCSsignal.ForDIPandSOICpackages

withMOT=VSS,theASinputisprovideda

signalsimilartoALEinanIntel-basedsys-tem.

2bq3285ED/LDBus

TypeMOT

LevelDS

EquivalentR/W

EquivalentAS

Equivalent

MotorolaVCCDS,E,or

Φ2R/WAS

IntelVSSRD,

MEMR,or

I/ORWR,

MEMW,or

I/OWALETable1.BusSetup

BD328501.eps PBus I/Fµ

Power-FailControlStorage Registers(114 Bytes)User Buffer(14 Bytes)

VOUTClock/Calendar, Alarmand Control BytesTime-BaseOscillator

Control/StatusRegisters÷ 8÷ 64÷ 64

16 1 MUX:

InteruptGenerator

Control/CalendarUpdate

VCCDSAD0–AD7CSMOT32K

INTX1

X2

34

RST

R/W

AS

Storage Registers(128 Bytes)RCL

EXTRAM

WriteProtectCS

BC32KDriver

July1997

http://oneic.com/DSDatastrobeinput

WhenMOT=VCC,DScontrolsdatatrans-

ferduringabq3285ED/LDbuscycle.Dur-

ingareadcycle,thebq3285ED/LDdrives

thebusaftertherisingedgeonDS.During

awritecycle,thefallingedgeonDSisused

tolatchwritedataintothechip.

WhenMOT=VSS,theDSinputisprovided

asignalsimilartoRD,MEMR,orI/ORin

anIntel-basedsystem.Thefallingedgeon

DSisusedtoenabletheoutputsduringa

readcycle.R/WRead/writeinput

WhenMOT=VCC,thelevelonR/Widenti-

fiesthedirectionofdatatransfer.Ahigh

levelonR/Windicatesareadbuscycle,

whereasalowonthispinindicatesawrite

buscycle.

WhenMOT=VSS,R/Wisprovidedasignal

similartoWR,MEMW,orI/OWinanIntel-

basedsystem.TherisingedgeonR/W

latchesdataintothebq3285ED/LD.CSChipselectinputCSshouldbedrivenlowandheldstable

duringthedata-transferphaseofabuscy-

cleaccessingthebq3285ED/LD.INTInterruptrequestoutputINTisanopen-drainoutput.Thisallows

alarmINTtobevalidinbattery-backup

mode.Tousethisfeature,connectINT

througharesistortoapowersupplyother

thanVCC.INTisassertedlowwhenany

eventflagissetandthecorresponding

eventenablebitisalsoset.INTbecomes

high-impedancewheneverregisterCisread

(seetheControl/StatusRegisterssection).

32K32.768kHzoutput

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0394850005;中文规格书,Datasheet资料

0394850005;中文规格书,Datasheet资料

This document was generated on 08/17/2012PLEASE CHECK FOR LATEST PART INFORMATIONPart Number:39485-0005Status:ActiveDescription:4.00mm Pitch Positive Locking Terminal Block PCB Header, Tin Plating, 5 CircuitsDocuments:3D ModelProduct Specification PS-39484-001 (PDF)Drawing (PDF)RoHS Certificate of Compliance (PDF)GeneralProduct FamilyTerminal BlocksSeries39485ApplicationWire-to-BoardComponent TypePCB HeaderProduct NameEurostyle™PluggableTypeEuro BlockUPC883906382759PhysicalCircuits (Loaded)5Circuits (maximum)5Color - ResinBlackEntry AngleVertical (Top Entry)Lock to Mating PartYesMaterial - MetalCopper AlloyMaterial - Plating MatingTinMaterial - ResinNylonNumber of Rows1OrientationVerticalPC Tail Length3.20mmPCB RetentionNonePanel MountNoPitch - Mating Interface4.00mmPitch - Termination Interface4.00mmPolarized to Mating PartYesShroudedNoStackableNoSurface Mount Compatible (SMC)YesTemperature Range - Operating-40°C to +140°CWire Size AWGN/AElectricalCurrent - Maximum per Contact10AVoltage - Maximum300VMaterial InfoReference - Drawing NumbersProduct SpecificationPS-39484-001Sales DrawingSD-39485-001Seriesimage - Reference onlyEU RoHSChina RoHSELV and RoHSCompliantREACH SVHCNot ReviewedLow-Halogen StatusNot ReviewedNeed more information on productenvironmental compliance?Email productcompliance@For a multiple part number RoHS Certificate ofCompliance, click herePlease visit the Contact Us section for anynon-product compliance questions.Search Parts in this Series39485SeriesMates With39484 4.00mm Pitch tin plated plugs

BQ30Z50EVM;中文规格书,Datasheet资料

BQ30Z50EVM;中文规格书,Datasheet资料

User'sGuide

SLUU432–January2012

bq30z50-R1EVMSBS1.1ImpedanceTrack™Enabled

BatteryManagementSolution

Thebq30z50-R1EVMisacompleteevaluationsystemforthebq30z50-R1/bq29412batterymanagementsolution.Thissystemincludesonebq30z50-R1/bq29412circuitmodule,acurrentsenseresistor,fourthermistors,andalinktoWindows®-basedPCsoftware.

Thecircuitmoduleincludesonebq30z50-R1IC,onebq29412IC,andallotheronboardcomponentsnecessarytomonitorandpredictcapacity,performcellbalancing,monitorcriticalparameters,protectthecellsfromovercharge,overdischarge,shortcircuit,andovercurrentin2-series,3-series,or4-seriescellLi-IonorLi-Polymerbatterypacks.Thecircuitmoduleconnectsdirectlyacrossthecellsinabattery.

WiththeEV2300orEV2400interfaceboardandsoftware,userscanreadthebq30z50-R1dataregisters,programthechipsetfordifferentpackconfigurations,logcyclingdataforfurtherevaluation,andevaluatetheoverallfunctionalityofthebq30z50-R1/bq29412solutionunderdifferentchargeanddischargeconditions.

BQ3285ES;BQ3285ESS;BQ3285ESSTR;BQ3285ESSTRG4;BQ3285ESTR;中文规格书,Datasheet资料

BQ3285ES;BQ3285ESS;BQ3285ESSTR;BQ3285ESSTRG4;BQ3285ESTR;中文规格书,Datasheet资料

Features

®Direct clock/calendar replace-ment for IBM®AT-compatible

computers and other applications

®Functionally compatible with theDS1285

-Closely matches MC146818A

pin configuration

®2.7–3.6V operation (bq3285L);4.5–5.5V operation (bq3285E)

®242 bytes of general nonvolatilestorage

®32.768kHz output for power man-agement

®System wake-up capability—alarm interrupt output active in

battery-backup mode

®Less than 0.5µA load under bat-tery operation

®Selectable Intel or Motorola bustiming

®14 bytes for clock/calendar andcontrol®BCD or binary format for clockand calendar data

®Calendar in day of the week,dayof the month,months,and years,

with automatic leap-year adjust-

ment

®Time of day in seconds,minutes,and hours

-12- or 24-hour format

-Optional daylight saving

adjustment

®Programmable square wave out-put

®Three individually maskable in-terrupt event flags:

W25Q128BVEIG;中文规格书,Datasheet资料

W25Q128BVEIG;中文规格书,Datasheet资料

W25Q128BV

Publication Release Date: April 18, 2012 - 1 - Revision G 3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI

/W25Q128BV

- 2 - Table of Contents 1. GENERAL DESCRIPTION ............................................................................................................... 5 2. FEATURES ....................................................................................................................................... 5 3. PACKAGE TYPES AND PIN CONFIGURATIONS ........................................................................... 6 3.1 Pad Configuration WSON 8x6-mm ...................................................................................... 6 3.2 Pad Description WSON 8x6-mm .......................................................................................... 6 3.3 Pin Configuration SOIC 300-mil ........................................................................................... 7 3.4 Pin Description SOIC 300-mil ............................................................................................... 7 3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array) ................................................. 8 3.6 Ball Description TFBGA 8x6-mm ......................................................................................... 8 4. PIN DESCRIPTIONS ........................................................................................................................ 9 4.1 Chip Select (/CS) .................................................................................................................. 9 4.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 9 4.3 Write Protect (/WP) .............................................................................................................. 9 4.4 HOLD (/HOLD) ..................................................................................................................... 9 4.5 Serial Clock (CLK) ................................................................................................................ 9 5. BLOCK DIAGRAM .......................................................................................................................... 10 6. FUNCTIONAL DESCRIPTIONS ..................................................................................................... 11 6.1 SPI OPERATIONS ............................................................................................................. 11 6.1.1 Standard SPI Instructions ..................................................................................................... 11 6.1.2 Dual SPI Instructions ............................................................................................................ 11 6.1.3 Quad SPI Instructions ........................................................................................................... 11 6.1.4 Hold Function ....................................................................................................................... 11 6.2 WRITE PROTECTION ....................................................................................................... 12 6.2.1 Write Protect Features ......................................................................................................... 12 7. STATUS REGISTERS AND INSTRUCTIONS ............................................................................... 13 7.1 STATUS REGISTERS ........................................................................................................ 13 7.1.1 BUSY Status (BUSY) ............................................................................................................ 13 7.1.2 Write Enable Latch Status (WEL) ........................................................................................ 13 7.1.3 Block Protect Bits (BP2, BP1, BP0) ...................................................................................... 13 7.1.4 Top/Bottom Block Protect Bit (TB) ........................................................................................ 13 7.1.5 Sector/Block Protect Bit (SEC) ............................................................................................. 13 7.1.6 Complement Protect Bit (CMP) ............................................................................................ 14 7.1.7 Status Register Protect Bits (SRP1, SRP0) .......................................................................... 14 7.1.8 Erase/Program Suspend Status (SUS) ................................................................................ 14 7.1.9 Security Register Lock Bits (LB3, LB2, LB1) ........................................................................ 14 7.1.10 Quad Enable Bit (QE) ......................................................................................................... 15 7.1.11 Status Register Memory Protection (CMP = 0) ................................................................... 16