开关电源制作设计(电路原理图+PCB)

TND313/DRev 3, Sep-11High-Efficiency305 W ATX Reference Design Documentation Package© 2011 ON Semiconductor.Disclaimer: ON Semiconductor is providing this reference design documentation package “AS IS” and the recipient assumes all risk associated with the use and/or commercialization of this design package. No licenses to ON Semiconductor’s or any third party’s Intellectual Property is conveyed by the transfer of this documentation. This reference design documentation package is provided only to assist the customers in evaluation and feasibility assessment of the reference design. The design intent is to demonstrate that efficiencies beyond 80% are achievable cost effectively utilizing ON Semiconductor provided ICs and discrete components in conjunction with other inexpensive components. It is expected that users may make further refinements to meet specific performance goals.Table of Contents1.Overview (6)2.Specifications (7)3.Architecture Overview (8)4.Performance Results (13)5.Evaluation Guidelines (23)6.Schematics (24)7.Parts List (29)8.Critical Component Information (35)9.Resources/Contact Information (35)10.Appendix (36)List of TablesTable 1: Target Specifications (7)Table 2: Load matrix for efficiency measurements (13)Table 3: Load matrix for cross regulation measurements (15)Table 4: Transient load conditions (18)List of FiguresFigure 1: Reference Design Architecture Block Diagram (7)Figure 2: One switch forward topology and associated waveform (9)Figure 3: Active clamp forward topology and associated waveform (11)Figure 4: Efficiency vs percentage load from 20% to full load (13)Figure 5: Power factor vs percentage load (14)Figure 6: Efficiency vs percentage load from 5% to full load (14)Figure 7: 5 V and 5 V SBY outputs cross regulation vs load conditions (16)Figure 8: 3.3 V output cross regulation vs load conditions (16)Figure 9: 12 V1 and 12 V2 outputs cross regulation vs load conditions (17)Figure 10: -12 V output cross regulation vs load conditions (17)Figure 11: 5 V output transient load response (18)Figure 12: 12 V1 output transient load response (18)Figure 13: 12 V2 output transient load response (19)Figure 14: 3.3 V output transient load response (19)Figure 15: 5 V output voltage ripple at full load (20)Figure 16: 3.3 V output voltage ripple at full load (20)Figure 17: 12 V1 output voltage ripple at full load (20)Figure 18: 12 V2 output voltage ripple at full load (21)Figure 19: -12 V output voltage ripple at full load (21)Figure 20: 5 V SBY output voltage ripple at full load (21)Figure 21: Holdup time at full load (22)Figure 22: Input inrush current (22)Figure 23: ATX solution boards in ATX enclosure (24)Figure 24: PFC controller PCB board schematic (25)Figure 25: EMC component board (25)Figure 26: Active clamp controller PCB board schematic (26)Figure 27: Supervisory and 3.3 V post regulator controller PCB board schematic (27)Figure 28: Main PCB board schematic PFC and standby section (27)Figure 29: Main PCB board schematic active clamp stage section (28)Figure 30: Main PCB board schematic 3.3 V post regulator section (28)1. OverviewON Semiconductor was the first Semiconductor company to provide an 80 PLUS open reference design for an ATX Power Supply in 2005. This 1st generation reference design, was certified and met all the requirements of the 80 PLUS program. Following on this successful 1st generation design, ON Semiconductor is introducing its improved 2nd Generation reference design. This 2nd generation design utilizes newer ICs from ON Semiconductor that enable this design to exceed 80% efficiency starting at 20% load across different line conditions with ample margin to spare.This reference document provides the details behind this 2nd generation design. The design manual provides a detailed view of the performance achieved with this design in terms of efficiency, performance, thermals and other key parameters. In addition, a detailed list of the bill-of-materials (BOM) is also provided. ON Semiconductor will also be able to provide technical support to help our customers design and manufacture a similar ATX power supply customized to meet their specific requirements.The results achieved in this 2nd generation design were possible due to the use of advanced new components from ON Semiconductor. These new ICs not only speeded up the overall development cycle for this new design, but also helped achieve the high efficiencies while at the same time keeping a check on the overall cost. With the use of these new ICs, ON Semiconductor has proven again that the emerging requirements for high efficiency desktop power supplies can be met and further, can be optimized to meet specific performance vs. cost goals.This 2nd generation design consists of a single PCB designed to fit into the standard ATX enclosure along with a fan. Figure 1 below presents the overall architecture employed in this design – detailed schematics are included later in this design manual. As seen in figure 1, this design employed an Active Clamp forward topology using the new, highly integrated Active Clamp Controller IC from ON Semiconductor – NCP1562. A Continuous Conduction Mode (CCM) Power Factor Correction (PFC) IC was employed for the active PFC circuit. This IC, the NCP1653 provides an integrated, robust and cost-effective PFC solution. The standby controller, NCP1027, is an optimized IC for the ATX power supply and incorporates a high-voltage MOSFET. On the secondary side, this architecture employs a post regulator approach for generating the 3.3 V output. This is an alternative approach to the traditional magnetic amplifier (Mag Amp) approach. Though ON Semiconductor believes that this post regulator approach provides the highest efficiency amongst the different means of generating these outputs in the power supply, it is important to note that if the customer desires to use a different approach, that is possible – i.e. a similar design can be developed that utilizes all the other pieces of this architecture without the post regulator and still achieve very good results.With the introduction of this 2nd generation, high-efficiency ATX Power Supply, ON Semiconductor has shown that with judicious choice of design tradeoffs, optimum performance is achieved at minimum cost.Figure 1: Reference Design Architecture Block Diagram2. SpecificationsThe design closely follows the ATX12V version 2.2 power supply guidelines and specifications available from , unless otherwise noted. For instance, our reference design had a target of +/- 5% tolerance for both the 5 V and 5 Vstandby outputs. Further, the efficiency targets for the 80 PLUS program and the EPA’s Energy Star specification – Energy Star Program Requirements for Computers, version 4.0 that is set to take effect from July 20, 2007 – were targeted. Key specifications are included in Table 1 below.Output Current Tolerance (%) Ripple/Noise(mV) Min. (A) Max (A)5 V 0.3 22 ± 3.350 5 V standby 0.0 2.5 ± 3.350 12 V 1.0 18 ± 5.0120 - 12 V 0.0 1 ± 10120 Table 1: Target SpecificationsTarget specifications for other key parameters of the reference design include: -Efficiency: Minimum efficiency of 80% for 20%, 50% and 100% of rated output load conditions as defined by the 80 PLUS requirements as well as the Energy Star specification.-Power Factor: Power factor of 0.9 or greater at 100 % load.-Input Voltage: Universal Mains – 90 Vac to 265 Vac, 47 – 63 M Hz.-Output Power: Total maximum output power is 305 W.-Safety Features: As per the ATX12V specification, this design includes safety features such as OVP, UVP, and OCP.-This design meets the IEC1000-3-2 requirements over the input line range and under full load conditions.-This converter was designed for a 20 ms minimum Hold-up time.-Physical dimensions: This converter is designed to fit into the standard ATX enclosure with dimensions of 150 mm x 140 mm x 86 mm.3. Architecture OverviewBefore discussing the power supply architecture of the Generation 2 design, it is worth reiterating the design goals. We are tasked with providing a flexible power platform, which is required to have the lowest cost and highest efficiency that can be packaged in a small volume. The architecture must deliver a minimum of 80% efficiency over a wide range of operating conditions (high-line and low-line) as well as rated output load conditions (20% load and above). In addition we require a robust design solution having low parts count to provide the same performance on a unit to unit basis in a high volume manufacturing environment.The architecture selected follows a traditional two stage conversion approach as illustrated in Figure 1. It is worth noting that in order to achieve 80% efficiency overall, the efficiency of each of the two conversion stages must exceed 90 %. The front-end is a universal input, active power factor boost stage delivering a constant output voltage of 385 V to the active clamp stage. The second stage consists of two, dc-dc converters. The first down-stream converter processes 290 W required by the system in the form of tightly regulated +/-12 V, +5 V and +3.3 V outputs. The second converter delivers 15 W of standby power to another isolated 5 V rail.ON Semiconductor has developed multiple power management controllers and MOSFET devices in support of the ATX program. Web based data sheets, design tools and technical resources are available to assist design optimization. The ICs, supporting the ATX Generation 2 platform, are the NCP1653 PFC controller, the NCP1562 active clamp controller, the NCP4330 post regulator, the NCP1027 standby controller, and the NTP48xx family of MOSFET synchronous rectifiers. It is not possible to discuss the tradeoffs involved in each conversion stage at length, but the selection of the activeclamp forward converter topology is a key one and will be covered in depth. Each controller is highly integrated and offers the lowest external parts count available.PFC StageThere are a variety of PFC topologies available. These include discontinuous conduction mode (DCM), critical conduction mode (CRM) and continuous conduction mode (CCM). At this power level, CCM is the preferred choice and the NCP1653 will implement a IEC1000-3-2 compliant, fixed frequency, peak current mode PFC boost converter with very few external components.DC to DC (Main) ConverterThe selection of the dc-dc down stream converter is at the heart of the 80% solution. The traditional work horse of the ATX market has been the single switch forward converter operating at a switching frequency of 100 kHz. The converter and its associated drain waveform are illustrated in Figure 2. This topology is robust and delivers good full load efficiency performance at minimal cost. However, as power levels increase and regulatory requirements and energy conservation agencies drive for higher efficiency under all load conditions, the single switch forward topology in its simplest form is reaching its limit.Figure 2: One switch forward topology and associated waveformThere are several technical reasons for this. First, because the main transformer is reset via an auxiliary winding across the input bus, the duty cycle is limited below 50%. Second, because of this reset mechanism there is always a dead time interval, during each converter cycle, when no power is flowing. These two constraints have negative implications on the silicon utilization of the primary switch requiring a costly, large area die to be selected. The primary switch’s conduction loss is given by (1))(*2*)(on DS R P I D conduction loss P =(1)where, D is the duty cycle, I P is the primary current and R DS(on) is the switch on resistance. The topology is a hard switched topology with the primary switch being driven on with 385 V across it each switching cycle. The capacitive switch loss are given by (2),f DS V OSS C capacitive loss P *2*21)(= (2)where, C OSS is the switch output capacitance, V DS is the drain to source voltage and f is the operating frequency. Capacitive losses dominate at light load. Hence a switch selected for full load performance will suffer at light load because of its large drain source capacitance. Reviewing these two loss equations, it becomes apparent for efficiency enhancement under both full load and light load operation, a topology is required that allows the primary switch to operate at lower current and voltage stress. As the loss terms appear as current and voltage squared, small reductions in primary current I P and switch voltage V DS significantly improve performance.The active clamp forward converter illustrated in Figure 3 represents the ultimate extension of the single switch converter and provides these benefits. Instead of using an auxiliary winding, transformer reset is achieved using a clamp capacitor and an auxiliary switch. The reset period, controlled by the auxiliary switch now extends to the interval ()S T D *1−, completely eliminating the previous dead time interval. To maintain flux balance in the main transformer core, the reset voltage across the clamp capacitor isdetermined by the expression ()D D in V −1*. The duty cycle D of the single switch forwardconverter can extend beyond 50%, limited only by the primary switch’s maximum voltage rating.Figure 3: Active clamp forward topology and associated waveformFor a given set of conditions and power throughput, operating at extended duty cycles allows for a lower primary current. This in turn allows the selection of a smaller, lower cost die. Let’s look at a design example to illustrate this point.To reduce cost, a 150 μF bulk capacitor (instead of a 470 μF conventional value) is selected to provide 20 ms of hold up time. Using the energy storage equation given by (3),()ηtime up Hold Delivered Power V V C Energy f i **2122=−= (3)where, V i and V f are the initial and final voltages of the input capacitor, respectively. The initial voltage is 385 V and converter efficiency is 90%, allows us to calculate the final voltage V f to be 250 V. In the case of a conventional single switch design, the maximum duty cycle we can practically select and avoid transformer saturation is 0.45. The switch voltage stress is 2 x 250 V. With the active clamp single switch forward, the duty cycle can be extended to 0.67 and the voltage stress on the switch is Vin / (1-D) or 3.03 x 250 V. Each converter has to process 290 / 0.9 or 322 W from the primary bulk source. At nominal 385 V bulk, the average primary current is 0.84 A. Factoring in the primary switch duty cycle D, the peak current I P in the traditional forward converter is 0.65 / 0.45 or 1.44 times larger than the active clamp approach. Based on the conduction loss equation given by (1), we see that the 1.44 ratio holds true for conduction loss in the primary switch. Put another way, we can choose a MOSFET with 44% higher R DS(on) in the active clamp topology and have the same conduction loss. This is significant, as we can achieve better silicon utilization, lower cost and lower drain capacitance. By reviewing the data sheets from high voltage MOSFET vendors, it is possible to compare output capacitance C OSS versus R DS(on) as a function of die size. For example as MOSFET resistance increases from 3.6 Ω to 4.8 Ω, the output capacitance reduces from100 pF to 70 pF. The resonant nature of the active clamp allows the switch be turned on at 300 V instead of the conventional 400 V. These two effects allow a reduction in capacitive switching loss of 39% over a conventional design. Again, a significant improvement remembering that light load efficiency is determined predominately by switching loss. The example above illustrates how small changes in switch stress can impact overall cost and performance.The same argument relating to increased duty cycle operation extends to the secondary by proportionally reducing output rectifier loss. Since the secondary loss is a dominant factor at full load, an additional efficiency improvement/ cost benefit is realized. To achieve the ultimate efficiency, synchronous rectification is required on the +12 V and +5 V outputs. The single switch active clamp forward is very suitable to drive synchronous rectifiers directly from the secondary windings without the need for expensive gate drivers or additional delay timing circuitry.To allow designers to capitalize on the benefits inherent in the active clamp topology, the NCP1562 has been developed to capture all the necessary control features within a 16 pin package. The full featured controller has been designed for tight tolerance on all parameters, including the maximum duty cycle limit and the important soft stop function. To boost efficiency and maintain tight regulation, instead of the conventional magnetic amplifier post regulated approach, the 3.3 V output is derived from the 5 Volt winding of the main transformer. The MOSFET drivers, timing, synchronization and control functions to support this output are provided by the NCP4330 controller. A 6 W improvement in the loss budget is achieved when this approach is adopted. Gate charge and R DS(on) have been optimized in the NTP48xx family of MOSFETs and provide synchronous rectification for both the 3.3 V and 5 V outputs.Standby PowerThe NCP1027 integrates a fixed frequency current mode controller and a 700 volt MOSFET. The NCP1027 is an ideal part to implement a flyback topology delivering 15 W to an isolated 5 V output. At light loads the IC will operate in skip cycle mode, thereby reducing its switching losses and delivering high efficiency throughout the load range.4. Performance ResultsThe evaluation of the reference design focused on several areas including efficiency, power factor, cross regulation and transient load response. Design optimizations may be needed to customize this reference design to meet specific requirements.The converter efficiency is measured according to the operating conditions detailed in Table 2. The converter efficiency is measured at 100 Vac, 115 Vac and 230 Vac at 50 Hz. The converter achieves over 80% efficiency with room to spare over all load conditions as shown in Figure 4. The output voltages used for the efficiency calculations are measured at the end of the power cables. The fan is disabled for measurements at or below 20% load. The fan is automatically enabled once the load exceeds 60 W or 20%. The fan is operational for 50% and 100% load measurements. Further increases in the efficiency can be obtained for 50% and 100% load conditions through fan speed control.Load Condition Output Current (A) 5 V 3.3 V 12 V1 12 V2 -12V5 V SBY 5 % 0.690 0.540 0.385 0.385 0.030 0.070 10 % 1.390 1.070 0.770 0.770 0.070 1.390 15 % 2.080 1.610 1.150 1.150 0.100 0.210 20 % 2.7802.150 1.510 1.510 0.140 0.280 50 % 6.950 5.3703.845 3.845 0.350 0.700 100 %13.900 10.7407.695 7.6950.700 1.400Figure 4: Efficiency vs percentage load from 20% to full loadThe power factor exceeds 0.9 over all operating conditions as shown in Figure 5.Figure 5: Power factor vs percentage loadIn Figure 6, the efficiency measurements are shown from 5% load to full-load. Note that neither the 80 PLUS program nor the Energy Star specification require efficiencies above 80% for any output load below 20%. However, as can be seen in Figure 6, this reference design achieved 80% efficiency down to 16 % load.Figure 6: Efficiency vs percentage load from 5% to full loadOutput voltage cross regulation is measured according to the load conditions listed in Table 3. The results of the cross regulation measurements are shown inFigure 7 through Figure 10. Included in these figures are the tolerance requirements based on the target specifications listed in Table 1. The margin for the 5 V and 5 V SBY outputs can be increased by shifting up the regulation target for the 5 V outputs. It can also be improved by changing the weight of the 12 V and 5 V outputs in the regulation circuit.Load ConditionOutput Current (A)5 V(+/-3.3%)3.3 V(+/-4%)12 V1(+/-5%)12 V2(+/-5%)-12 V(+/-10%)5 V SBY(+/-3.3%)1 0.3 0.3 0 0 0 02 73 2 2 0.1 0.53 0.3 0.3 0 0 0 0.54 0.3 3 2 2 0.1 0.55 7 0.3 2 2 0.1 0.56 4 0.3 1 1 0.2 0.27 18 12 5 5 1 2.58 18 12 1 1 0.2 2.59 4 12 5 5 1 2.510 18 0.3 5 5 1 2.511 4 0.2 1 1 0.2 0.212 14 17 8 6 1 2.513 18 17 1 1 0.2 2.514 4 17 8 6 1 2.515 18 0.3 8 6 1 2.516 4 2 5 5 0.2 117 22 17 5 5 1 2.518 4 17 5 5 1 2.519 22 2 5 5 1 2.5Table 3: Load matrix for cross regulation measurementsFigure 7: 5 V and 5 V SBY outputs cross regulation vs load conditionsFigure 8: 3.3 V output cross regulation vs load conditionsFigure 9: 12 V1 and 12 V2 outputs cross regulation vs load conditionsFigure 10: -12 V output cross regulation vs load conditionsThe 5 V, 12 V and 3.3 V outputs are evaluated independently under transient load conditions. Each output is loaded at 50% and the load is reduced to 25% or increased to 75% of the maximum rated current. The transient voltage tolerance of each of the 5 V, 12 V and 3.3 V outputs is +/- 5%. Table 4 summarizes the transient load conditions and limits for each output. Transient waveforms are shown in Figure 11 through Figure 14.Output Minimum Load (A)Nominal Load (A)Maximum Load (A)Voltage under/overshoot (V) 5 V 5.5 11 16.5 ±250mV, ≤0.5V pk-pk 3.3 V 4.25 8.5 12.75 ±170mV, ≤0.34V pk-pk 12 V1 4.5 9 13.5 ±600mV, ≤1.2V pk-pk 12 V24.5913.5±600mV, ≤1.2V pk-pkTable 4: Transient load conditionsFigure 11: 5 V output transient load responseFigure 12: 12 V1 output transient load responseΔI LOAD = 11.5 A to 5.5 AΔI LOAD = 11.5 A to 16.5 AΔI LOAD = 9 A to 4.5 AΔI LOAD = 9 A to 13.5 AFigure 13: 12 V2 output transient load responseFigure 14: 3.3 V output transient load responseAll the outputs meet the transient voltage requirements under the evaluated conditions. The ripple voltage of each output is measured at the maximum load for each output. The output ripple is measured across 10 μF/MLC parallel 1000 μF low ESR/ESL termination capacitors. The target ripple is +/- 120 mV for the 12 V outputs and 50 mV for all other outputs. Figure 15 through Figure 20 show the output voltage ripple measurements. All outputs meet the voltage ripple requirements.ΔI LOAD = 9 A to 4.5 AΔI LOAD = 9 A to 13.5 AΔI LOAD = 8.5 A to 4.25 AΔI LOAD = 8.5 A to 12.75 AFigure 15: 5 V output voltage ripple at full loadFigure 16: 3.3 V output voltage ripple at full loadFigure 17: 12 V1 output voltage ripple at full loadFigure 18: 12 V2 output voltage ripple at full loadFigure 19: -12 V output voltage ripple at full loadFigure 20: 5 V SBY output voltage ripple at full loadThe required holdup time at full load is 20 ms. Holdup time is measured from the moment the AC power is removed to when the PWR_OK signal goes low. Figure 21 shows the holdup time at full load. Channel 1 is the AC power and Channel 2 is the PWR_OK signal. Holdup time is measured at 22.5 ms.Figure 21: Holdup time at full loadThe input inrush current of the system at 230 Vac at full load is measured at 28.8 A as shown in Figure 22.Figure 22: Input inrush current5. Evaluation GuidelinesEvaluation of the reference design should be attempted only by persons who are intimately familiar with power conversion circuitry. Lethal mains referenced voltages and high dc voltages are present within the primary section of the ATX circuitry. All testing should be done using a mains high-isolation transformer to power the demonstration unit so that appropriate test equipment probing will not affect or potentially damage the test equipment or the ATX circuitry. The evaluation engineer should also avoid connecting the ground terminal of oscilloscope probes or other test probes to floating or switching nodes (e.g. the source of the active clamp MOSFET). It is not recommended to touch heat sinks, on which primary active components are mounted, to avoid the possibility of receiving RF burns or shocks. High impedance, low capacitance test probes should be used where appropriate for minimal interaction with the circuits under investigation. Particular care should be taken when probing the high impedance input pins of the NCP1653 power factor controller and the NCP1562 active clamp controller. As with all sensitive switchmode circuitry, the power supply under test should be switched off from the ac mains whenever the test probes are connected and/or disconnected.The 3.3 V output does not have a minimum load requirement and a preload resistor is included in the -12 V output.The NCP1027 standby flyback converter will be operational as long as there is ac mains voltage applied to the system. This auxiliary converter can be evaluated by merely applying the mains voltage to the board. The supervisory IC enable input and monitoring circuitry will have to be disabled. The supervisory circuitry will normally cause a shutdown of the PFC (and the main converter) if the 3.3 V, the 5 V and the 12 V outputs are not sensed at their nominal voltage.The evaluating engineer should also be aware of the idiosyncrasies of constant current type electronic loads when powering up the ATX demonstration unit. If the loads are adjusted to be close to the ATX’s maximum rated output power, the unit could shut down at turn on due to the instantaneous overloading effect of the constant current loads. As a consequence, electronic loads should be set to constant resistance mode or rheostats should be used for loads. The other alternative is to start the supply at light to medium load and then increase the constant current electronic loads to the desired level.The board is designed to fit in a traditional ATX enclosure as shown in Figure23.Figure 23: ATX solution boards in ATX enclosure6. SchematicsThe power supply is implemented using a single sided PCB board. Added flexibility is provided by using daughter cards for the PFC (NCP1653), active clamp (NCP1562) controllers. A PCB board is also used for the 3.3 V post regulator (NCP4330) and supervisory controllers. This allows the use of newer generation controllers without the need of a complete re-layout of the main board. An additional daughter card is used for EMC components. The individual PCB board schematics are shown in Figure 24 through Figure 27.The schematic of the main PCB board is divided in three sections: PFC & standby section, active clamp section, and the post regulator section as shown in Figure 28 through Figure 30, respectively.Figure 24: PFC controller PCB board schematicFigure 25: EMC component boardFigure 27: Supervisory and 3.3 V post regulator controller PCB board schematicFigure 28: Main PCB board schematic PFC and standby sectionFigure 29: Main PCB board schematic active clamp stage sectionFigure 30: Main PCB board schematic 3.3 V post regulator section7. Parts ListThe bill of materials (BOM) for the design is provided in this section. To reflect theschematics shown in the previous section, the BOM have also been broken into differentsections and provided in separate tables – Table 5 through Table 9.It should be noted that a number of components used during the development cycle werebased on availability. As a result, further cost reductions and better inventorymanagement can be achieved by component standardization. IE, the unique part numberscan be SIGNIFICANTLY reduced by standardization and re-use of component valuesand case sizes. This will result in a lower cost BOM and better inventory management.Description Part Numbers Qty 0.1µF, ±10%, 500V, X7R, Case Size 1812 VJ1812Y104KXEAT 3 0.1µF, ±10%, 50V, X7R, Case Size1206 B37872K5104K060 18 0.1µF, ±20%,300VAC, Interference Suppression CapX2 PHE840EB6100MB05R17 2 0.22uF, ±20% ,300VAC, Interference Suppression CapX2 PHE840EX6220MB06R17 1 270µF, ±20%, 400V, -40°C to +85°C, B43501 series , Snap-In, Pitch 10mm B43501A9277M000 1 100pF, ±10%, 1kVDC,High voltage ceramic disc Capacitor, -25°C to +85°C DEBB33A101KC1B 2 100pF, ±5%, 50V, COG, Case Size1206 B37871K5101J060 1 1nF, ±20% , 100V , Stacked-film capacitor, MMK series , 5mm Pitch MMK5 102M100J01L4 BULK 2 1nF, ±10%, 1kVDC,High voltage ceramic disc Capacitor,-25°C to +85°C DEBB33A102KA2B 2 1nF, ±20%,, 440VAC,Interference Suppression CapY1 PME294RB4100MR30 2 1nF,±20%, ,440/250VAC,Interference Suppression CapX1/Y2 2252 812 35 027 1 1nF, ±10%, 100V, COG, Case Size1206 B37871K1102J560 5 4.7nF, ±10%, 1kVDC, High voltage ceramic disc Capacitor, -25°C to +85°C DEBB33A472KA3B 1 4.7nF,±10% ,440/250VAC,Interference Suppression CapX1/Y2 2252 812 35 427 1 10nF, ±20% , 100V , Stacked-film capacitor, MMK series , 5mm Pitch MMK5 103M100J01L4 BULK 1 10nF, ±10%, 50V, X7R, Case Size1206 B37872K5103K060 1 22nF, ±20% , 100V , Stacked-film capacitor, MMK series , 5mm Pitch MMK5 223M100J01L4 BULK 1 2n2F, ±5%, 50V, COG, Case Size1206 B37871K5222J060 1 470pF, ±5%, 50V, COG, Case Size1206 B37871K5471J060 1 10µF, ±20%, 16V,-40°C to +85°C, Type VR, Radial, Pitch 2mm, Pb Free UVR1C100MDD 4 220µF, ±20%, 25V,-40°C to +85°C, Type VR, Radial, Pitch 3.5mm, Pb Free UVR1E221MPD 1 3300µF, ±20%, 10V,-40°C to +85°C, Type VR, Radial, Pitch 5mm, Pb Free UVR1A332MHD 1 47µF, ±20%, 25V,-40°C to +85°C, Type VR, Radial, Pitch 2mm, Pb Free UVR1E470MDD 1 2200µF, ±20%, 10V,-40°C to +85°C, Type PM, Radial, Pitch 5mm, Pb Free UPM1A222MHD 2 220µF, ±20%, 25V,-40°C to +85°C, Type PW, Radial, Pitch 3.5mm, Pb Free UPW1E221MPD 2 470E, ±1%, 0.25W, Case Size 1206 MCR18 EZH F-4700 1 0.2E, ±1%,1W, Case Size 2010 CRL1206-FW-0R20E_ 3 0E022, ±5%, 3W,Wire Wound Resister BSI680E022±5%±100ppm/°C 1 100E, ±1%, 0.25W, Case Size 1206 MCR18 EZH F-1000 1 100E, ±1%, 0.25W, MFR EROS2CHF1000 2 10E0, ±1%, 0.25W, Case Size 1206 MCR18 EZH F-10R0 2 10E, ±1%, 0.5W, Case Size 2010 MCR50-JZH-J 10R0 5。

开关电源从原理图到PCB设计的流程解析描述一、从原理图到PCB的设计流程建立元件参数-输入原理网表-设计参数设置-手工布局-手工布线-验证设计-复查-CAM输出。

二、参数设置相邻导线间距必须能满足电气安全要求，而且为了便于操作和生产，间距也应尽量宽些。

最小间距至少要能适合承受的电压，在布线密度较低时，信号线的间距可适当地加大，对高、低电平悬殊的信号线应尽可能地短且加大间距，一般情况下将走线间距设为8mil。

焊盘内孔边缘到印制板边的距离要大于1mm，这样可以避免加工时导致焊盘缺损。

当与焊盘连接的走线较细时，要将焊盘与走线之间的连接设计成水滴状，这样的好处是焊盘不容易起皮，而是走线与焊盘不易断开。

三、元器件布局实践证明，即使电路原理图设计正确，印制电路板设计不当，也会对电子设备的可靠性产生不利影响。

例如，如果印制板两条细平行线靠得很近，则会形成信号波形的延迟，在传输线的终端形成反射噪声;由于电源、地线的考虑不周到而引起的干扰，会使产品的性能下降，因此，在设计印制电路板的时候，应注意采用正确的方法。

每一个开关电源都有四个电流回路：（1）。

电源开关交流回路（2）。

输出整流交流回路（3）。

输入信号源电流回路（4）。

输出负载电流回路输入回路通过一个近似直流的电流对输入电容充电，滤波电容主要起到一个宽带储能作用;类似地，输出滤波电容也用来储存来自输出整流器的高频能量，同时消除输出负载回路的直流能量。

所以，输入和输出滤波电容的接线端十分重要，输入及输出电流回路应分别只从滤波电容的接线端连接到电源;如果在输入/输出回路和电源开关/整流回路之间的连接无法与电容的接线端直接相连，交流能量将由输入或输出滤波电容并辐射到环境中去。

电源开关交流回路和整流器的交流回路包含高幅梯形电流，这些电流中谐波成分很高，其频率远大于开关基频，峰值幅度可高达持续输入/输出直流电流幅度的5倍，过渡时间通常约为50ns。

这两个回路最容易产生电磁干扰，因此必须在电源中其它印制线布线之前先布好这些交流回路，每个回路的三种主要的元件滤波电容、电源开关或整流器、电感或变压器应彼此相邻地进行放置，调整元件位置使它们之间的电流路径尽可能短。

电脑开关电源原理及电路图2.1、输入整流滤波电路只要有交流电AC220V输入，ATX开关电源，无论是否开启，其辅助电源就一直在工作，直接为开关电源控制电路提供工作电压。

图1中，交流电AC220V经过保险管FUSE、电源互感滤波器L0，经BD1—BD4整流、C5和C6滤波，输出300V左右直流脉动电压。

C1为尖峰吸收电容，防止交流电突变瞬间对电路造成不良影响。

TH1为负温度系数热敏电阻，起过流保护和防雷击的作用。

L0、R1和C2组成Π型滤波器，滤除市电电网中的高频干扰。

C3和C4为高频辐射吸收电容，防止交流电窜入后级直流电路造成高频辐射干扰。

2.2、高压尖峰吸收电路D18、R004和C01组成高压尖峰吸收电路。

当开关管Q03截止后，T3将产生一个很大的反极性尖峰电压，其峰值幅度超过Q03的C极电压很多倍，此尖峰电压的功率经D18储存于C01中，然后在电阻R004上消耗掉，从而降低了Q03的C极尖峰电压，使Q03免遭损坏。

2.3、辅助电源电路整流器输出的300V左右直流脉动电压，一路经T3开关变压器的初级①~②绕组送往辅助电源开关管Q03的c极，另一路经启动电阻R002给Q03的b极提供正向偏置电压和启动电流，使Q03开始导通。

Ic流经T3初级①~②绕组，使T3③~④反馈绕组产生感应电动势(上正下负)，通过正反馈支路C02、D8、R06送往Q03的b极，使Q03迅速饱和导通，Q03上的Ic电流增至最大，即电流变化率为零，此时D7导通，通过电阻R05送出一个比较电压至IC3（光电耦合器Q817）的③脚，同时T3次级绕组产生的感应电动势经D50整流滤波后一路经R01限流后送至IC3的①脚，另一路经R02送至IC4（精密稳压电路TL431），由于Q03饱和导通时次级绕组产生的感应电动势比较平滑、稳定，经IC4的K端输出至IC3的②脚电压变化率几乎为零，使IC3内发光二极管流过的电流几乎为零，此时光敏三极管截止，从而导致Q1截止。

开关电源PCB设计原则及走线技巧一、引言开关电源是一种电压转换电路，主要的工作内容是升压和降压，广泛应用于现代电子产品。

因为开关三极管总是工作在“开”和“关”的状态，所以叫开关电源。

开关电源实质就是一个振荡电路，这种转换电能的方式，不仅应用在电源电路，在其它的电路应用也很普遍，如液晶显示器的背光电路、日光灯等。

开关电源与变压器相比具有效率高、稳性好、体积小等优点，缺点是功率相对较小，而且会对电路产生高频干扰，变压器反馈式振荡电路，能产生有规律的脉冲电流或电压的电路叫振荡电路，变压器反馈式振荡电路就是能满足这种条件的电路。

开关电源分为，隔离与非隔离两种形式，在这里主要谈一谈隔离式开关电源的拓扑形式，在下文中，非特别说明，均指隔离电源。

隔离电源按照结构形式不同，可分为两大类：正激式和反激式。

反激式指在变压器原边导通时副边截止，变压器储能。

原边截止时，副边导通，能量释放到负载的工作状态，一般常规反激式电源单管多，双管的不常见。

正激式指在变压器原边导通同时副边感应出对应电压输出到负载，能量通过变压器直接传递。

按规格又可分为常规正激，包括单管正激，双管正激。

半桥、桥式电路都属于正激电路。

正激和反激电路各有其特点，在设计电路的过程中为达到最优性价比，可以灵活运用。

一般在小功率场合可选用反激式。

稍微大一些可采用单管正激电路，中等功率可采用双管正激电路或半桥电路，低电压时采用推挽电路，与半桥工作状态相同。

大功率输出，一般采用桥式电路，低压也可采用推挽电路。

反激式电源因其结构简单，省掉了一个和变压器体积大小差不多的电感，而在中小功率电源中得到广泛的应用。

在有些介绍中讲到反激式电源功率只能做到几十瓦，输出功率超过100瓦就没有优势，实现起来有难度。

本人认为一般情况下是这样的，但也不能一概而论，PI公司的TOP芯片就可做到300瓦，有文章介绍反激电源可做到上千瓦，但没见过实物。

输出功率大小与输出电压高低有关。

反激电源变压器漏感是一个非常关键的参数，由于反激电源需要变压器储存能量，要使变压器铁芯得到充分利用，一般都要在磁路中开气隙，其目的是改变铁芯磁滞回线的斜率，使变压器能够承受大的脉冲电流冲击，而不至于铁芯进入饱和非线形状态，磁路中气隙处于高磁阻状态，在磁路中产生漏磁远大于完全闭合磁路。

自制12v开关电源电路图2011-08-19 11:56:50 来源:互联网关键字：12v 开关电源+12V、0.5A单片开关稳压电源的电路如图所示。

其输出功率为6W。

当输入交流电压在110～260V范围内变化时，电压调整率Sv≤1％。

当负载电流大幅度变化时，负载调整率SI=5％～7％。

为简化电路，这里采用了基本反馈方式。

接通电源后，220V交流电首先经过桥式整流和C1滤波，得到约+300V的直流高压，再通过高频变压器的初级线圈N1，给WSl57提供所需的工作电压。

从次级线圈N2上输出的脉宽调制功率信号，经VD7、C4、L和C5进行高频整流滤波，获得+12V、0.5A的稳压输出。

反馈线圈N3上的电压则通过VD6、R2、C3整流滤波后，将控制电流加至控制端C上。

由VD5、R1，和C2构成的吸收回路，能有效抑制漏极上的反向峰值电压。

该电路的稳压原理分析如下：当由于某种原因致使Uo↓时，反馈线圈电压及控制端电流也随之降低，而芯片内部产生的误差电压Ur↑时，PWM比较器输出的脉冲占空比D↑，经过MOSFET和降压式输出电路使得Uo↑，最终能维持输出电压不变。

反之亦然。

如图所示12v开关电源电路图分享到：相关阅读开关电源的基本控制原理2011-08-19 开关电源的种类2011-08-19 由MC33374T/TV构成52W开关电源的电路2011-08-19 ERICSSON型开关电源电路图,原理图2011-08-19 采用电容传感器的全电子开关电源设计2011-08-18 降压开关电源设计过程中控制技术的选择2011-08-18 通信用高频开关电源技术的发展2011-08-18 静电感应晶闸管（SITH）在开关电源电路中的应用2011-08-18 基于VIPer22A的空调开关电源设计2011-08-18 超低功耗开关电源零空载功耗的设计实现2011-08-16(本文转自电子工程世界：/mndz/2011/0819/article_11573.html) 开关电源的基本控制原理2011-08-19 12:13:12 来源:互联网关键字：开关电源控制原理一．开关电源的控制结构：一般地，开关电源大致由输入电路、变换器、控制电路、输出电路四个主体组成。

开关电源PCB设计要点及实例分析开关电源PCB设计要点及实例分析开关电源PCB设计要点及实例分析为了适应电子产品飞快的更新换代节奏，产品设计工程师更倾向于选择在市场上很容易采购到的AC/DC适配器，并把多组直流电源直接安装在系统的线路板上。

由于开关电源产生的电磁干扰会影响到其电子产品的正常工作，正确的电源PCB设计就变得非常重要。

开关电源PCB设计与数字电路PCB设计完全不一样。

在数字电路排版中，许多数字芯片可以通过PCB软件来自动排列，且芯片之间的连接线可以通过PCB软件来自动连接。

用自动排版方式排出的开关电源肯定无法正常工作。

所以,设计人员需要对开关电源PCB设计基本规则和开关电源工作原理有一定的了解。

1 开关电源PCB设计基本要点1.1 电容高频滤波特性图1是电容器基本结构和高频等效模型。

图1 电容器结构和寄生等效串联电阻和电感电容的基本公式是C=Εrε0 （1）式（1）显示，减小电容器极板之间的距离（D）和增加极板的截面积（A）将增加电容器的电容量。

电容通常存在等效串联电阻（ESR）和等效串联电感（ESL）二个寄生参数。

图2是电容器在不同工作频率下的阻抗（ZC）。

图2 电容阻抗（ZC）曲线一个电容器的谐振频率（F0）可以从它自身电容量（C）和等效串联电感量（LESL）得到，即F0= （2）当一个电容器工作频率在F0以下时，其阻抗随频率的上升而减小，即ZC= （3）当电容器工作频率在F0以上时，其阻抗会随频率的上升而增加，即ZC=J2πfLESL（4）当电容器工作频率接近F0时，电容阻抗就等于它的等效串联电阻（RESR）。

电解电容器一般都有很大的电容量和很大的等效串联电感。

由于它的谐振频率很低，所以只能使用在低频滤波上。

钽电容器一般都有较大电容量和较小等效串联电感，因而它的谐振频率会高于电解电容器，并能使用在中高频滤波上。

瓷片电容器电容量和等效串联电感一般都很小，因而它的谐振频率远高于电解电容器和钽电容器，所以能使用在高频滤波和旁路电路上。

单管开关电源制作电路图详细说明一、基本要求和原理输入电压AC(90~265V)，频率(47~440Hz)；输出直流电压12V/24W，效率η=70%左右，线性调整<1%×输出电压，纹波及噪声≤2%×输出电压(mVP-P),具有过流、过压、短路自动恢复等保护功能。

基本原理如下图所示。

当VT导通时，变压器初级线圈Nl中电流线性增大，磁场增强，内部产生方向为上正下负的感生电动势￡，通过磁芯耦合到次级线圈N2中。

根据同名端原理，感应电压方向为上负下正，此时，与N2相连的二极管VD处于反偏压状态，VD截止，N2中无电流流过，即没有能量传递给负载RL。

当VT截止时，变压器初级线圈Nl中电流将消失。

由于电流不能突变，则Nl中感生电动势&epSILon;改变方向为上负下正．力图维持原态。

N1中磁场通过磁芯耦合到次级线圈N2中，根据同名端原理，感应电压方向为上正下负，与N2相连的二极管VD处于正偏压状态，VD导通，给输出电容C充电，同时负载RL 上也有电流IL流过。

所谓反激是指：VT导通→初级Nl储能→VD截止→次级N2中无电流；VT截止→初级N1泄能→VD导通→次级N2中有电流。

所谓单端是相对于桥式或推挽而言。

二、电路原理图和工作过程分析电路原理图如下图所示。

220V交流电一电源噪声滤波器(PNF)滤掉射频干扰一整流器(VD5~VD8)和Cl滤波获得约+300V直流电压。

该电压分成两路供电：一路经Nl绕组→VT1的D极，另一路经R15降压后向IC1提供+13V左右的启动电压一IC1内部振荡一IC1⑥脚输出开关脉冲→VT1处于开关状态→Nl绕组产生变化的磁场：一方面耦合到反馈绕组N3→整流滤波(VD2、C3)→输出+13V电压为IC1供电。

另一方面耦合到次级绕组N2→整流(VD4)→滤波(Cll-C14、12)→输出+12V电压。

C2、VD1、Rl和R12构成吸收回路，用于吸收尖峰电压，保护开关管，R5、R6、VD3和R7构成栅极无源加速关断驱动电路。

开关电源电路详解图一、开关电源的电路组成开关电源的主要电路是由输入电磁干扰滤波器(EMI）、整流滤波电路、功率变换电路、PWM控制器电路、输出整流滤波电路组成.辅助电路有输入过欠压保护电路、输出过欠压保护电路、输出过流保护电路、输出短路保护电路等。

开关电源的电路组成方框图如下:二、输入电路的原理及常见电路1、AC 输入整流滤波电路原理：①防雷电路：当有雷击，产生高压经电网导入电源时,由MOV1、MOV2、MOV3：F1、F2、F3、FDG1 组成的电路进行保护.当加在压敏电阻两端的电压超过其工作电压时,其阻值降低，使高压能量消耗在压敏电阻上，若电流过大，F1、F2、F3 会烧毁保护后级电路。

②输入滤波电路:C1、L1、C2、C3组成的双π型滤波网络主要是对输入电源的电磁噪声及杂波信号进行抑制，防止对电源干扰，同时也防止电源本身产生的高频杂波对电网干扰.当电源开启瞬间,要对C5充电,由于瞬间电流大，加RT1（热敏电阻）就能有效的防止浪涌电流.因瞬时能量全消耗在RT1电阻上，一定时间后温度升高后RT1阻值减小（RT1是负温系数元件），这时它消耗的能量非常小，后级电路可正常工作。

③整流滤波电路:交流电压经BRG1整流后，经C5滤波后得到较为纯净的直流电压。

若C5容量变小，输出的交流纹波将增大。

2、DC 输入滤波电路原理:①输入滤波电路:C1、L1、C2组成的双π型滤波网络主要是对输入电源的电磁噪声及杂波信号进行抑制，防止对电源干扰，同时也防止电源本身产生的高频杂波对电网干扰.C3、C4 为安规电容，L2、L3为差模电感。

② R1、R2、R3、Z1、C6、Q1、Z2、R4、R5、Q2、RT1、C7组成抗浪涌电路。

在起机的瞬间，由于C6的存在Q2不导通,电流经RT1构成回路.当C6上的电压充至Z1的稳压值时Q2导通.如果C8漏电或后级电路短路现象，在起机的瞬间电流在RT1上产生的压降增大，Q1导通使Q2没有栅极电压不导通,RT1将会在很短的时间烧毁,以保护后级电路。