LTC1155CN8#PBF;LTC1155CS8#PBF;LTC1155CN8;LTC1155CS8;LTC1155CS8#TR;中文规格书,Datasheet资料

1D UESCRIPTIOSFEATURE U A OPPLICATITYPICAL DIRORODI5V The LTC ®1485 is a low power differential bus/line trans-ceiver designed for multipoint data transmission standard RS485 applications with extended common-mode range (12V to –7V). It also meets the requirements of RS422.The CMOS with Schottky design offers significant power savings over its bipolar counterpart without sacrificing ruggedness against overload or ESD damage.The driver and receiver feature three-state outputs, with the driver outputs maintaining high impedance over the entire common-mode range. Excessive power dissipation caused by bus contention or faults is prevented by a thermal shutdown circuit which forces the driver outputs into a high impedance state. I/O pins are protected against multiple ESD strikes of over ±10kV.The receiver has a fail-safe feature which guarantees a high output state when the inputs are left open.Both AC and DC specifications are guaranteed from –40°C to 85°C and 4.75V to 5.25V supply voltage range.s Low Power RS485/RS422 Transceiver sLevel TranslatorU SA OPPLICATIs ESD Protection over ±10kV s Low Power: I CC = 1.8mA Typs28ns Typical Driver Propagation Delays with 4ns Skews Designed for RS485 or RS422 Applications s Single 5V Supplys–7V to 12V Bus Common-Mode Range Permits ±7V Ground Difference Between Devices on the Bus s Thermal Shutdown Protections Power-Up/Down Glitch-Free Driver OutputssDriver Maintains High Impedance in Three-State or with the Power OffsCombined Impedance of a Driver Output and Receiver Allows up to 32 Transceivers on the Bus s 60mV Typical Input HysteresissPin Compatible with the SN75176A, DS75176A, and SN75LBC1762A U G WA W U W A R BSOLUTEXI TI S W U U PACKAGE/ORDER I FOR ATIO(Note 1)Supply Voltage (V CC ).............................................. 12V Control Input Voltages................... –0.5V to V CC + 0.5V Control Input Currents........................ –50mA to 50mA Driver Input Voltages..................... –0.5V to V CC + 0.5V Driver Input Currents.......................... –25mA to 25mA Driver Output Voltages ......................................... ±14V Receiver Input Voltages........................................ ±14V Receiver Output Voltages .............. –0.5V to V CC + 0.5V Operating Temperature RangeLTC1485C............................................... 0°C to 70°C LTC1485I .......................................... –40°C to 85°C Storage Temperature Range................ –65°C to 150°C Lead Temperature (Soldering, 10 sec.)................ 300°CSYMBOL PARAMETERCONDITIONS MINTYP MAX UNITSV OD1Differential Driver Output Voltage (Unloaded)I O = 0q 5V V OD2Differential Driver Output Voltage (With Load)R = 50Ω, (RS422)q 2V R = 27Ω, (RS485) (Figure 1)q 1.55V ∆V OD Change in Magnitude of Driver DifferentialR = 27Ω or R = 50Ω (Figure 1)q 0.2V Output Voltage for Complementary Output States V OC Driver Common-Mode Output VoltageR = 27Ω or R = 50Ω (Figure 1)q 3V ∆|V OC |Change in Magnitude of Driver Common-Mode R = 27Ω or R = 50Ω (Figure 1)q 0.2V Output Voltage for Complementary Output States V INH Input High Voltage DI, DE, RE q 2.0V V INL Input Low Voltage DI, DE, RE q 0.8V I IN1Input CurrentDI, DE, REq ±2µA I IN2Input Current (A, B)V CC = 0V or 5.25V, V IN = 12V q 1.0mA V CC = 0V or 5.25V, V IN = –7V q –0.8mA V TH Differential Input Threshold Voltage for Receiver –7V ≤ V CM ≤ 12V q –0.20.2V ∆V TH Receiver Input Hysteresis V CM = 0Vq 60mV V OH Receiver Output High Voltage I O = –4mA, V ID = 0.2V q 3.5V V OL Receiver Output Low VoltageI O = 4mA, V ID = –0.2Vq 0.4V I OZR Three-State Output Current at Receiver V CC = Max 0.4V ≤ V O ≤ 2.4V q ±1µA I CCSupply CurrentNo Load; DI = GND or V CC Outputs Enabled q 1.8 2.3mA Outputs Disabled q 1.72.3mA R IN Receiver Input Resistance–7V ≤ V CM ≤ 12V q 12k ΩI OSD1Driver Short-Circuit Current, V OUT = High V O = –7V q 250mA I OSD2Driver Short-Circuit Current, V OUT = Low V O = 10 V q 250mA I OSRReceiver Short-Circuit Current0V ≤ V O ≤ V CCq785mAV CC = 5V (Notes 2, 3), unless otherwise noted.ELECTRICAL C C HARA TERISTICSC D Consult factory for Military grade parts.3SYMBOL PARAMETERCONDITIONSMIN TYP MAX UNITSt PLH Driver Input to Output R DIFF = 54Ω, C L1 = C L2 = 100pF q 103050ns(Figures 2, 5)t PHL Driver Input to Output R DIFF = 54Ω, C L1 = C L2 = 100pF q 103050ns (Figures 2, 5)t SKEW Driver Output to Output R DIFF = 54Ω, C L1 = C L2 = 100pF q 410ns (Figures 2, 5)t r , t fDriver Rise or Fall TimeR DIFF = 54Ω, C L1 = C L2 = 100pF q 51525ns (Figures 2, 5)t ZH Driver Enable to Output High C L = 100pF (Figures 4, 6) S2 Closed q 4070ns t ZL Driver Enable to Output Low C L = 100pF (Figures 4, 6) S1 Closed q 4070ns t LZ Driver Disable Time from Low C L = 15pF (Figures 4, 6) S1 Closed q 4070ns t HZ Driver Disable Time from High C L = 15pF (Figures 4, 6) S2 Closedq 4070ns tPLH Receiver Input to Output R DIFF = 54Ω, C L1 = C L2 = 100pF (Figures 2, 7)q 152550ns t PHL Receiver Input to Output R DIFF = 54Ω, C L1 = C L2 = 100pF (Figures 2, 7)q 203055ns t SKEW | t PLH – t PHL |R DIFF = 54Ω, C L1 = C L2 = 100pF (Figures 2, 7)q 515ns Differential Receiver Skewt ZL Receiver Enable to Output Low C L = 15pF (Figures 3, 8) S1 Closedq 3045ns t ZH Receiver Enable to Output High C L = 15pF (Figures 3, 8) S2 Closed q 3045ns t LZ Receiver Disable from Low C L = 15pF (Figures 3, 8) S1 Closed q 3045ns t HZ Receiver Disable from HighC L = 15pF (Figures 3, 8) S2 Closedq3045nsS UG C C HARA TERISTICSWITCHI V CC = 5V (Notes 2, 3), unless otherwise noted.The q denotes specifications which apply over the operating temperature range.Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed.Note 2: All currents into device pins are positive. All currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified.Note 3: All typicals are given for V CC = 5V and T A = 25°C.C C HARA TERISTICSU WA TYPICAL PERFOR CE Receiver Output High Voltage vs TemperatureReceiver Output Low Voltage vs Output CurrentReceiver Output High Voltage vs Output CurrentOUTPUT VOLTAGE (V)0O U T P U T C U R R E N T (m A )16 1.01485 G0180.51.524322.0412202836OUTPUT VOLTAGE (V)50O U T P U T C U R R E N T (m A )–81485 G02–443–12–162–2–6–10–14–18TEMPERATURE (°C)–50O U T P U T V O L T A G E (V )501485 G03–25125025751004C C HARA TERISTICSU WA TYPICAL PERFOR CE Driver Differential Output Voltage vs TemperatureTEMPERATURE (°C)–500O U T P U T V O L T A G E (V )0.10.30.40.5500.91485 G040.2–251250.60.70.802575100OUTPUT VOLTAGE (V)00O U T P U T C U R R E N T (m A )3221485 G05161348644TEMPERATURE (°C)–501.6D I F F E R E N T I A L V O L T A G E (V )2.0501485 G061.8–251252.22.402575100Driver Differential Output Voltage vs Output CurrentReceiver Output Low Voltage vs TemperatureDriver Output High Voltage vs Output CurrentTTL Input Threshold vs TemperatureDriver Output Low Voltage vs Output CurrentOUTPUT VOLTAGE (V)00O U T P U T C U R R E N T (m A )4021485 G07201360804OUTPUT VOLTAGE (V)00O U T P U T C U R R E N T (m A )–4821485 G08–2413–72–964TEMPERATURE (°C)–501.55I N P U T T H R E S H O L D V O L T A G E (V )1.59501485 G091.57–251251.611.6302575100Receiver | t PLH – t PHL | vs TemperatureSupply Current vs TemperatureDriver Skew vs TemperatureTEMPERATURE (°C)–501T I M E (n s )3501485 G102–251254502575100TEMPERATURE (°C)–501T I M E (n s )3501485 G112–251254502575100TEMPERATURE (°C)–501.4S U P P L Y C U R R E N T (m A )1.6501485 G121.5–251251.71.8025751005PI FU CTIO SUU U RO (Pin 1): Receiver Output. If the receiver output is enabled (RE low), then if A > B by 200mV, RO will be high.If A < B by 200mV, then RO will be low.RE (Pin 2): Receiver Output Enable. A low enables the receiver output, RO. A high input forces the receiver output into a high impedance state.DE (Pin 3): Driver Output Enable. A high on DE enables the driver outputs, A and B. A low input will force the driver outputs into a high impedance state.DI (Pin 4): Driver Input. If the driver outputs are enabled (DE high), then a low on DI forces the driver outputs A low and B high. A high on DI will force A high and B low.GND (Pin 5): Ground Connection.A (Pin 6): Driver Output/Receiver Input.B (Pin 7): Driver Output/Receiver Input.V CC (Pin 8): Positive Supply. 4.75V ≤ V CC ≤ 5.25V.TEST CIRCUITSFigure 3. Receiver Timing Test LoadV CCRECEIVER OUTPUTFigure 4. Driver Timing Test LoadV CCOUTPUT UNDER TESTAB1485 F01DI1485 F02RO Figure 1. Driver DC Test LoadFigure 2. Driver/Receiver Timing Test Circuit6TI W E WAVEFOR S G WITCHI SFigure 7. Receiver Propagation DelaysFigure 5. Driver Propagation DelaysFigure 6. Driver Enable and Disable Times–V V OH V V OLRO V A – V B1485 F070VVB AV O3V DI V A – V B–V 1485 F050VV DE V A,B A,B 0V5V7TI E WAVEFOR S G WITCHI SFigure 9. Typical Connection0VV 3V V RO RO 5V RE Figure 8. Receiver Enable and Disable TimesU S A OPPLICATI W UUI FOR ATIOTypical ApplicationA typical connection of the LTC1485 is shown in Figure 9.Two twisted pair wires connect up to 32 driver/receiver pairs for half duplex data transmission. There are no restrictions on where the chips are connected to the wires and it isn’t necessary to have the chips connected at the ends. However, the wires must be terminated only at theends with a resistor equal to their characteristic imped-ance, typically 120Ω. The input impedance of a receiver is typically 20k to GND, or 0.6 unit RS485 load, so in practice 50 to 60 transceivers can be connected to the same wires.The optional shields around the twisted pair help reduce unwanted noise, and are connected to GND at one end.RXDXRXDX8U S A OPPLICATI W U UI FOR ATIOThermal ShutdownThe LTC1485 has a thermal shutdown feature which protects the part from excessive power dissipation. If the outputs of the driver are accidentally shorted to a power supply or low impedance source, up to 250mA can flow through the part. The thermal shutdown circuit disables the driver outputs when the internal temperature reaches 150°C and turns them back on when the temperature cools to 130°C. If the outputs of two or more LTC1485drivers are shorted directly, the driver outputs can not supply enough current to activate the thermal shutdown.Thus, the thermal shutdown circuit will not prevent con-tention faults when two drivers are active on the bus at the same time.Cables and Data RateThe transmission line of choice for RS485 applications is a twisted pair. There are coaxial cables (twinaxial) made for this purpose that contain straight pairs, but these are less flexible, more bulky, and more costly than twisted pairs. Many cable manufacturers offer a broad range of 120Ω cables designed for RS485 applications.Losses in a transmission line are a complex combination of DC conductor loss, AC losses (skin effect), leakage, and AC losses in the dielectric. In good polyethylene cables such as the Belden 9841, the conductor losses and dielec-tric losses are of the same order of magnitude, leading to relatively low overall loss (Figure 10).When using low loss cables, Figure 11 can be used as a guideline for choosing the maximum line length for a given data rate. With lower quality PVC cables the dielectric loss factor can be 1000 times worse. PVC twisted pairs have terrible losses at high data rates (>100kbs), and greatly reduce the maximum cable length. At low data rates however, they are acceptable and much more economical.Cable TerminationThe proper termination of the cable is very important. If the cable is not terminated with its characteristic imped-ance, distorted waveforms will result. In severe cases,distorted (false) data and nulls will occur. A quick look at the output of the driver will tell how well the cable is terminated. It is best to look at a driver connected to theFREQUENCY (MHz)0.10.1L O S S P E R 100 F T (d B )1101101001485 F10DATA RATE (bps)10k10C A B L E L E N G T H (F T )1001k10k100k 1M 10M1485 F112.5M Figure 11. Cable Length vs Data RateFigure 10. Attenuation vs Frequency for Belden 9481end of the cable, since this eliminates the possibility of getting reflections from two directions. Simply look at the driver output while transmitting square wave data. If the cable is terminated properly, the waveform will look like a square wave (Figure 12).If the cable is loaded excessively (47Ω) the signal initially sees the surge impedance of the cable and jumps to an initial amplitude. The signal travels down the cable and is reflected back out of phase because of the mistermination.When the reflected signal returns to the driver, the ampli-tude will be lowered. The width of the pedestal is equal to twice the electrical length of the cable (about 1.5ns/foot).If the cable is lightly loaded (470Ω) the signal reflects in phase and increases the amplitude at the driver output. An input frequency of 30kHz is adequate for tests out to 4000feet of cable.9U S A OPPLICATIW U UI FOR ATIOFigure 12. Termination Effects1485 F12DXRXPROBE HERERt = 120ΩRt = 47ΩRt = 470ΩAC Cable TerminationCable termination resistors are necessary to prevent un-wanted reflections, but they consume power. The typical differential output voltage of the driver is 2V when the cable is terminated with two 120Ω resistors, causing 33mA of DC current to flow in the cable when no data is being sent. This DC current is about 10 times greater than the supply current of the LTC1485. One way to eliminate the unwanted current is by AC-coupling the termination resistors as shown in Figure 13.Figure 13. AC-Coupled TerminationThe coupling capacitor must allow high frequency energy to flow to the termination, but block DC and low frequen-cies. The dividing line between high and low frequency depends on the length of the cable. The coupling capacitor must pass frequencies above the point where the line represents an electrical one-tenth wavelength. The valueof the coupling capacitor should therefore be set at 16.3pF per foot of cable length for 120Ω cables. With the coupling capacitors in place, power is consumed only on the signal edges and not when the driver output is idling at a 1 or 0state. A 100nF capacitor is adequate for lines up to 400 feet in length. Be aware that the power savings start to de-crease once the data rate surpasses 1/(120Ω • C).Receiver Open-Circuit Fail-SafeSome data encoding schemes require that the output of the receiver maintains a known state (usually a logic 1)when the data is finished transmitting and all drivers on the line are forced into three-state. The receiver of the LTC1485has a fail-safe feature which guarantees the output to be in a logic 1 state when the receiver inputs are left floating (open-circuit).If the receiver output must be forced to a known state, the circuits of Figure 14 can be used.Figure 14. Forcing “0” When All Drivers Are OffRXRXRXRX10U S A OPPLICATI WU UI FOR ATIOThe termination resistors are used to generate a DC bias which forces the receiver output to a known state, in this case a logic 0. The first method consumes about 208mW and the second about 8mW. The lowest power solution is to use an AC termination with a pull-up resistor. Simply swap the receiver inputs for data protocols ending in logic 1.Fault ProtectionAll of LTC’s RS485 products are protected against ESD transients up to 2kV using the human body model (100pF, 1.5k Ω). However, some applications need more protection. The best protection method is to connect a bidirectional TransZorb ® from each line side pin to ground (Figure 15).A TransZorb is a silicon transient voltage suppressor that has exceptional surge handling capabilities: fast responsetime and low series resistance. They are available from General Semiconductor Industries and come in a variety of breakdown voltages and prices. Be sure to pick a breakdown voltage higher than the common-mode volt-age required for your application (typically 12V). Also,don’t forget to check how much the added parasitic capacitance will load down the bus.Figure 15. ESD Protection with TransZorbsU SA OPPLICATI TYPICAL TransZorb is a registered trademark of General Instruments, GSIRS232 ReceiverRS232INRXRS232 to RS485 Level Translator with HysteresisRS232IN11LTC1485PACKAGE DESCRIPTIOUDimensions in inches (millimeters) unless otherwise noted.N8 Package 8-Lead Plastic DIPN8 0694(6.477 ± 0.381)–0.3818.255*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm).Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of circuits as described herein will not infringe on existing patent rights.12LTC1485© PACKAGE DESCRIPTIOUDimensions in inches (millimeters) unless otherwise noted.S8 Package 8-Lead Plastic SOICSO8 02940.053 – 0.069 BSC*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006 INCH (0.15mm).RELATED PARTSPART NUMBER DESCRIPTION COMMENTSLTC486Quad RS485 Driver Fits 75172 Pinout, Only 110µA I Q LTC488Quad RS485 Receiver Fits 75173 Pinout, Only 7mA I Q LTC490Full Duplex RS485 TransceiverFits 75179 Pinout, Only 300µA I Q LTC1481Ultra-Low Power Half Duplex RS485 TransceiverFits 75176 Pinout, 80µA I QLinear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7487(408) 432-1900 qFAX : (408) 434-0507 qTELEX : 499-3977。

LTC4054丝印LTH7锂电充电管理IC————————————————————————————————作者：————————————————————————————————日期：2V1.31）典型应用电路注：R1 电阻建议不要省列与 C 1 构成 R C 滤波防止过充电压。

如果 R 1 电阻不接 C 1 使用 10UF 以上电容。

典型运用电路仅供参考，其它以实际运用为准。

概述HX4054A 是一款单节锂离子电池恒流/恒压线性充电器，简单的外部应用电路非常适合便携式设备应用，适合 USB 电源和适配器电源工作，内部采用防倒充电路，不需要外部隔离二极管。

热反馈可对充电电流进行自动调节，以便在大功率操作或高环境温度条件下对芯片温度加以限制。

HX4054A 充电截止电压为 4.2V, 充电电流可通过外部电阻 进行设置。

当充电电流降至设定值的 1/10 时，HX4054A 将自动结束充电过程。

当输入电压被移掉后，HX4054A 自动进入低电流待机状态，将待机电流降至 1uA 以下。

HX4054A 在有输入电源时也可置于停机模式，从而将工作电流降至 30uA 。

兼容TP4054 XT4054 LN2054 SE9016 ME4054 XT4052 EUP8054 AS3020 XZ3085A BL8572 HX6001 QX4054 HYM4054 SUN4054 FK5406 AP5056 SLM4054 LP4054 APL3202 OPC8020 OHL5100 LM2054 UCT3054 TQ7051 特点∙ 锂电池正负极反接保护（没充电的情况下 ∙ 最大充电电流：500mA∙ 无需 MOSFET 、检测电阻器和隔离二极管 ∙ 智能热调节功能可实现充电速率最大化 ∙ 智能再充电功能 ∙ 预充电压：4.2V±1% ∙ 3C/10 充电终止 ∙ 待机电流 30uA∙ BAT 超低自耗电 1uA ∙ 2.9V 涓流充电阈值∙ 单独的充电、结束指示灯控制信号 ∙封装形式：SOT23-5应用∙ 手机、PDA 、MP3/MP4 ∙ 蓝牙耳机、GPS ∙ 充电座∙数码相机、Mini 音响等便携式设备V1.32管脚定购信息SOT23-5L封装 定购型号 包装形式产品正印SOT23-5LHX4054A极限参数（注 1）符号 参数额定值 单位 VCC 输入电源电压 -0.3~7 V PROG PROG 脚电压 -0.3~0.3 V BAT BAT 脚电压 -0.3~7 V CHRG CHRG 脚电压-0.3~7 V T BAT_SHTBAT 脚短路持续时间 连续 - I BAT BAT 脚电流 600 mA I PROG PROG 脚电流 600 uA T OP 工作环境温度 -40~85 ℃ T STG储存温度 -65~125 ℃ ESDHBM2000 V MM200V注 1：最大极限值是指超出该工作范围芯片可能会损坏。

Feb 28, 2011IR1155SPROGRAMMABLE FREQUENCY, ONE CYCLE CONTROL PFC ICFeaturesDescription Package• PFC IC with IR proprietary “One Cycle Control” • Continuous conduction mode boost type PFC • Programmable switching frequency (48k-200kHz) • Average current mode control • Output overvoltage protection • Open loop protection • Cycle by cycle peak current limit • VCC under voltage lockout• Programmable soft start • Micropower startup • User initiated micropower “Sleep Mode”• OVP/EN pin internal filtering for higher noise immunity • 1.5A peak gate drive• Latch immunity and ESD protection The μPFC IR1155 power factor correction IC, based on IR proprietary "OneCycle Control" (OCC) technique, provides for high PF, low THD and excellent DC Bus regulation while enabling drastic reduction in component count, PCB area and design time as compared to traditional solutions. The IC is designed to operate in continuous conduction mode Boost PFC converters with average current mode control over 85-264VAC input line voltage range. Switching frequency can be programmed to anywhere between 48kHz to 200kHz based on the specific application requirement. In addition, IR1155 offers several advanced system-enabling and protective features such as dedicated pin for over voltage protection, cycle by cycle peak current limitation, open loop protection, V CCUVLO, soft-start and micropower startup/sleep-mode with IC current consumption less than 200µA. The sleep mode, invoked by pulling the OVP/EN pin low, enables compliance with standby power requirements mandated by regulations such as Energy Star, Green Power, Blue Angel etc.Qualification InformationIndustrialQualification Level Comments: This family of ICs has passed JEDEC’s Industrialqualification. IR’s Consumer qualification level is granted byextension of the higher Industrial level.Moisture Sensitivity LevelMSL2 260°C(per IPC/JEDEC J-STD-020)Machine ModelClass A(per JEDEC standard JESD22-A115)ESDHuman Body ModelClass 1B (passes 500V)(per EIA/JEDEC standard EIA/JESD22-A114)IC Latch-Up Test Class I, Level A (per JESD78)RoHS Compliant YesAbsolute Maximum RatingsParameter Symbol Min. Max. Units RemarksVCC Voltage V CC -0.3 20 VFREQ Voltage V FREQ -0.3 6.5 VISNS Voltage V ISNS -10 0.3 VVFB, OVP Voltage V FB, V OVP -0.3 6.5 VCOMP Voltage V COMP -0.3 6.5 VGATE Voltage V GATE -0.3 18 VISNS Current I ISNS -2 2 mAJunction Temperature T J -40 150 °CStorage Temperature T S -55 150 °CThermal ResistanceJunction to AmbientRθJA128 °C/WPackage Power Dissipation P D976 mWT AMB = 25°CRecommended Operating ConditionsRecommended operating conditions for reliable operation with marginParameter SymbolMin.Typ.Max.UnitsRemarks Supply Voltage V CC12 19 VJunction Temperature T J -25 125 °CSwitching Frequency F SW 48 200 kHzElectrical CharacteristicsThe electrical characteristics involve the spread of values guaranteed within the specified supply voltage and junction temperature range T J from –25 °C to 125°C. Typical values represent the median values, which are related to 25°C. If not otherwise stated, a supply voltage of V CC =15V is assumed for test condition . Supply SectionParameter Symbol Min. Typ. Max. Units Remarks VCC Turn On ThresholdV CC ON 10.65 11.3 11.95 V VCC Turn OffThreshold (Under Voltage Lock Out) V CC UVLO 9.2 9.8 10.4 V VCC Turn On/Off Hysteresis V CC HYST 1.5VOperating CurrentI CC 10 13 mA C load =1nF, F SW =181kHz6 8 mAStandby Mode (Inactive Gate, Inactive Internal Oscillator)V FB <V OLPSee State Transition Diagram Startup CurrentI CCSTART175 uA V CC =V CC ON - 0.1VSleep CurrentI SLEEP 125 200 uASleep Mode (Inactive Gate,Inactive Oscillator)- V OVP <V SLEEP,OFFSee State Transition Diagram Sleep ModeThreshold (Enable)V SLEEP,ON0.80 0.90 1.00 VIC Enable threshold,Bias on OVP pinSleep ModeThreshold (Disable)V SLEEP,OFF 0.53 0.60 0.67VIC Disable threshold, Bias on OVP pinOscillator SectionParameter Symbol Min. Typ. Max. Units Remarks Switching Frequency F SW48 200 kHz 200khz:C =430pF approx.48kHz: C=2nF approx.Oscillator Charge Current I OSC(CHG) 200 µA Oscillator Discharge Current I OSC(DCHG) 6.6 mA Oscillator Peak V OSC PK 4 V Oscillator Valley V OSC VAL 2 V 5 % C =2nF, T A = 25°C Initial Accuracy F SW ACC 8 % C =500pF, T A = 25°C Voltage Stability V STAB0.21%14V < V CC < 19VTemperature Stability T STAB 2 % -25°C ≤ T J ≤ 125°CTotal Variation F VT10 % Line & TemperatureMaximum Duty Cycle D MAX 94 99 %Minimum Duty CycleD MIN 0 % Pulse SkippingProtection SectionParameter Symbol Min. Typ. Max. Units RemarksOpen Loop Protection(OLP) V FB Threshold V OLP 17 19 21 % V REF Bias on VFB pinOutput Over Voltage Protection (OVP) V OVP 104.5 106.5 108.5 % V REF Bias on OVP/EN pin Output Over Voltage Protection (OVP) Reset V OVP(RST) 100.2 102.2 104.2 % V REF Bias on OVP/EN pin Peak Current LimitProtection (IPK LMT) I SNS Voltage Threshold V ISNS-0.85-0.77-0.69VBias on ISNS pinOVP Input Bias Current I OVP(Bias) -0.2 µAInternal Voltage Reference SectionVoltage Error Amplifier SectionParameter Symbol Min. Typ. Max. Units Remarks Transconductance g m 35 50 65 µS 30 44 58 T AMB = 25°C Source CurrentI OVEA(SRC)20 44 90µA -25°C ≤T AMB ≤ 125°C -57 -43 -30 T AMB = 25°C Sink Current I OVEA(SNK)-90 -43 -20µA -25°C ≤T AMB ≤ 125°CSoft Start Delay Time t SS35 msec R GAIN = 1k Ω, C ZERO = 0.33uF,C POLE = 0.01uF V COMP Voltage (Fault) V COMP FLT 1 1.4 V@ 100µA steady statecurrentEffective V COMP Voltage V COMP EFF 4.6 4.9 5.2 V VFB Input Bias Current I IB(Bias)-0.2 µA V FB =4.9VOutput Low Voltage V OL 0.25 V Output High Voltage V OH 5 5.4 V V COMP Start Voltage V COMP START240 340 460 mVParameter Symbol Min. Typ. Max. Units Remarks Reference Voltage V REF 4.9 5 5.1 V T A = 25°C Line Regulation R REG1020mV14 V < V CC < 19V Temp Stability T STAB 0.4 % -25°C ≤ T AMB ≤ 125°C Total VariationΔV TOT4.855.1VLine & TemperatureCurrent Amplifier SectionUnitsRemarksMax.Parameter SymbolMin.Typ.DC Gain g DC 3.1 V/VCorner Frequency f C 5 kHz - Average current mode, Note 1Note1Input Offset Voltage V IO 4 16 mVI SNS Bias Current I ISNS(Bias) -57 -13 µABlanking Time T BLANK220 370 520 nsGate Driver SectionUnitsMax.Remarks Parameter SymbolMin.Typ.Gate Low Voltage V GLO 0.8 VI GATE=200mAclamp12 13 14 VGateInternalGate High Voltage V GTHV CC = 11.5V10 VRise Time t r20 nsC LOAD = 1nFFall Time t f20 nsC LOAD = 1nFC LOAD = 10nF, Note 1Output Peak Current I OPK 1.5 AGate Voltage @ Fault V G fault 0.08I GATE = 20mAVNote 1 – Guaranteed by design, but Not tested in productionLead Assignments & DefinitionsBlock DiagramVFBCOMPOVPNote: Soft-Start & Normal modes are essentially the same (differentiation above is for purpose of clarity only)VCC Undervoltage LockoutV o l t a g e o n V C C p i nTiming DiagramsOutput ProtectionIR1155 General DescriptionThe μPFC IR1155 IC is intended for power factor correction in continuous conduction mode Boost PFC converters operating at fixed switching frequency with average current mode control. The switching frequency is programmable any where from 48kHz to 200khz. The IC operates according to IR's proprietary "One Cycle Control" (OCC) PFC algorithm, which is based on the re-settable integrator principle. When operating a AC-DC Boost converter, power factor correction can be achieved using this algorithm without AC input line sensing.Theory of OperationThe OCC algorithm works using two loops - a slow outer voltage loop and a fast inner current loop. The outer voltage loop monitors the VFB pin to maintain regulation of boost converter output voltage and generates a constant error signal. The inner current loop exploits the embedded input voltage information in the boost converter duty cycle to generate a current reference for power factor correction. The combination of the two control elements forces the amplitude and shape of the input current to be proportional to and in phase with the input voltage while maintaining output voltage regulation. This is true so long as operation in continuous conduction mode is maintained. Average current mode operation is envisaged by filtering the switching frequency ripple from the current sense signal in the current loop using an on-chip filter.The IC determines the boost converter instantaneous duty cycle using the voltage feedback loop error signal V m and the current sense signal V ISNS, which is the voltage at the current sense pin of the IC. The PWM ramp is generated using a resettable integrator that tracks V m every switching cycle. The current sense signal is amplified by the current amplifier averaged to remove the ripple component and fed into the summing node where it is subtracted from the voltage error signal, V m. The resulting voltage (V m - g DC.V ISNS) is compared with the PWM ramp signal by the PWM comparator to determine the gate drive duty cycle. The instantaneous duty cycle is mathematically given by:D = (V m - g DC.V ISNS) /V mA more detailed description of IR1155 theory of operation is available in Application Note. Feature setThe IR1155 offers a host of advanced features and system protections functions, which makes it the most feature-intensive IC in PFC market in a compact 8-pin package.User-Programmable Switching FrequencyIR1155 IC operates under fixed switching frequency. The switching frequency is user-programmed by inserting a capacitor between FREQ & COM pins. A pair of current sources inside the IC source/sink current in/out of the capacitor alternately thus generating a constant-slope saw-tooth ramp signal between a pre-determined peak & valley voltage pair (typically between 2V to 4V). This saw-tooth signal is the oscillator signal of the IC. The frequency of operation of the IC can be programmed anywhere between 48kHz and 200kHz by suitably sizing the capacitor. The oscillator signal is a key control signal and is used by the resettable integrator block of the IC to generate the internal PWM ramp every switching cycle.IC Supply Circuit & Low start-up currentThe IR1155 UVLO circuit maintains the IC in UVLO mode during start-up if VCC pin voltage is less than the VCC turn-on threshold, V CC,ON and current consumption is less than I CC,START. Should VCC pin voltage should drop below UVLO threshold V CC, UVLO anytime after start-up, the IC is pushed back into UVLO mode (VCOMP pin is discharged) and VCC pin has to exceed V CC,ON again to re-start operation. It is noted that there is no internal clamping of the VCC pin.User initiated Micropower Sleep modeThe IC can be actively pushed into a micropower sleep mode where current consumption is less than I CC,SLEEP by pulling OVP/EN pin below the Sleep threshold, V SLEEP(OFF), even while VCC is above V CC,ON. This allows the user to disable PFC during application stand-by situations in order to meet regulations (Blue Angel, Green Power etc). When OVP/EN pin is pulled low, the VCOMP pin of the IC is actively discharged as the IC is relegated to the Sleep mode. This enables the IC to go through soft-start when the IC is re-enabled. Since V SLEEP(OFF) is less than 1V, even logic level signals can be employed to disable and enable the IC.IR1155 General DescriptionProgrammable Soft StartThe soft start process controls the rate of rise of the voltage feedback loop error signal thus providing a linear control on RMS input current that the PFC converter will admit. The soft start time is essentially controlled by voltage error amplifier compensation components selected andis therefore user programmable to some degree based on desired loop crossover frequency.Gate Drive CapabilityThe gate drive output stage of the IC is a totem pole driver with 1.5A peak current drive capability. The gate drive is internally clamped at 13V (Typ). Gate drive buffer circuits can be easily driven with the GATE pin of the IC to suit any system power level.System Protection FeaturesIR1155 protection features include DC bus Overvoltage protection (OVP) via a dedicated pin, Open-loop protection (OLP), Cycle-by-cycle peak current limit (IPK LIMIT), Soft-current limit and VCC under voltage lock-out (UVLO).- Overvoltage voltage protection (OVP) feature in IR1155 is achieved using a dedicated pin called the OVP/EN pin. The input of OVP comparator is connected the OVP pin. When the OVP pin voltage exceeds V OVP, an overvoltage situation is detected and the gate drive is immediately terminated. The gate drive is re-enabled only after OVP pin voltage drops below V OVP(RST). The use of a dedicated OVP/EN pin ensures that the system is protected from catastrophic overvoltages, even if the feed-back loop (connected to the VFB pin) encounters any failure. This ensures the best possible system overvoltage protection against extremes of situations.- Open Loop Protection (OLP) is activated whenever the VFB pin voltage falls below V OLP threshold. The gate drive is then immediately disabled, VCOMP is actively discharged and the IC is pushed into Stand-by mode. The IC will re-start (with soft-start) once the VFB pin voltage exceeds V OLP again. There is no voltage hysteresis associated with this feature. During start-up the IC is held in Stand-by until this pin exceeds V OLP. - Soft-current limit is an output voltage fold-back type protection feature that is encountered when the RMS current in the PFC converter exceeds a certain magnitude that causes the internal error signal of the voltage feedback, V m to saturate at its highest value. Amplitude of V m signal is directly proportional to the RMS input current admitted into the PFC converter. In effect, once V m saturates, the maximum RMS current admissible into the PFC converter has been encountered. Any attempt to increase the RMS current beyond this limit causes the IC to limit the duty cycle delivered to the PFC converter, which then has the effect of causing the DC bus voltage to droop i.e. output voltage folds-back. The current level at which V m saturates is closely related to the value of the current sense resistor selected for the PFC converter. In one way, this feature can be perceived to offer an overpower limitation of sorts at the conditions at which current sense design is performed (minimum VAC & maximum output power). For details, please refer to IR1155 Application Note.- Cycle-by-cycle peak current limit protection instantaneously turns-off the gate output whenever the ISNS pin voltage exceeds V ISNS(PK) threshold in magnitude. The gate drive output is re-enabled only after the magnitude of the ISNS pin voltage drops below the V ISNS(PK) threshold. It is clarified that even though the IC operates based on average current mode control, since the averaging circuit is decoupled from the peak current limit comparator input, the IC is still able to provide instantaneous response to a system overcurrent condition. This protection feature incorporates a leading edge blanking circuit following the comparator to improve noise immunity.- VCC Under Voltage Lockout protection maintains the IC in a low current consumption, UVLO mode during start-up if VCC pin voltage is less than the VCC turn-on threshold, V CC,ON. In UVLO mode the current consumption is less than I CC,START which is typically about 200uA. Should VCC pin voltage should drop below UVLO threshold V CC, UVLO anytime after start-up, the IC is pushed back into UVLO mode (VCOMP pin is discharged) and VCC pin has to exceed V CC,ON again to re-start operation.IR1155 Pin DescriptionPin COM: This is ground potential pin of the IC. All internal devices are referenced to this point. A star-connection point, very close to this pin, is recommended in PCB lay-out in order to reference the return traces of the various control loops to the COM potential of the IC.Pin COMP: External circuitry from this pin to ground compensates the system voltage loop and programs the soft start time. The COMP pin is essentially the output of the voltage error amplifier. VCOMP is actively discharged using an internal switch & resistance inside the IC whenever the IC is pushed into Stand-by mode (Open Loop Condition) or UVLO/Sleep mode. The IC is designed not to start-up (from UVLO, Sleep or Stand-by modes) when there is a pre-bias on VCOMP pin that is greater than V COMP,START. The VCOMP-COM loop represents a very important control loop to the IC and hence a dedicated PCB trace loop is recommended for layout (star-connection to GND potential) for noise free, stable operation.Pin ISNS: ISNS pin is the inverting input to the current sense amplifier of the IC. The voltage at this pin is the negative voltage drop sensed across the system current sense resistor and thus represents the inductor current sense signal to the IC for determining gate drive duty cycle. ISNS pin is also the inverting input to the cycle-by-cycle peak current limit comparator. Whenever this pin voltage exceeds V ISNS(PK) threshold in magnitude, the gate drive is instantaneously disabled. Any external filtering of the ISNS pin must be performed carefully in order to ensure that the integrity of the current sense signal is maintained for cycle-by-cycle protection.Pin FREQ: This is the user-programmable frequency pin. The switching frequency is programmed by inserting a capacitor between FREQ & COM pins. A pair of current sources inside the IC source/sink current in/out of the capacitor alternately thus generating a constant-slope saw-tooth ramp signal between a pre-determined peak & valley voltage pair (typically between 2V to 4V). This saw-tooth signal is the oscillator signal of the IC. The frequency of operation of the IC can be programmed anywhere between 48kHz and 200kHz by suitably sizing the capacitor. The FREQ-COM loop represents yet another very important control loop to the IC and hence a dedicated PCB trace loop is recommended in lay-out (star-connection to GND potential) for noise free, stable operation.Pin OVP/EN: The OVP/EN pin is connected to the input of the overvoltage comparator and is used to detect output overvoltage situations. The output voltage information is communicated to the OVP pin using a resistive divider. This pin also serves the second purpose of an ENABLE pin. The OVP/EN pin can be used to activate the IC into “micropower sleep” mode by pulling the voltage on this pin below the V SLEEP threshold.Pin VFB: The converter output voltage is sensed via a resistive divider and fed into this pin. VFB pin is the inverting input of the output voltage error amplifier. The non-inverting input of this amplifier is connected to an internal 5V reference. The impedance of the divider string must be low enough that it does not introduce substantial error due to the input bias currents of the amplifier, yet high enough to minimize power dissipation. Typical value of external divider impedance will be 1MΩ. VFB pin is also the inverting input to the Open Loop comparator. The IC is held in Stand-by Mode whenever VFB pin voltage is below V OLP threshold. Pin VCC: This is the supply voltage pin of the IC and sense node for the under-voltage lock out circuit. It is possible to turn off the IC by pulling this pin below the minimum turn off threshold voltage, V CC,UVLO without damage to the IC. This pin is not internally clamped.Pin GATE: This is the gate drive output of the IC. This drive voltage is internally clamped to 13V(Typ) and provides a drive current of ±1.5A peak with matched rise and fall times.IR1155S IR1155 Modes of operation (refer to States & Transitions Diagram)UVLO/Sleep Mode: The IC is in the UVLO/Sleep mode when either the VCC pin voltage is below V CC,UVLO and/or the OVP/EN pin voltage is below V SLEEP. The UVLO/Sleep mode is accessible from any other state of operation. This mode can be actively invoked by pulling the OVP/EN pin below the Sleep threshold V SLEEP even if VCC pin voltage is above V CC,ON. In the UVLO/Sleep state, the gate drive circuit is inactive, most of the internal circuitry is unbiased and the IC draws a quiescent current of I SLEEP which is typically 200uA or less. Also, the internal logic of the IC ensures that whenever the UVLO/Sleep mode is actively invoked, the COMP pin is actively discharged below V COMP,START prior to entering the sleep mode, in order to facilitate soft-start upon resumption of operation.Stand-by Mode: The IC is placed in Stand-by mode whenever an Open-loop situation is detected. An open-loop situation is sensed anytime VFB pin voltage is less than V OLP. All internal circuitry is biased in the Stand-by Mode, but the gate is inactive and the IC draws a few mA of current. This state is accessible from any other state of operation of the IC. COMP pin is actively discharged to below V COMP,START whenever this state is entered from normal operation in order to facilitate soft-start upon resumption of operation. Soft Start Mode: During system start-up, the soft-start mode is activated once the VCC voltage has exceeded V CC,ON, the VFB pin voltage has exceeded V OLP and OVP pin voltage has exceeded V SLEEP(ON). The soft start time is the time required for the VCOMP voltage to charge through its entire dynamic range i.e. through V COMP,EFF. As a result, the soft-start time is dependent upon the component values selected for compensation of the voltage loop on the COMP pin. As VCOMP voltage raises gradually, the IC allows a higher and higher RMS current into the PFC converter. This controlled increase of the input current amplitude contributes to reducing system component stress during start-up. It is clarified that, during soft-start, the IC is capable of full duty cycle modulation (from 0% to MAX DUTY), based on the instantaneous ISNS signal from system current sensing. .For all practical purposes, the Soft-start mode of the IC is the same as the Normal mode (only difference being that the DC bus voltage is approaching the regulation point). All protection functions of the IC are active during soft-start mode.Normal Mode: The IC enters the normal operating mode seamlessly following conclusion of soft-start. At this point the DC bus is well regulated and all protection functions of the IC are active. If, from the normal mode, the IC is pushed into either a Stand-by mode or Sleep mode then COMP pin is actively discharged below V COMP,START and system will go through soft-start upon resumption of operation.OVP Mode: The IC enters OVP fault mode whenever an overvoltage condition is detected. A system overvoltage condition is recognized when OVP/EN pin voltage exceeds V OVP threshold. When this happens the IC immediately disables the gate drive. The gate drive is re-enabled only when OVP/EN pin voltage is less than V OVP(RST) threshold. This state is accessible from both the soft start and normal modes of operation.IPK LIMIT Mode: The IC enters IPK LIMIT fault mode whenever the magnitude of ISNS pin voltage exceeds the V ISNS(PK) threshold triggering cycle-by-cycle peak over current protection. When this happens, the IC immediately disables the gate drive. Gate drive is re-enabled when magnitude of ISNS pin voltage drops below V ISNS(PK) threshold. This state is accessible from both the soft start and normal modes of operation.0.010.11107.0 V9.0 V 11.0 V 13.0 V 15.0 V 17.0 VI S U P P L Y (m A )Supply voltageFigure 1: Supply Current vs.Supply Voltage9.0 V9.5 V10.0 V 10.5 V 11.0 V 11.5 V12.0 V -50 °C0 °C50 °C 100 °C 150 °CV C C U V L O T h r e s h o l d sT emperatureVCC UV+VCC UV-Figure 2: Undervoltage Lockout vs.Temperature8.78.88.99.09.19.29.39.49.59.69.7-50 °C0 °C50 °C 100 °C 150 °CI C C S u p p l y C u r r e n t (m A )T emperatureIcc @ C LOAD =1nFFigure 3: Icc Current vs. Temperature(@181kHz frequency)50.070.090.0110.0130.0150.0170.0-50 °C0 °C 50 °C 100 °C 150 °CC u r r e n t (u A )T emperatureI CCSTART and I SLEEPISLEEPICCSTARTFigure 4: Startup Current and SleepCurrent vs. Temperature20.040.060.080.0100.0120.0140.0160.0180.0200.0-50 °C0 °C 50 °C 100 °C 150 °CS w i t c h i n g F r e q u e n c y (K H z )T emperatureCT=500pFCT=2nFFigure 5: Switching Frequency vs.Temperature4.954.974.995.015.035.05-50 °C0 °C 50 °C 100 °C 150 °CR e f e r e n c e V o l t a g e (V )T emperatureFigure 6: Reference Voltage vs.Temperature40.042.044.046.048.050.052.054.0-50 °C0 °C 50 °C 100 °C 150 °CE A T r a n s c o n d u c t a n c e g m (u S )T emperatureFigure 7: Voltage Error Amplifier Transconductance vs. Temperature10.020.030.040.050.060.070.080.0-50 °C0 °C 50 °C 100 °C 150 °CE r r o r A m p l i f i e r S o u r c e /S i n k C u r r e n t (u A )T emperatureSource |Sink|Figure 8: Voltage Error Amplifier Source& Sink Current vs. Temperature3.003.053.103.153.203.253.30-50 °C0 °C 50 °C 100 °C 150 °C C u r r e n t S e n s e A m p l i f i e r D C G a i n g D C (V /V )T emperatureFigure 9: Current Amplifier DC Gain vs.Temperature-1.0-0.9-0.8-0.7-0.6-0.5-50 °C0 °C 50 °C 100 °C 150 °CP e a k C u r r e n t L i m i t T h r e s h o l d (V )T emperatureFigure 10: Peak Current Limit ThresholdV ISNS(PK) vs. Temperature1.001.021.041.061.081.10-50 °C0 °C 50 °C 100 °C 150 °CO V P T h r e s h o l d (%V r e f )T emperatureVOVPVOVP(RST)Figure 11: Over Voltage ProtectionThresholds vs. Temperature40.0060.0080.00100.00120.00140.00160.00180.00200.004006509001150140016501900F r e q u e n c y (K H z )CT (pF)Frequency vs. CTFigure 12: Oscillator Frequency vs.Programming CapacitorPackage Details: SOIC8NTape and Reel Details: SOIC8NC LOADED TAPE FEED DIRECTIONPart Marking InformationIR1155S 21 © 2011 International Rectifier Ordering InformationStandard Pack Base Part Number Package TypeForm Quantity Complete Part Number Tube/Bulk 95 IR1155SPBF IR1155SSOIC8N Tape and Reel 2500 IR1155STRPBFThe information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any patent or patent rights of International Rectifier. The specifications mentioned in this document are subject tochange without notice. This document supersedes and replaces all information previously supplied.For technical support, please contact IR’s Technical Assistance Center/technical-info/WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245Tel: (310) 252-7105。