LTM9009CY-14#PBF;LTM9009IY-14#PBF;LTM9010CY-14#PBF;LTM9010IY-14#PBF;中文规格书,Datasheet资料
- 格式:pdf
- 大小:147.03 KB
- 文档页数:11
19009101114faTypical applicaTionFeaTuresapplicaTionsDescripTion80Msps Low Power Octal ADCsLTM9011-14, 125Msps,2-Tone FFT, f IN = 70MHz and 75MHzThe L TM ®9011-14/LTM9010-14/LTM9009-14 are 8-chan-nel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. AC performance includes 73.1dB SNR and 88dB spurious free dynamic range (SFDR). Low power consumption per channel reduces heat in high channel count applications. Integrated bypass capacitance and flow-through pinout reduces overall board space requirements.DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSB RMS .The digital outputs are serial LVDS to minimize the num-ber of data lines. Each channel outputs two bits at a time (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode).The ENC + and ENC – inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer al-lows high performance at full speed for a wide range of clock duty cycles.n8-Channel Simultaneous Sampling ADC n 73.1dB SNR n 88dB SFDRn Low Power: 140mW/113mW/94mW per Channel n Single 1.8V Supplyn Serial LVDS Outputs: 1 or 2 Bits per Channel n Selectable Input Ranges: 1V P-P to 2V P-P n 800MHz Full Power Bandwidth S/H n Shutdown and Nap Modesn Serial SPI Port for ConfigurationnInternal Bypass Capacitance, No External Componentsn 140-Pin (11.25mm × 9mm) BGA PackagenCommunications n Cellular Base Stations n Software Defined Radios n Portable Medical Imaging n Multichannel Data Acquisition nNondestructive TestingL , L T, L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.FREQUENCY (MHz)0–100–110–120–70–60–80–90A M P L I T U D E (d B F S )–50–30–40–20–1001020304050609009101114 TA01bENCODE INPUTSERIALIZED LVDS OUTPUTS9009101114 TA01CHANNEL 1ANALOG INPUT CHANNEL 2ANALOG INPUTCHANNEL 8ANALOG INPUT • • •• • •/29009101114faabsoluTe MaxiMuM raTings(Notes 1, 2)pin conFiguraTionorDer inForMaTionLEAD FREE FINISH TRAYPART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGELTM9011CY-14#PBF LTM9011CY-14#PBF LTM9011Y14140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C LTM9011IY-14#PBF LTM9011IY-14#PBF LTM9011Y14140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C LTM9010CY-14#PBF LTM9010CY-14#PBF LTM9010Y14140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C LTM9010IY-14#PBF LTM9010IY-14#PBF LTM9010Y14140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C LTM9009CY-14#PBF LTM9009CY-14#PBF LTM9009Y14140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C LTM9009IY-14#PBFLTM9009IY-14#PBFLTM9009Y14140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°CConsult L TC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.For more information on lead free part marking, go to: /leadfree/This product is only offered in trays. For more information go to: /packaging/Supply VoltagesV DD , OV DD ................................................–0.3V to 2V Analog Input Voltage (A IN +, A IN –,PAR/SER , SENSE) (Note 3) ..........–0.3V to (V DD + 0.2V)Digital Input Voltage (ENC +, ENC –, CS ,SDI, SCK) (Note 4) ....................................–0.3V to 3.9V SDO (Note 4) .............................................–0.3V to 3.9V Digital Output Voltage ................–0.3V to (OV DD + 0.3V)Operating Temperature RangeLTM9011C, LTM9010C, LTM9009C .........0°C to 70°C LTM9011I, LTM9010I, LTM9009I .........–40°C to 85°C Storage Temperature Range ..................–55°C to 125°C/39009101114faconverTer characTerisTics The l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. (Note 5)PARAMETERCONDITIONSLTM9011-14LTM9010-14LTM9009-14UNITS MIN TYPMAXMIN TYP MAX MIN TYP MAX Resolution (No Missing Codes)l141414Bits Integral Linearity Error Differential Analog Input (Note 6)l–4.1±1.2 4.1–3.25±1 3.25–2.75±1 2.75LSB Differential Linearity Error Differential Analog Input l –0.9±0.30.9–0.8±0.30.8–0.8±0.30.8LSB Offset Error (Note 7)l –12±312–12±312–12±312mV Gain Error Internal Reference External Referencel–2.6–1.3 –1.3 0–2.6–1.3 –1.3 0–2.6–1.3 –1.3 0%FS %FS Offset Drift ±20±20±20µV/°C Full-Scale Drift Internal ReferenceExternal Reference ±35 ±25±35 ±25±35 ±25ppm/°C ppm/°C Gain Matching External Reference ±0.2±0.2±0.2%FS Offset Matching ±3±3±3mV T ransition NoiseExternal Reference 1.21.21.2LSB RMSanalog inpuTThe l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5)SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN Analog Input Range (A IN + – A IN –) 1.7V < V DD < 1.9Vl 1 to 2V P-P V IN(CM)Analog Input Common Mode (A IN + + A IN –)/2Differential Analog Input (Note 8)l V CM – 100mVV CM V CM + 100mVV V SENSE External Voltage Reference Applied to SENSE External Reference Model0.6251.250 1.300V I INCM Analog Input Common Mode CurrentPer Pin, 125Msps Per Pin, 105Msps Per Pin, 80Msps155 130 100µA µA µAI IN1Analog Input Leakage Current 0 < A IN +, A IN – < V DD , No Encode l –11µA I IN2PAR/SER Input Leakage Current 0 < PAR/SER < V DD l –33µA I IN3SENSE Input Leakage Current0.625 < SENSE < 1.3Vl –66µA t AP Sample-and-Hold Acquisition Delay Time 0ns t JITTER Sample-and-Hold Acquisition Delay Jitter 0.15ps RMSCMRR Analog Input Common Mode Rejection Ratio 80dB BW-3BFull-Power BandwidthFigure 6 Test Circuit 800MHz/DynaMic accuracy The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. A IN = –1dBFS. (Note 5)SYMBOL PARAMETER CONDITIONSLTM9011-14LTM9010-14LTM9009-14UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAXSNR Signal-to-Noise Ratio5MHz Input70MHz Input 140MHz Input l70.873.17372.670.67372.972.669.77372.972.5dBFSdBFSdBFSSFDR Spurious Free Dynamic Range2nd or 3rd Harmonic 5MHz Input70MHz Input140MHz Inputl698885827188858274888582dBFSdBFSdBFSSpurious Free Dynamic Range 4th Harmonic or Higher 5MHz Input70MHz Input140MHz Inputl819090908190909082909090dBFSdBFSdBFSS/(N+D)Signal-to-Noise PlusDistortion Ratio 5MHz Input70MHz Input140MHz Inputl68.47372.67269.77372.67269.672.972.672dBFSdBFSdBFSCrosstalk, Near Channel10MHz Input (Note 12)–90–90–90dBcCrosstalk, Far Channel10MHz Input (Note 12)–105–105–105dBc inTernal reFerence characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. A IN = –1dBFS. (Note 5)PARAMETER CONDITIONS MIN TYP MAX UNITS V CM Output Voltage I OUT = 00.5 • V DD – 25mV0.5 • V DD0.5 • V DD + 25mV V V CM Output Temperature Drift±25ppm/°C V CM Output Resistance–600µA < I OUT < 1mA4ΩV REF Output Voltage I OUT = 0 1.225 1.250 1.275V V REF Output Temperature Drift±25ppm/°C V REF Output Resistance–400µA < I OUT < 1mA7ΩV REF Line Regulation 1.7V < V DD < 1.9V0.6mV/V/49009101114fa59009101114faDigiTal inpuTs anD ouTpuTsThe l denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. (Note 5)SYMBOL PARAMETER CONDITIONSMINTYPMAXUNITSENCODE INPUTS (ENC +, ENC – )Differential Encode Mode (ENC – Not Tied to GND)V ID Differential Input Voltage (Note 8)l 0.2V V ICM Common Mode Input Voltage Internally SetExternally Set (Note 8) l 1.1 1.21.6V V V IN Input Voltage Range ENC +, ENC – to GND l0.23.6V R IN Input Resistance (See Figure 10)10kΩC IN Input Capacitance 3.5pF Single-Ended Encode Mode (ENC – Tied to GND)V IH High Level Input Voltage V DD = 1.8V l 1.2VV IL Low Level Input Voltage V DD = 1.8V l 0.6V V IN Input Voltage Range ENC + to GND l3.6V R IN Input Resistance (See Figure 11)30kΩC IN Input Capacitance 3.5pF DIGITAL INPUTS (CS , SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)V IH High Level Input Voltage V DD = 1.8V l 1.3VV IL Low Level Input Voltage V DD = 1.8V l 0.6V I IN Input Current V IN = 0V to 3.6Vl–1010µA C IN Input Capacitance3pF SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)R OL Logic Low Output Resistance to GND V DD = 1.8V, SDO = 0V 200ΩI OH Logic High Output Leakage Current SDO = 0V to 3.6Vl–1010µA C OUT Output Capacitance 3pFDIGITAL DATA OUTPUTSV OD Differential Output Voltage 100Ω Differential Load, 3.5mA Mode100Ω Differential Load, 1.75mA Mode l l 247 125350 175454 250mV mV V OS Common Mode Output Voltage 100Ω Differential Load, 3.5mA Mode 100Ω Differential Load, 1.75mA Mode l l1.125 1.1251.250 1.250 1.375 1.375V V R TERMOn-Chip Termination ResistanceTermination Enabled, OV DD = 1.8V100Ω/power requireMenTs The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 9)SYMBOL PARAMETER CONDITIONSLTM9011-14LTM9010-14LTM9009-14UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAXV DD Analog Supply Voltage(Note 10)l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9V OV DD Output Supply Voltage(Note 10)l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9V I VDD Analog Supply Current Sine Wave Input l582632476508395450mAI OVDD Digital Supply Current2-Lane Mode, 1.75mA Mode2-Lane Mode, 3.5mA Mode ll549862108529662106509458104mAmAP DISS Power Dissipation2-Lane Mode, 1.75mA Mode2-Lane Mode, 3.5mA Mode ll1145122412491332950103010261105801880914997mWmWP SLEEP Sleep Mode Power222mW P NAP Nap Mode Power170170170mW P DIFFCLK Power Decrease With Single-Ended Encode Mode Enabled(No Decrease for Sleep Mode)404040mWTiMing characTerisTics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at T A = 25°C. (Note 5)SYMBOL PARAMETER CONDITIONSLTM9011-14LTM9010-14LTM9009-14UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAXf S Sampling Frequency(Notes 10,11)l51255105580MHzt ENCL ENC Low Time (Note 8)Duty Cycle Stabilizer OffDuty Cycle Stabilizer On ll3.82441001004.5224.764.761001005.9326.256.25100100nsnst ENCH ENC High Time (Note 8)Duty Cycle Stabilizer OffDuty Cycle Stabilizer On ll3.82441001004.5224.764.761001005.9326.256.25100100nsnst AP Sample-and-HoldAcquisition Delay Time000nsSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Digital Data Outputs (R TERM = 100Ω Differential, C L = 2pF to GND on Each Output)t SER Serial Data Bit Period2-Lanes, 16-Bit Serialization2-Lanes, 14-Bit Serialization2-Lanes, 12-Bit Serialization1-Lane, 16-Bit Serialization1-Lane, 14-Bit Serialization1-Lane, 12-Bit Serialization 1/(8 • f S)1/(7 • f S)1/(6 • f S)1/(16 • f S)1/(14 • f S)1/(12 • f S)sssssst FRAME FR to DCO Delay(Note 8)l0.35 • t SER0.5 • t SER0.65 • t SER s t DATA DATA to DCO Delay(Note 8)l0.35 • t SER0.5 • t SER0.65 • t SER s t PD Propagation Delay(Note 8)l0.7n + 2 • t SER 1.1n + 2 • t SER 1.5n + 2 • t SER s t R Output Rise Time Data, DCO, FR, 20% to 80%0.17ns t F Output Fall Time Data, DCO, FR, 20% to 80%0.17ns DCO Cycle-Cycle Jitter t SER = 1ns60ps P-PPipeline Latency6Cycles /69009101114fa79009101114faSYMBOL PARAMETER CONDITIONSMIN TYPMAXUNITSSPI Port Timing (Note 8)t SCK SCK PeriodWrite ModeRead Back Mode, C SDO = 20pF, R PULLUP = 2kl l 40 250ns ns t S CS to SCK Setup Time l 5ns t H SCK to CS Setup Time l 5ns t DS SDI Setup Time l 5ns t DH SDI Hold Time l5ns t DOSCK Falling to SDO ValidRead Back Mode, C SDO = 20pF, R PULLUP = 2kl125nsTiMing characTerisTicsThe l denotes the specifications which apply over the full operating temperaturerange, otherwise specifications are at T A = 25°C. (Note 5)Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: All voltage values are with respect to GND (unless otherwise noted).Note 3: When these pin voltages are taken below GND or above V DD , they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V DD without latchup.Note 4: When these pin voltages are taken below GND they will beclamped by internal diodes. When these pin voltages are taken above V DD they will not be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND without latchup.Note 5: V DD = OV DD = 1.8V, f SAMPLE = 125MHz (LTM9011), 105MHz (LTM9010), or 80MHz (LTM9009), 2-lane output mode, differential ENC +/ENC – = 2V P-P sine wave, input range = 2V P-P with differential drive, unless otherwise noted.Note 6: Integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. The deviation is measured from the center of the quantization band.Note 7: Offset error is the offset voltage measured from –0.5 LSB when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2’s complement output mode.Note 8: Guaranteed by design, not subject to test.Note 9: V DD = OV DD = 1.8V, f SAMPLE = 125MHz (LTM9011), 105MHz (LTM9010), or 80MHz (LTM9009), 2-lane output mode, differential ENC +/ENC – = 2V P-P sine wave, input range = 2V P-P with differentialdrive, unless otherwise noted. The supply current and power dissipation specifications are totals for the entire device, not per channel.Note 10: Recommended operating conditions.Note 11: The maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. The maximum serial data rate is 1000Mbps so t SER must be greater than or equal to 1ns.Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.7 to Ch.8. Far-channel crosstalk refers to Ch.1 to Ch.7, Ch.1 to Ch.8, Ch.2 to Ch.7, and Ch.2 to Ch.8./89009101114fa2-Lane Output Mode, 14-Bit SerializationANALOG INPUT ENC –ENC +DCO –DCO +9009101114 TD02OUT#A –OUT#A +FR –FR +OUT#B –OUT#B +NOTE THAT IN THIS MODE FR +/FR – HAS TWO TIMES THE PERIOD OF ENC +/ENC –TiMing DiagraMs2-Lane Output Mode, 16-Bit Serialization*ANALOG INPUT ENC –ENC +DCO –DCO +*SEE THE DIGITAL OUTPUTS SECTION9009101114 TD01OUT#A –OUT#A +FR –FR +OUT#B –OUT#B +/99009101114faTiMing DiagraMs2-Lane Output Mode, 12-Bit Serialization1-Lane Output Mode, 16-Bit SerializationANALOG INPUT ENC –ENC +DCO –DCO +OUT#A –OUT#A +FR +FR –OUT#B –OUT#B +ANALOG INPUT ENC –ENC +DCO –DCO +OUT#A –OUT#A +FR –FR +OUT#B +, OUT#B – ARE DISABLED/109009101114faTiMing DiagraMs1-Lane Output Mode, 14-Bit SerializationANALOG INPUT ENC –ENC +DCO –DCO +OUT#A –OUT#A +FR –FR +OUT#B +, OUT#B – ARE DISABLED1-Lane Output Mode, 12-Bit SerializationANALOG INPUT ENC –ENC +DCO –DCO +9009101114 TD07OUT#A –OUT#A +FR –FR +OUT#B +, OUT#B – ARE DISABLED/分销商库存信息:LINEAR-TECHNOLOGYLTM9009CY-14#PBF LTM9009IY-14#PBF LTM9010CY-14#PBF LTM9010IY-14#PBF LTM9011CY-14#PBF LTM9011IY-14#PBF。