TPS3705_IcpdfCom_1454019

TMS370511-07-22-003–SCBS881B–JANUARY2010–REVISED APRIL2010TRANSPONDER BASE STATION ICCheck for Samples:TMS3705FEATURES•Base Station IC for TI-RFid™RF Identification•Short-Circuit ProtectionSystems•Diagnosis•Drives Antenna•Sleep-Mode Supply Current:0.2mA•Sends Modulated Data to Antenna•Designed for Automotive Requirements •Detects and Demodulates Transponder•16-Pin SOIC(D)Package Response(FSK)DESCRIPTIONThe transponder base station IC is used to drive the antenna of a TI-RFid™transponder system,to send data modulated on the antenna signal,and to detect and demodulate the response of the transponder.The response of the transponder is a FSK signal(frequency shift keyed).The high or low bits are coded in two different high-frequency signals(134.2kHz for low bits and123kHz for high bits,nominal).The transponder induces these signals in the antenna coil according an internally stored code.The energy the transponder needs to send out the data is stored in a charge capacitor in the transponder.The antenna field charges this capacitor in a preceding charge phase.The IC has an interface to an external microcontroller.There are two configurations for the clock supply to both the microcontroller and the base station IC:1.Microcontroller and base station IC are supplied with a clock signal derived from only one resonator:Theresonator is attached to the microcontroller.The base station IC is supplied with a clock signal driven by the digital clock output of the microcontroller.The clock frequency is either4MHz or2MHz depending on the selected microcontroller type.2.Both the microcontroller and the base station have their own resonator.The base station IC has a PLL on-chip that generates a clock frequency of16MHz for internal clock supply only. The TMS3705BDRG4is optimized for higher communication data rates and therefore works without frequency measurement during the write phase.ORDERING INFORMATION(1)T A PACKAGE(2)ORDERABLE PART NUMBER TOP-SIDE MARKINGTMS3705A1DRG4TMS3705AG4–40°C to85°C SOIC–D Reel of2500TMS3705BDRG4TMS3705BG4(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TIweb site at .(2)Package drawings,thermal data,and symbolization are available at /packaging.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2010,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.123413141516NC SCIO F_SEL TXCT A_TST D_TST SFB SENSE D PACKAGE (TOP VIEW)567101112OSC2OSC1VSS/VSSB ANT2VSSA ANT189VDDVDDANC –No connectionTMS370511-07-22-003–SCBS881B –JANUARY 2010–REVISED APRIL 2010TERMINAL FUNCTIONSTERMINAL TYPE DESCRIPTION 1SENSE Analog input Input of the RF amplifier 2SFB Analog output Output of the RF amplifier 3D_TST Digital output Test output for digital signals 4A_TST Analog output Test output for analog signals 5ANT1Driver output Antenna output 16VSSA Supply input Ground for the full bridge drivers 7ANT2Driver output Antenna output 28VDDA Supply input Voltage supply for the full bridge drivers 9VDD Supply input Voltage supply for non-power blocks 10OSC2Analog output Oscillator output 11OSC1Analog input Oscillator input12VSS/VSSB Supply inputGround for non-power blocks and PLL 13NC Not connected14SCIO Digital output Data output to the microcontroller15F_SEL Digital input Control input for frequency selection (default value is high)16TXCTDigital input Control input from the microcontroller (default value is high)2Submit Documentation Feedback Copyright ©2010,Texas Instruments IncorporatedA_TSTSFBSENSEVDDA ANT1ANT2VSSAVSSVDDSCIOTXCTD_TSTF_SELOSC2OSC1VSSBTMS370511-07-22-003–SCBS881B –JANUARY 2010–REVISED APRIL 2010FUNCTIONAL BLOCK DIAGRAMPower SupplyThe device is supplied with 5V by an external voltage regulator via two supply pins,one for providing the driver current for the antenna and for supplying the analog part in front of the digital demodulator and one for supplying the other blocks.The power supply supplies a power-on reset that brings the control logic into idle mode as soon as the supply voltage drops under a certain value.In sleep mode the sum of both supply currents is reduced to 0.2mA.The base station device falls into sleep mode 100ms after TXCT has changed to high.When TXCT changes to low or is low,the base station IC immediately goes into and remains in normal operation.Copyright ©2010,Texas Instruments Incorporated Submit Documentation Feedback 3TMS370511-07-22-003–SCBS881B–JANUARY2010–REVISED OscillatorThe oscillator generates the clock of the base station IC of which all timing signals are derived.Between its input and output a crystal or ceramic resonator is connected that oscillates at a typical frequency of4MHz.If a digital clock signal with a frequency of4MHz or2MHz is supplied to pin OSC1,the signal can be used to generate the internal operation frequency of16MHz.The oscillator block contains a PLL that generates the internal clock frequency of16MHz from the input clock signal.The PLL multiplies the input clock frequency depending on the logic state of the input pin F_SEL by a factor of4(F_SEL is high)or by a factor of8(F_SEL is low).In sleep mode the oscillator is switched off.PredriversThe predrivers generate the signals for the four power transistors of the full bridge using the carrier frequency generated by the frequency divider.The gate signals of the p-channel power transistors(active low)have the same width(±1cycle of the16MHz clock),the delay between one p-channel MOSFET being switched off and the other one being switched on is defined to be12cycles of the16MHz clock.In write mode the first activation of a gate signal after a bit pause is synchronized to the received transponder signal by a phase shift of18°.Full BridgeThe full bridge drives the antenna current at the carrier frequency during the charge phase and the active time of the write phase.The minimal load resistance the full bridge sees between its outputs in normal operation at the resonance frequency of the antenna is43.3Ω.When the full bridge is not active,the two driver outputs are switched to ground.Both outputs of the full bridge are protected independently against short-circuits to ground.In case of an occurring short-circuit,the full bridge is switched off in less than10µs in order to avoid a drop of the supply voltage.After a delay time of less than10ms the full bridge is switched on again to test if the short-circuit is still there.An overcurrent due to a resistive short to ground that is higher than the maximum current in normal operation but lower than the current threshold for overcurrent protection does not need to be considered.RF AmplifierThe RF amplifier is an operational amplifier with a fixed internal voltage reference and a voltage gain of5defined by external resistors.It has a high gain-bandwidth product of at least2MHz in order to show a phase shift of less than16°for the desired signal and to give the possibility to use it as a low-pass filter by adapting additional external components.The input signal of the RF amplifier is DC coupled to the antenna.The amplitude of the output signal of the RF amplifier is higher than5mV peak-to-peak.Band-Pass Filter and LimiterThe band-pass filter provides amplification and filtering without external components.The lower cut-off frequency is about a factor of2lower than the average signal frequency of130kHz,the higher cut-off frequency is about a factor of2higher than130kHz.The limiter converts the analog sine-wave signal to a digital signal.It provides a hysteresis depending on the minimal amplitude of its input signal.The duty cycle of its digital output signal is between40%and60%.The band-pass filter and the limiter together have a high gain of at least1000.4Submit Documentation Feedback Copyright©2010,Texas Instruments IncorporatedTMS3705 11-07-22-003–SCBS881B–JANUARY2010–REVISED APRIL2010DiagnosisThe diagnosis is carried out during the charge phase to detect whether the full bridge and the antenna are working.When the full bridge drives the antenna,the voltage across the coil exceeds the supply voltage so that the voltage at the input of the RF amplifier is clamped by the ESD-protection diodes.For diagnosis,the SENSE pin is loaded on-chip with a switchable resistor to ground so that the internal switchable resistor and the external SENSE resistor form a voltage divider,while the internal resistor is switched off in read mode.When the voltage drop across the internal resistor exceeds a certain value,the diagnosis block passes the frequency of its input signal to the digital demodulator.The frequency of the diagnosis signal is accepted,if eight subsequent time can be detected,all with their counter state within the range of112to125,during the diagnosis time(at most0.1 ms).The output signal is used during the charge phase only else it is ignored.When the short-circuit protection switches off one of the full-bridge drivers,the diagnosis also indicates an improper operation of the antenna by sending the same diagnostic byte to the microcontroller as for the other failure mode.During diagnosis,the antenna drivers are active.In synchronous mode the antenna drivers remain active up to1 ms after the diagnosis is performed,without any respect to the logic state of the signal at TXCT(thus enabling the microcontroller to clock out the diagnosis byte).Power-On ResetThe power-on reset generates an internal reset signal to allow the control logic to start up in the defined way. Frequency DividerThe frequency divider is a programmable divider that generates the carrier frequency for the full-bridge antenna drivers.The default value for the division factor is the value119needed to provide the nominal carrier frequency of134.45kHz generated from16MHz.The resolution for programming the division factor is one divider step that corresponds to a frequency shift of about1.1kHz.The different division factors needed to cover the range of frequencies for meeting the resonance frequency of the transponder are114to124.Digital DemodulatorThe input signal of the digital demodulator comes from the limiter and is frequency-coded according to the high-and low-bit sequence of the transmitted transponder code.The frequency of the input signal is measured by counting the oscillation clock for the time period of the input signal.As the high-bit and low-bit frequencies are specified with wide tolerances,the demodulator is designed to distinguish the high-bit and the low-bit frequency by the shift between the two frequencies and not by the absolute values.The threshold between the high-bit and the low-bit frequency is defined to be6.5kHz lower than the measured low-bit frequency and has a hysteresis of ±0.55kHz.The demodulator is controlled by the control logic.After the charge phase(that is during read or write phase)it measures the time period of its input signal and waits for the transponder resonance-frequency measurement to determine the counter state for the threshold between high-bit and low-bit frequency.Then the demodulator waits for the occurrence of the start bit.For that purpose,the results of the comparisons between the measured time periods and the threshold are shifted in a12-bit shift register.The detection of the start bit comes into effect when the contents of the shift register matches a specific pattern,indicating8subsequent periods below the threshold immediately followed by4subsequent periods above the threshold.A2-period digital filter is inserted in front of the12-bit shift register to make a start bit detection possible in case of a non-monotonous progression of the time periods during a transition from low-to high-bit frequency.The bit stream detected by the input stage of the digital demodulator passes a digital filter before being evaluated.After demodulation,the serial bit flow received from the transponder is buffered byte-wise before being sent to the microcontroller by SCI encoding.Copyright©2010,Texas Instruments Incorporated Submit Documentation Feedback5TMS370511-07-22-003–SCBS881B–JANUARY2010–REVISED Transponder Resonance-Frequency MeasurementDuring the pre-bit reception phase,the bits the transponder transmits show the low-bit frequency,which is the resonance frequency of the transponder.The time periods of the pre-bits are evaluated by the demodulator counter.Based on the counter states,an algorithm is implemented that guarantees a correct measurement of the transponder’s resonance frequency:1.A time period of the low-bit frequency has a counter state between112and125.2.The measurement of the low-bit frequency(the average of eight subsequent counter states)is acceptedduring the write mode,when the eight time periods have counter states in the defined range.The measurement during write mode is started with the falling edge at TXCT using the fixed delay time at which end the full bridge is switched on again.3.The counter state of the measured low-bit frequency results in the average counter state of an acceptedmeasurement and can be used to update the register of the programmable frequency divider.4.The measurement of the low-bit frequency(the average of eight subsequent counter states)is acceptedduring the read mode,when the eight time periods have counter states in the defined range.The start of the measurement during read mode is delayed in order to use a stable input signal for the measurement.5.The threshold to distinguish between high-bit and low-bit frequency is calculated to be by a value of5or7(see hysteresis in threshold)higher than the counter state of the measured low-bit frequency.SCI EncoderAn SCI encoder performs the data transmission to the microcontroller.As the transmission rate of the transponder is lower than the SCI transmission rate,the serial bit flow received from the transponder is buffered after demodulation and before SCI encoding.The SCI encoder uses an8-bit shift register to send the received data byte-wise(least significant bit first)to the microcontroller with a transmission rate of15.625kbaud(±1.5%),one start bit(high)and one stop bit(low),but no parity bit(asynchronous mode indicated by the SYNC bit of the mode control register permanently low).The data bits at the SCIO output are inverted with respect to the corresponding bits sent by the transponder.The transmission starts after the reception of the start bit.The start byte detection is initialized with the first rising edge.Typical values for the start byte are81_H or01_H(at SCIO).The start byte is the first byte to be sent to the microcontroller.The transmission stops and the base station returns to idle state when TXCT becomes low or 20ms after the beginning of the read phase.TXCT remains low for at least128µs to stop the read phase and less than900µs to avoid starting the next transmission cycle.The SCI encoder also sends the diagnostic byte2ms after beginning of the charge phase.In case of a normal operation of the antenna,the diagnostic byte AF_H is sent.If no antenna oscillation can be measured or if at least one of the full-bridge drivers is switched off due to a detected short-circuit,the diagnostic byte FF_H is sent to indicate the failure mode.The SCI encoder can be switched into a synchronous data transmission mode by setting the mode control register bit SYNC to high.In this mode,the output SCIO indicates by a high state that a new byte is ready to be transmitted.The microcontroller can receive the eight bits at SCIO when sending the eight clock signals(falling edge means active)for the synchronous data transmission via pin TXCT to the SCI encoder.Control LogicThe control logic is the core of the TMS3705circuit.It contains a sequencer or a state machine that controls the global operations of the base station(see Figure1).This block has a default mode configuration but can also be controlled by the microcontroller via the TXCT serial input pin to change the configuration and to control the programmable frequency divider.For that purpose a mode control register is implemented in this module that can be written by the microcontroller.6Submit Documentation Feedback Copyright©2010,Texas Instruments Incorporated(1)In SCI synchronous mode,this transition always occurs approx.3ms after leaving Idle state (diag.byte trans mis sion should be completed before).(2)A falling edge on TXCT interrupts the Receive phase after a delay of 0.9ms.TXCT must remain low for at least 128m s.If TXCT is still low after the 0.9ms delay,the basestation will go to Idle and directly to the Diagnosis phase one clock cycle later (Dotted line (3)).No MCR can be written,o n ly default mode is fully supported in this case.Otherwise,if TXCT returns to high and remains high during the delay,the basestation will s tay in Idle and wait for TXCT to go low (this will start properly a new MCR programming)or wait for 100m s to go to Sleep.Notes :(4)A falling edge on TXCT interrupts the Sleep state.Only default mode is fully supported when starting an oper ationfrom Sleep with only one falling edge on TXCT (because of the 2m s delay).For a proper M CR programming,TXCT has to return to high and remain high during this delay.(3)This transition only occurs in a special case (see note (2))(5)Idle mode is the next state in cas e of undefined sataes ('fail s afe state machine')Frequency measurement only available for TMS3705A1DRG4(6)TMS370511-07-22-003–SCBS881B –JANUARY 2010–REVISED APRIL 2010Figure 1.Operational State Diagram for the Control LogicCopyright ©2010,Texas Instruments IncorporatedSubmit Documentation Feedback 7TMS370511-07-22-003–SCBS881B–JANUARY2010–REVISED The default mode is a read-only mode that uses the default frequency as the carrier frequency for the full bridge. Therefore the mode control register does not need to be written(it is filled with low states),and the communication sequence between microcontroller and base station starts with TXCT being low for a fixed time to initiate the charge phase.When TXCT becomes high again,the module enters the read phase and the data transmission via the SCIO pin to the microcontroller starts.There is another read-only mode that differs from the default mode only in the writing of the mode control register before the start of the charge phase.The way that the mode control register is filled and the meaning of its contents is described below.The write-read mode starts with the programming of the mode control register.Then the charge phase starts with TXCT being low for a fixed time.When TXCT becomes high again,the write phase begins in which the data are transmitted from the microcontroller to the transponder via the TXCT pin,the control logic,the predrivers,and the full bridge by amplitude modulation of100%with a fixed delay time.After the write phase TXCT goes low again to start another charge or program phase.When TXCT becomes high again,the read phase begins.The contents of the mode control register define the mode and the way that the carrier frequency generated by the frequency divider is selected in order to meet the transponder resonance frequency as good as possible.Table1.Mode Control Register(7-Bit Register)BIT RESETDESCRIPTIONVALUENAME NO.START_BIT Bit00START_BIT=0The start bit is always low and does not need to be stored.DATA_BIT[4:1]=0000Microcontroller selects division factor119DATA_BIT1Bit10DATA_BIT[4:1]=1111Division factor is adapted automatically(1)DATA_BIT[4:1]=0001Microcontroller selects division factor114DATA_BIT2Bit20DATA_BIT[4:1]=0010Microcontroller selects division factor115......DATA_BIT3Bit30DATA_BIT[4:1]=0110Microcontroller selects division factor119......DATA_BIT4Bit40DATA_BIT[4:1]=1011Microcontroller selects division factor124SCI_SYNC=0Asynchronous data transmission to the microcontrollerSCI_SYNC Bit50SCI_SYNC=1Synchronous data transmission to the microcontrollerRX_AFC=0Demodulator threshold is adapted automaticallyRX_AFC Bit60RX_AFC=1Demodulator threshold is defined by DATA_BIT[4:1]TEST_BIT=0No further test bytesTEST_BIT Bit70TEST_BIT=1Further test byte follows for special test modes(1)Only available for TMS3705A1DRG4The TMS3705A1DRG4can adjust the carrier frequency to the transponder resonance frequency automatically by giving the counter state of the transponder resonance-frequency measurement directly to the frequency divider by setting the first four bits in high state.This setting is not available for TMS3705BDRG4.The other combinations of the first four bits allow the microcontroller to select the default carrier frequency or to use another frequency.The division factor can be selected to be between114and124.Some bits for testability reasons can be added.The default value of these test bits for normal operation is low. Especially the bit7called TEST_BIT is Low for normal operation;otherwise the base station may enter one of the test modes.The control logic also controls the demodulator,the SCI encoder,the diagnosis,and especially the transmission of the diagnosis byte during the charge phase.The state diagram in Figure1shows the general behavior of the state machine(note that the state blocks drawn can contain more than one state).All given times are measured from the moment when the state is entered if not specified otherwise.8Submit Documentation Feedback Copyright©2010,Texas Instruments IncorporatedTMS3705 11-07-22-003–SCBS881B–JANUARY2010–REVISED APRIL2010Test PinsThe IC has an analog test pin A_TST for the analog part of the receiver.The digital output pin D_TST is used for testing the internal logic.Both pins need not be connected in the application.Copyright©2010,Texas Instruments Incorporated Submit Documentation Feedback9TMS370511-07-22-003–SCBS881B–JANUARY2010–REVISED ABSOLUTE MAXIMUM RATINGS(1)over operating free-air temperature range(unless otherwise noted)V DD Supply voltage range VDD,VSS/VSSB,VDDA,VSSA–0.3V to7VV OSC Voltage range OSC1,OSC2–0.3V to(V DD+0.3)VV inout Voltage range SCIO,TXCT,F_SEL,D_TST–0.3V to(V DD+0.3)VI inout Overload clamping current SCIO,TXCT,F_SEL,D_TST–5mA to5mAV ANT Output voltage ANT1,ANT2–0.3V to(V DD+0.3)VI ANT Output peak current ANT1,ANT2–1.1A to1.1AV analog Voltage range SENSE,SFB,A_TST–0.3V to(V DD+0.3)VI SENSE SENSE input current SENSE,SFB,A_TST–5mA to5mAI SFB Input current in case of overvoltage SFB–5mA to5mAT A Operating ambient temperature–40°C to85°CT stg Storage temperature range–55°C to150°CR q JA Thermal resistance,junction to free air130°C/WP D Total power dissipation at T A=85°C0.5WV ESD ESD protection(MIL STD883)–2000V to2000V(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONSMIN NOM MAX UNIT V DD Supply voltage VDD,VSS/VSSB,VDDA,VSSA 4.55 5.5Vf osc Oscillator frequency OSC1,OSC24MHz V IH High-level input voltage F_SEL,TXCT,OSC10.7V DD VTXCT,OSC10.3V DDV IL Low-level input voltage VF_SEL0.2V DDI OH High-level output current SCIO,D_TST–1mAI OL Low-level output current SCIO,D_TST1mA 10Submit Documentation Feedback Copyright©2010,Texas Instruments IncorporatedTMS3705 11-07-22-003–SCBS881B–JANUARY2010–REVISED APRIL2010ELECTRICAL CHARACTERISTICSV DD=4.5V to5.5V,f osc=4MHz,F_SEL=high,over operating free-air temperature range(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply(VDD,VSS/VSSB,VDDA,VSSA)Sum of supply currents in charge phase,I DD Supply current820mAwithout antenna loadSum of supply currents in sleep mode,without mAI SLEEP Supply current,sleep mode0.0150.2I/O currentsOscillator(OSC1,OSC2)g osc Transconductance f osc=4MHz,0.5V pp at OSC10.525mA/V C in Input capacitance at OSC1(1)10pFC out Output capacitance at OSC2(1)10pF Logic Inputs(TXCT,F_SEL,OSC1)TXCT120500R pullup Pullup resistance kΩF_SEL10500Logic Outputs(SCIO,D_TST)V OH High-level output voltage0.8V DD VV OL Low-level output voltage0.2V DD V Full-Bridge Outputs(ANT1,ANT2)Full bridge n-channel and p-channel MOSFETsΣR ds_on Sum of drain-source resistances714Ωat driver current I ant=50mADuty cycle p-channel MOSFETs of full bridge384042%Symmetry of pulse widths for thet on1/t on296104.5% p-channel MOSFETs of full bridgeThreshold for overcurrentI oc2201100mAprotectionSwitch-off time of overcurrentt oc Short to ground with3Ω0.2510µs protectionDelay for switching on the fullt doc2 2.05 2.1ms bridge after an overcurrentI leak Leakage current1µA Analog Module(SENSE,SFB,A_TST)I SENSE Input current SENSE,In charge phase–22mAV DCREF/DC reference voltage of RF9.251011%V DD amplifier,related to VDDAt500kHz with external components toGain-bandwidth product of RFGBW achieve a voltage gain of minimum4-mV pp and2MHz amplifier5-mV pp input signalAt134kHz with external components tof O Phase shift of RF amplifier achieve a voltage gain of5-mV pp and20-mV pp16°input signalPeak-to-peak input voltage of bandAt134kHz(corresponds to a minimal total gainV sfb pass at which the limiter5mVof1000)comparator should toggle(2)Lower cut-off frequency off low2460100kHzband-pass filter(3)Higher cut-off frequency off high160270500kHzband-pass filter(3)A_TST pin used as input,D_TST pin as output,ΔV hys Hysteresis of limiter2550135mVOffset level determined by bandpass stage(1)Specified by design(2)Specified by design;functional test done for input voltage of90mV pp.(3)BP filter tested at three different frequencies:f mid=134kHz and gain>30db;f low=24kHz,f high=500kHz and attenuation<–3dB(reference=measured gain at f mid=134kHz).Copyright©2010,Texas Instruments Incorporated Submit Documentation Feedback11TMS370511-07-22-003–SCBS881B–JANUARY2010–REVISED ELECTRICAL CHARACTERISTICS(continued)V DD=4.5V to5.5V,f osc=4MHz,F_SEL=high,over operating free-air temperature range(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Diagnosis(SENSE)Current threshold for operatingI diag80240µAantenna(4)Phase-Locked Loop(D_TST)f pll PLL frequency15.9841616.0166MHz Δf/f pll Jitter of the PLL frequency6% Power-On Reset(POR)V por_r POR threshold voltage,rising V DD rising with low slope 1.9 3.5VV por_f POR threshold voltage,falling V DD falling with low slope 1.3 2.6V (4)Internal resistance switched on and much lower than external SENSE resistance.SWITCHING CHARACTERISTICSV DD=4.5V to5.5V,f osc=4MHz,F_SEL=high,over operating free-air temperature range(unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNITFrom start of the oscillator afterpower-on or waking up until reachingt init min Time for TXCT high to initialize a new transmission2 2.05 2.2msthe idle mode(see Figure2,Figure3,Figure4)Delay between leaving idle mode and start of Normal operation(see Figure2,t diag2 2.12 2.2ms diagnosis byte at SCIO Figure3,Figure4)Delay between end of charge or end of program andt R See Figure2,Figure3,Figure4)3ms start of transponder data transmit on SCIOt off Write pulse pause See Figure60.1mst dwrite Signal delay on TXCT for controlling the full bridge Write mode737985µst mcr NRZ bit duration for mode control register See Figure5121128135µst sci NRZ bit duration on SCIO Asynchronous mode(see Figure7)636465µst dstop Low signal delay on TXCT to stop Synchronous mode128800µst t_sync Total TXCT time for reading data on SCIO Synchronous mode(see Figure8)900µst sync TXCT period for shifting data on SCIO Synchronous mode(see Figure8)464100µst L_sync Low phase on TXCT Synchronous mode(see Figure8)232t sync–2µst ready Data ready for output after SCIO goes high Synchronous mode(see Figure8)1127µs 12Submit Documentation Feedback Copyright©2010,Texas Instruments Incorporated。

1234525µs/DIV3705 G06V INNDRVV CC1µs/DIV3705 G07TG FB/INFS/IN –40ms/DIV3705 G08BGSSFLTUUUPI FU CTIO SGND (Pin 1): Signal Ground.I S (Pin 2): Input to the Overcurrent Comparator. Connect to the positive terminal of a current-sense resistor in series with the source of the ground-referenced bottom MOSFET.V SLMT (Pin 3): Volt-Second Limit. Form an R-C integrator by connecting a resistor from V IN to V SLMT and a capacitor from V SLMT to ground. The gate drives are turned off when the voltage on the V SLMT pin exceeds 1.25V.UVLO (Pin 4): Undervoltage Lockout. Connect to a resis-tive voltage divider to monitor input voltage V IN. Enables converter operation for V UVLO > 1.242V. Hysteresis is a fixed 16mV hysteresis voltage with a 4.9µA hysteresis current that combines with the Thevenin resistance of the divider to set the total UVLO hysteresis voltage. This input also senses V IN for voltage feedforward. Finally, this pin can be used for external run/stop control.SSFLT (Pin 5): Combination Soft-Start and Fault Indica-tor. A capacitor to GND sets the duty cycle ramp-up rate during start-up. To indicate a fault, the SSFLT pin is momentarily pulled up to within 1.3V of V CC.NDRV (Pin 6): Drive for the External NMOS of the Linear Regulator. Connect to the gate of the NMOS and connect a pull up resistor to the input voltage V IN. Optionally, to create a trickle charger omit the NMOS device and connect NDRV to V CC.FB/IN+ (Pin 7): This pin has several functions. The two terminals of one pulse transformer winding are connected to the FB/IN+ and FS/IN– pins. The other pulse transformer winding is connected to the LTC3706. The LTC3705 automatically detects when the LTC3706 applies a pulse-encoded signal to the FB/IN+ and FS/IN– pins and decodes duty cycle information for control of the primary-side gate drives (see Operation below). In secondary-side control, primary-side gate drive bias power is also extracted from the FB/IN+ and FS/IN– pins using an on-chip full-wave rectifier.For primary-side control connect this pin to an optoisolator for feedback control of converter output voltage using an internal optoisolator biasing network.FS/IN– (Pin 8): This pin has several functions. Place a resistor from this pin to GND to set the oscillator fre-quency. For secondary-side control with the LTC3706, connect one winding of the pulse transformer for opera-tion as described for the FB/IN+ pin above.PGND (Pin 9): Supply Return for the Bottom Gate Driver and the On-Chip Bridge Rectifier.BG (Pin 10): Bottom Gate Driver. Connect to the gate of the “low side” external MOSFET.V CC (Pin 11): Main V CC Power for All Driver and Control Circuitry.NC (Pins 12, 13): Voltage Isolation Pins. No connection. Provided to allow adequate clearance between high-volt-age pins (BOOST, TG, and TS) and the remainder of the pins.BOOST (Pin 14): Top Gate Driver Supply. Connect to V CC with a diode to supply power to the “high side” external MOSFET and bypass with a capacitor to TS.TG (Pin 15): Top Gate Driver. Connect to the gate of the “high side” external MOSFET.TS (Pin 16): Supply Return for the Top Gate Driver. Connect to the source of the “high side” external MOSFET.63705fb78Self-Starting ArchitectureThe LTC3705 is combined with the LTC3706 to form a complete self-starting DC isolated power supply. When power is first applied, and when V CC for the LTC3705 is above the appropriate threshold, the LTC3705 begins open-loop operation using its own internal oscillator. Power is supplied to the secondary by switching the gate drivers with a gradually increasing duty cycle as controlled by the rate of rise of the voltage on the SSFLT pin. A peak detector power supply for the LTC3706 allows it to begin operation even for small duty cycles. Once adequate voltage is available for the LTC3706, it provides duty cycle information and gate drive bias power using the pulse transformer as shown in Figure 1. The LTC3705 detects the appearance of this signal and transfers control of the gate drivers to the LTC3706. Simultaneously, the LTC3705 also enables the on-chip rectifier and turns off the linear regulator.Alternately, when the LTC3705 is used as a standalone primary-side controller, the gradually increasing duty cycle powers up a secondary-side reference and optoisolator and feedback is accomplished when the output of the optoisolator begins pulling down in the FB/IN+ pin. Soft-Start and FaultThese two functions are implemented using the SSFLT pin. (This pin is also used for linear regulator timeout as described in the following section.)Initiating soft-start requires that: 1) the gate drive undervoltage (UVGD) goes low meaning that adequate voltage is available on the V CC pin (7.4V for the linear regulator or 13.4V for the trickle charger) and 2) the input undervoltage (UVV IN) goes low meaning that the voltage on the UVLO pin has reached the 1.242V rising threshold. During soft-start, the LTC3705 gradually charges the soft-start capacitor to ramp up the converter duty cycle. Soft-start is over when the voltage on the SSFLT pin reaches 2.8V. In normal operation, at some point before this, the LTC3705 makes a transition to controlling duty cycle using closed-loop regulation of the converter output voltage.The SSFLT pin is also used to indicate a fault. The LTC3705 recognizes faults from four origins: 1) an overcurrent fault caused by the current sense voltage on the IS pin exceed-ing the 300mV overcurrent threshold, 2) an input undervoltage fault caused by the UVLO pin falling below the 1.226V falling threshold, 3) a gate drive undervoltage fault caused by the voltage on the V CC pin falling below the 7V threshold, or 4) loss of the gate drive encoding signal from the LTC3706.Upon sensing a fault, the LTC3705 immediately turns off the top and bottom gate drives and indicates a fault by quickly pulling the voltage on the SSFLT pin to within 1.3V of the voltage on the V CC pin. After indicating the fault, the LTC3705 quickly ramps down the voltage on the SSFLT pin to approximately 2.8V. Then, to allow complete dis-charge of the secondary-side circuit, the LTC3705 slowly ramps down the voltage on the SSFLT pin to about 200mV. The LTC3705 then attempts a restart.Linear Regulator TimeoutThe thermal rating of the linear regulator’s external NMOS often cannot allow it to indefinitely supply bias current to the primary-side gate drives. The LTC3705 has a linear regulator timeout mechanism that also uses the SSFLT capacitor.As described in the prior section, soft-start is over once the voltage on the SSFLT pin reaches 2.8V. However, the SSFLT capacitor continues to charge and the linear regu-lator is turned off when the voltage on the SSFLT pin reaches 3.9V. The “Applications Information” section de-scribes linear regulator timeout in more detail.Volt-Second LimitThe volt-second limit ensures that the power transformer core does not saturate for any combination of duty cycle and input voltage. The input of an R-C integrator is connected to V IN and its output is connected to the V SLMT pin. While the top and bottom gate drives are “off,” the LTC3705 grounds the V SLMT pin. When the gate drives are turned “on” the V SLMT pin is released and the capacitor is allowed to charge in proportion to V IN. If the capacitor voltage on the V SLMT pin exceeds 1.25V the two gate drives are immediately turned “off.” Note that this is not considered a fault condition and the LTC3705 can run indefinitely with the switch duty cycle being determined byOPERATIO93705fb103705fbUVLOThe UVLO pin is connected to a resistive voltage divider connected to V IN as shown in Figure 2. The voltage threshold on the UVLO pin for V IN rising is 1.242V. To introduce hysteresis, the LTC3705 draws 4.9µA from the UVLO pin when V IN is rising. The hysteresis is therefore user adjustable and depends on the value of R1. The UVLO threshold for V IN rising is:V V R R R R A IN UVLO RISING (,)(.)(.)=++µ1242122149the volt-second limit circuit. The duty cycle is always limited to 50% to ensure that the power transformer flux always has time to reset before the start of the next cycle.In an alternate application, the volt-second limit can be used for open-loop regulation of the output against changes in V IN .Current LimitCurrent limit for the LTC3705 is principally a safety feature to protect the converter and is not part of a control function. The current that flows in series through the top switch, the transformer primary, and the bottom switch is sensed by a resistor connected between the source of the bottom switch and GND. If the voltage across this resistor exceeds 300mV, the LTC3705 initiates a fault.Bootstrap RefreshThe LTC3705 incorporates a unique bootstrap refresh circuit to ensure that the bootstrap supply (BOOST) for the top switch has adequate voltage for operation at low duty cycles. Therefore, the LTC3705 does not require a undervoltage lockout for the bootstrap supply and a po-tential source of unexpected shutdowns is eliminated.Voltage FeedforwardThe LTC3705 uses voltage feedforward to properly modu-late the duty cycle as a function of the input voltage. For secondary-side control with the LTC3706, voltage feedforward is used during start-up only. The duty cycleduring start up is determined by comparison of the voltage on the SSFLT pin to a 50% duty cycle triangle wave with an amplitude of 2V. To implement voltage feedforward, the charging current for the soft-start capacitor is reduced in proportion to the input voltage. As a result, the initial rate of rise of the converter output voltage is held approxi-mately constant regardless of the input voltage. At some point during start-up, the LTC3706 begins to switch the pulse transformer and takes over the soft-start.For operation with standalone primary-side control and optoisolator feedback, voltage feedforward is used during both start-up and normal operation. The duty cycle is determined by using a 50% duty cycle triangle wave with an amplitude equal to 66% of the voltage on the UVLO pin which is, in turn, proportional to V IN . The charging current for the soft-start capacitor is a constant 5.2µA. During soft-start, the duty cycle is determined by comparing the voltage on the SSFLT pin to the triangle wave. Soft-start is concluded when the voltage on the SSFLT pin exceeds the voltage on the FB/IN + pin. After the conclusion of soft-start, the duty cycle is determined by comparison of the voltage on the FB/IN + pin to the triangle wave.Optoisolator BiasWhen the LTC3705 is used in standalone primary-side mode, feedback is provided by an optoisolator connected to the FB/IN + pin. The LTC3705 has a built optoisolator bias circuit which eliminates the need for external components.OPERATIOAPPLICATIO S I FOR ATIOW UUU The LTC3705 also has 16mV of voltage hysteresis on the UVLO pin so that the UVLO threshold for V IN falling is:V V R R R IN UVLO FALLING (,)(.)=+1226122To implement external Run/Stop control, connect a small NMOS to the UVLO pin as shown in Figure 2. Turning the NMOS on grounds the UVLO pin and prevents the LTC3705from running.11123705fbIn the event that a short-circuit is applied to the output of the converter prior to start-up, the LTC3706 generally does not receive enough bias voltage to operate. In this case, the LTC3705 detects a FAULT for one of two reasons:1) since the LTC3706 never sends pulse encoding to the LTC3705, the linear regulator times out resulting in a gate drive undervoltage fault, or 2) the primary-side overcurrent circuit is tripped because of current buildup in the output inductor. In either case, the LTC3705 initiates a shutdown followed by a soft-start retry.Linear Regulator TimeoutAfter start-up, the LTC3705 times out the linear regulator to prevent overheating of the external NMOS. The timeout interval is set by further charging the soft-start capacitor C SSFLT from the end-of-soft-start voltage of approximately 2.8V to the timeout threshold of 3.9V. Linear regulator timeout behaves differently depending on mode.In primary-side standalone mode, the LTC3705 generally requires that an auxiliary gate drive bias supply take over from the linear regulator. (See the subsequent section for more detail on the auxiliary supply.) During linear regula-tor timeout, the rate of rise of the soft-start capacitor voltage depends on the current into the NDRV pin as controlled by the pull-up resistor R PULLUP , the value of V IN and the value of V NDRV .I V V R NDRV IN NDRV PULLUP=–The value of V NDRV is V CC = 8V plus the value of the gate-to-source voltage (V NDRV – V CC ) of the external NMOS in the linear regulator. The gate-to-source voltage depends on the actual device but is approximately the threshold voltage of the external NMOS.For I NDRV > 0.27mA, the capacitor on the SSFLT pin is charged in proportion to (I NDRV – 0.27mA) until the linear regulator times out. Thus, since V NDRV is very nearly constant, the timeout interval for the linear regulator is inversely proportional to the input voltage and a higher input voltage produces a shorter timeout.t C V V V V R mA TIMEOUT SSFLT IN NDRV PULLUP =−⎡⎣⎢⎤⎦⎥663928027(.–.)–.Since the power dissipation of the linear regulator isproportional to the input voltage, this strategy of making the timeout inversely proportional to the input voltage produces an approximately constant temperature excur-sion for the external NMOS of the linear regulator regard-less of the input voltage.In situations for which the continuous operation of the linear regulator does not exceed the thermal limitations of the external NMOS (i.e. converters with low V IN or with minimal gate drive bias requirements), the auxiliary sup-ply can be omitted and the linear regulator allowed to operate continuously. If I NDRV is less than 0.27mA the linear regulator never times out and the voltage on the SSFLT pin stays at approximately 2.8V after start-up is completed. To accomplish this set:R V V mAPULLUP IN MAX NDRV>()–.027where V IN(MAX) is the maximum expected continuous input voltage. Note that once the linear regulator is turned off it locks out. Therefore when using this strategy, care should be taken to ensure that a transient higher than V IN(MAX) does not persist longer than t TIMEOUT .In secondary-side operation with the LTC3706, there is never any need for continuous operation of the linear regulator since gate drive bias power is provided by the LTC3706 through the pulse transformer and on-chip rectifier. The LTC3705 shuts down the linear regulator once the LTC3706 begins switching the pulse trans-former. If the LTC3706 fails to start, the LTC3705 quickly times out the linear regulator once the voltage on the SSFLT pin reaches 2.8V.Fault LockoutThe LTC3705 indicates a fault by pulling the SSFLT pin to within 1V of V CC . The LTC3705 subsequently attempts a restart. Optionally, the user can prevent restart and “lock out” the converter by clamping the voltage on the SSFLT pin with a 4.3V Zener diode. Once the converter has locked out it can only be restarted by the removal of the input voltage or by release of the Zener diode clamp.APPLICATIO S I FOR ATIOW UUU13143705fbGrounding ConsiderationsThe LT3705 is typically used in high current converter designs that involve substantial switching transients. Fig-ure 5 illustrates these currents. The switch drivers on the IC are designed to drive large capacitances and, as such,generate significant transient currents. Careful consider-ation must be made regarding input and local power supply bypassing to avoid corrupting the ground refer-ences used by the UVLO and frequency set circuitry.Typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from GND. By virtue of the topologies used in LT3705applications, the large currents from the primary switches,as well as the switch drive transients, pass through the sense resistor to ground. This defines the ground connec-tion of the sense resistor as the reference point for both GND and PGND.Effective grounding can be achieved by considering the return current paths from the sense resistor to each respective bypass capacitor. Don’t be tempted to run small traces to separate the grounds. A power ground plane is important as always in high power converters, but care must be taken to keep high current paths away from the GND reference. An effective approach is to use a 2-layer ground plane, reserving an entire layer for GND and an entire layer for PGND. The UVLO and frequency set resistors can then be directly connected to the GND plane.For the LTC3706, the master performs soft-start and voltage-loop regulation by driving all slaves to the same current as the master using the I TH pins. Faults and shutdowns are communicated via the interconnection of the RUN/SS pins. The LTC3706 is put into slave mode by tying the FB pin to V CC .Standalone Primary-Side OperationThe LTC3705 can be used to implement a standalone forward converter using optoisolator feedback and a secondary-side voltage reference. Alternately the LTC3705can be used to implement an open-loop forward converter using the VSLMT pin to regulate against changes in V IN . In either case, the LTC3705 oscillator determines the fre-quency as found from:f R OSC FS P =+211042009•()Note that polyphase operation is not possible in the stand-alone configuration.APPLICATIO S I FOR ATIOW UUU1516171819Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.20Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● © LINEAR TECHNOLOGY CORPORA TION 2005LT 1006 REV B • PRINTED IN USA。

LM3704/LM3705Microprocessor Supervisory Circuits with Power Fail Input,Low Line Output and Manual ResetGeneral DescriptionThe LM3704/LM3705series of microprocessor supervisory circuits provide the maximum flexibility for monitoring power supplies and battery controlled functions in systems without backup batteries.The LM3704/LM3705series are available in MSOP-10and 9-bump micro SMD packages.Built-in features include the following:Reset:Reset is asserted during power-up,power-down,and brownout conditions.RESET is guaranteed down to V CC of 1.0V.Manual Reset Input:An input that asserts reset when pulled low.Power-Fail Input:A 1.225V threshold detector for power fail warning,or to monitor a power supply other than V CC .Low Line Output:This early power failure warning indicator goes low when the supply voltage drops to a value which is 2%higher than the reset threshold voltage.Featuresn Standard Reset Threshold voltage:3.08Vn Custom Reset Threshold voltages:For other voltages between 2.2V and 5.0V in 10mV increments,contact National Semiconductor Corp.n No external components required n Manual-Reset inputn RESET (LM3704)or RESET (LM3705)outputs n Precision supply voltage monitorn Factory programmable Reset Timeout Delay n Separate Power Fail comparatorn Available in micro SMD package for minimum footprint n ±0.5%Reset threshold accuracy at room temperature n±2%Reset threshold accuracy over temperature extremesn Reset assertion down to 1V V CC (RESET option only)n 28µA V CC supply currentApplicationsn Embedded Controllers and Processors n Intelligent Instruments n Automotive SystemsnCritical µP Power MonitoringTypical Application10136903July 2002LM3704/LM3705Microprocessor Supervisory Circuits with Power Fail Input,Low Line Output and Manual Reset©2002National Semiconductor Corporation Connection DiagramMSOP-10Top View(looking from the coating side)micro SMD 9Bump PackageBPA091013690210136901Pin DescriptionPin Functionmicro SMD MSOP A12MR Manual-Reset input.When MR is less than V MRT (Manual Reset Threshold)RESET/RESET is engaged.B11V CC Power Supply input.C110RESETReset Logic Output.Pulses low for t RP (Reset Timeout Period)when triggered,and stays low whenever V CC is below the reset threshold or when MR is below V MRT .It remains low for t RP after either V CC rises above the reset threshold,or after MR input rises above V MRT (LM3704only).RESETReset Logic Output.RESET is the inverse of RESET (LM3705only).C28PFO Power-Fail Logic Output.When PFI is below V PFT ,PFO goes low;otherwise,PFO remains high.C37LLOLow-Line Logic Output.Early Power-Fail warning output.Low when V CC falls below V LLOT (Low-Line Output Threshold).This output can be used to generate an NMI (Non-Maskable Interrupt)to provide an early warning of imminent power-failure.B35GND Ground reference for all signals.A34,6NC No Connect.A23PFI Power-Fail Comparator Input.When PFI is less than V PFT (Power-Fail Reset Threshold),the PFO goes low;otherwise,PFO remains high.B29NCNo Connect.Test input used at factory only.Leave floating.L M 3704/L M 3705 2Block Diagram3Ordering Information10136904*For other voltages between 2.2V and 5.0V,please contact National Semiconductor sales office.LM3704/LM3705Part Number Output Reset TimeoutPeriodPackagePackage Marking MSOPmicro SMD LM3704XCBP-308totem-pole 200ms x %%I4LM3704XCBPX-308totem-pole 200ms x%%I4LM3704XCMM-308totem-pole 200ms x R35B LM3704XCMMX-308totem-pole 200ms xR35B LM3705XCBP-308totem-pole 200ms x %%I5LM3705XCBPX-308totem-pole 200ms x%%I5LM3705XCMM-308totem-pole 200ms x R36B LM3705XCMMX-308totem-pole200msx R36B%%is the datecode and will vary with time.Table Of FunctionsPart Number Active Low Reset Active High ResetOutput(X =totem-pole)(Y =open-drain)Reset Timeout Period Manual Reset Power Fail ComparatorLow Line Output LM3704xX,Y *Customized x x x LM3705x XCustomizedxxx*=available upon request.Contact NationalL M 3704/L M 3705 4Absolute Maximum Ratings(Note 1)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (V CC )−0.3V to 6.0VAll Other Inputs −0.3V to V CC +0.3VESD Ratings (Note 2)Human Body Model Machine Model1.5kV 150VPower Dissipation (Note 3)Operating Ratings (Note 1)Temperature Range−40˚C ≤T J ≤85˚CLM3704/LM3705Series Electrical CharacteristicsLimits in the standard typeface are for T J =25˚C and limits in boldface type apply over full operating range.Unless otherwise specified:V CC =+2.2V to 5.5V.Symbol Parameter ConditionsMin TypMax UnitsPOWER SUPPLYV CC Operating Voltage Range:V CC LM3704 1.0 5.5V LM37051.25.5I CCV CC Supply CurrentAll inputs =V CC ;all outputs floating2850µARESET THRESHOLD V RSTReset ThresholdV CC falling−0.5−2V RST+0.5+2%V CC falling:T A =0˚C to 70˚C−1.5+1.5V RSTH Reset Threshold Hysteresis 0.0032•V RSTmV t RPReset Timeout PeriodReset Timeout Period =A Reset Timeout Period =B Reset Timeout Period =C ResetTimeoutPeriod=D1201401120 1.42820016002402802240mst RDV CC to Reset Delay V CC falling at 1mV/µs20µsRESET (LM3705)V OLRESETV CC >2.25V,I SINK =900µA 0.3VV CC >2.7V,I SINK =1.2mA 0.3V CC >4.5V,I SINK =3.2mA0.4V OHRESETV CC >1.2V,I SOURCE =50µA 0.8V CC VV CC >1.8V,I SOURCE =150µA 0.8V CC V CC >2.25V,I SOURCE =300µA 0.8V CC V CC >2.7V,I SOURCE =500µA 0.8V CC V CC >4.5V,I SOURCE =800µAV CC −1.5VI LKGOutput Leakage Current V RESET =5.5V1.0µA RESET (LM3704)V OLRESETV CC >1.0V,I SINK =50µA 0.3VV CC >1.2V,I SINK =100µA 0.3V CC >2.25V,I SINK =900µA 0.3V CC >2.7V,I SINK =1.2mA 0.3V CC >4.5V,I SINK =3.2mA0.4V OHRESETV CC >2.25V,I SOURCE =300µA 0.8V CC V CC >2.7V,I SOURCE =500µA 0.8V CC V CC >4.5V,I SOURCE =800µAV CC −1.5VLM3704/LM37055LM3704/LM3705Series Electrical Characteristics(Continued)Limits in the standard typeface are for T J =25˚C and limits in boldface type apply over full operating range.Unless otherwise specified:V CC =+2.2V to 5.5V.Symbol ParameterConditionsMin Typ Max Units PFI/MR V PFT PFI Input Threshold 1.2001.2251.250VV MRT MR Input Threshold MR,Low 0.8V MR,High2.0V PFTH /V MRTH PFI/MR Threshold Hysteresis PFI/MR falling:V CC =V RSTMAXto 5.5V0.0032•V RSTmV I PFI Input Current (PFI only)−7575nA R MR MR Pull-up Resistance 355675k Ωt MD MR to Reset Delay12µS t MR MR Pulse Width25µSPFO,LLO V OLPFO,LLO Output VoltageV CC >2.25V,I SINK =900µA 0.3VV CC >2.7V,I SINK =1.2mA 0.3V CC >4.5V,I SINK =3.2mA0.4V OHV CC >2.25V,I SOURCE =300µA 0.8V CC V CC >2.7V,I SOURCE =500µA 0.8V CC V CC >4.5V,I SOURCE =800µAV CC −1.5V LLO OUTPUT V LLOTLLO Output Threshold(V LLO −V RST ,V CC falling) 1.01•V RST1.02•V RST1.03•V RSTV V LLOTH Low-Line Comparator Hysteresis 0.0032•V RSTmVt CDLow-LineComparator DelayV CC falling at 1mV/µs20µsNote 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is intended to be functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance characteristics may degrade when the device is not operated under the listed conditions.Note 2:The Human Body model is a 100pF capacitor discharged through a 1.5k Ωresistor into each pin.The machine model is a 200pF capacitor discharged directly into each pin.Note 3:The maximum allowable power dissipation is a function of the maximum junction temperature,T J (MAX),the junction-to-ambient thermal resistance,θJ-A ,and the ambient temperature,T A .The maximum allowable power dissipation at any ambient temperture is calculated using:Where the value of θJ-A for the MSOP-10package is 195˚C/W in a typical PC board mounting and the micro SMD package is 220˚C/W.L M 3704/L M 3705 6Typical Performance CharacteristicsSupply Current vs Supply Voltage3.3V Supply Current vs Temperature1013691510136911Normalized Reset Threshold Voltage vs TemperatureReset Timeout Period vs V CC1013691210136932Reset Timeout Period vs TemperatureMax.Transient Duration vs Reset Comparator Overdrive(V CC =3.3V)1013691010136916LM3704/LM37057Typical Performance Characteristics(Continued)Low-Line Comparator Propagation Delay vs Temperature10136914L M 3704/L M 3705 8Circuit InformationReset OutputThe Reset input of a µP initializes the device into a known state.The LM3704/LM3705microprocessor supervisory cir-cuits assert a forced reset output to prevent code execution errors during power-up,power-down,and brownout condi-tions.RESET is guaranteed valid for V CC >1V.Once V CC ex-ceeds the reset threshold,an internal timer maintains the output for the reset timeout period.After this interval,reset goes high.The LM3704offers an active-low RESET;The LM3705offers an active-high RESET.Any time V CC drops below the reset threshold (such as during a brownout),the reset activates.When V CC again rises above the reset threshold,the internal timer starts.Reset holds until V CC exceeds the reset threshold for longer than the reset timeout period.After this time,reset releases.The Manual Reset input (MR)will initiate a forced reset also.See the Manual Reset Input section.Reset ThresholdThe LM3704/LM3705family is available with a reset voltage of 3.08V.Other reset thresholds in the 2.20V to 5.0V range,in steps of 10mV,are available;contact National Semicon-ductor for details.Manual Reset Input (MR)Many µP-based products require a manual reset capability,allowing the operator to initiate a reset.The MR input is fully debounced and provides an internal 56k Ωpull-up.When the MR input is pulled below V MRT (1.225V)for more than 25µs,reset is asserted after a typical delay of 12µs.Reset remains active as long as MR is held low,and releases after the reset timeout period expires after MR rises above V MRT .Use MR with digital logic to assert or to daisy chain supervisory circuits.It may be used as another low-line comparator by adding a buffer.Power-Fail Comparator (PFI/PFO)The PFI is compared to a 1.225V internal reference,V PFT .If PFI is less than V PFT ,the Power Fail Output PFO drops low.The power-fail comparator signals a falling power supply,and is driven typically by an external voltage divider that senses either the unregulated supply or another systemsupply voltage.The voltage divider generally is chosen so the voltage at PFI drops below V PFT several milliseconds before the main supply voltage drops below the reset thresh-old,providing advanced warning of a brownout.The voltage threshold is set by R 1and R 2and is calculated as follows:Note this comparator is completely separate from the rest of the circuitry,and may be employed for other functions as needed.Low-Line Output (LLO)The low-line output comparator is typically used to provide a non-maskable interrupt to a µP when V CC begins falling.LLO monitors V CC and goes low when V CC falls below V LLOT (typically 1.02•V RST )with hysteresis of 0.0032•V RST .Special Precautions for the micro SMD PackageAs with most integrated circuits,the LM3704and LM3705are sensitive to exposure from visible and infrared (IR)light radiation.Unlike a plastic encapsulated IC,the micro SMD package has very limited shielding from light,and some sensitivity to light reflected from the surface of the PC board or long wavelength IR entering the die from the side may be experienced.This light could have an unpredictable affect on the electrical performance of the IC.Care should be taken to shield the device from direct exposure to bright visible or IR light during operation.Micro SMD MountingThe micro SMD package requires specific mounting tech-niques which are detailed in National Semiconductor Appli-cation Note AN-1112.Referring to the section Surface Mount Technology (SMT)Assembly Considerations ,it should be noted that the pad style which must be used with the 9-pin package is the NSMD (non-solder mask defined)type.For best results during assembly,alignment ordinals on the PC board may be used to facilitate placement of the micro SMD device.LM3704/LM37059Timing Diagrams10Typical Application Circuits10136918FIGURE 4.Monitoring Two Critical Supplies10136919FIGURE 5.Monitoring Two Supplies plus Manual ResetLM3704/LM370511Typical Application Circuits(Continued)10136920FIGURE 6.Monitoring Dual Supplies plus External Fault Input10136921Note:MR input with its 1.225V nominal threshold,may monitor an additional supply voltage.An internal 56k Ωpull-up resistor is included on this input.FIGURE 7.Microprocessor Supervisor with Early Warning DetectorL M 3704/L M 3705 12LM3704/LM3705 Typical Application Circuits(Continued)10136924FIGURE8.LM3705Power-On Delay13Typical Application Circuits(Continued)10136923FIGURE 9.LM3705Power-On Delay with Overvoltage ProtectionL M 3704/L M 3705 14Typical Application Circuits(Continued)10136922FIGURE 10.Regulator/Switch with Long-Term Overvoltage Lockout Prevents Overdissipation in Linear Regulator10136931FIGURE 11.Switch DebouncerLM3704/LM370515Physical Dimensionsinches (millimeters)unless otherwise noted10Lead MSOP Package NS Package Number MUB10AL M 3704/L M 3705 16Physical Dimensionsinches (millimeters)unless otherwise noted (Continued)NOTES:UNLESS OTHERWISE SPECIFIED 1.EPOXY COATING2.63Sn/37Pb EUTECTIC BUMP3.RECOMMEND NON-SOLDER MASK DEFINED LANDING PAD.4.PIN 1IS ESTABLISHED BY LOWER LEFT CORNER WITH RESPECT TO TEXT ORIENTATION.REMAINING PINS ARE NUMBERED COUNTER CLOCKWISE.5.XXX IN DRAWING NUMBER REPRESENTS PACKAGE SIZE VARIATION WHERE X1IS PACKAGE WIDTH,X2IS PACKAGE LENGTH AND X3IS PACKAGE HEIGHT.6.NO JEDEC REGISTRATION AS OF AUG.1999.9bump micro SMD Package NS Package Number BPA09FFBThe dimensions of X1,X2and X3are given belowX1=1.412mm X2=1.412mm X3=0.850mmLIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or systems which,(a)are intended for surgical implant into the body,or (b)support or sustain life,and whose failure to perform when properly used in accordance with instructions for use provided in the labeling,can be reasonably expected to result in a significant injury to the user.2.A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system,or to affect its safety or effectiveness.National Semiconductor Corporation AmericasEmail:support@National Semiconductor EuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)6995086208English Tel:+44(0)8702402171Français Tel:+33(0)141918790National Semiconductor Asia Pacific Customer Response Group Tel:65-2544466Fax:65-2504466Email:ap.support@National Semiconductor Japan Ltd.Tel:81-3-5639-7560Fax:81-3-5639-7507LM3704/LM3705Microprocessor Supervisory Circuits with Power Fail Input,Low Line Output and Manual ResetNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。

172地壳构造与地壳应力文集(19) 2006年电源转换芯片TPS5430及其应用马爱虹 李海亮(中国地震局地壳应力研究所 北京 100085)摘要 TPS5430是TI(美国德州仪器公司)最新推出的一款DC/DC开关电源转换芯片。

其优越的性能使得它刚刚上市就受到广泛关注。

本文描述了该芯片的特征、参数、功能、结构,并结合实践情况对其在地震前兆观测仪器中的应用进行了介绍。

一、引 言地震前兆观测仪器是地震前兆观测的重要组成部分。

只有仪器稳定、工作可靠,才能为地震前兆分析工作提供连续的原始数据。

不断的挖掘和采用高性能的元器件替换相对性能低的、旧的元器件是改善仪器性能的一条途径。

TPS5430是TI公司最新推出的一款性能优越的DC/DC开关电源转换芯片。

我们对其进行了开发,并将其应用到了T J-2型体积式应变仪的数据采集系统。

二、TPS5430简介1 TPS5430特性TPS5430具有良好的特性,其各项性能及主要参数如下:高电流输出:3A(峰值4A); 宽电压输入范围:5 5~36V;高转换效率:最佳状况可达95%;宽电压输出范围:最低可以调整降到1 221V;内部补偿最小化了外部器件数量;固定500k H z转换速率;有过流保护及热关断功能;具有开关使能脚,关状态仅有17uA静止电流;内部软启动与其他同类型直流开关电源转换芯片相比,TPS5430的高转换效率特别值得关注。

图1为在12V输入电压、5V输出电压时TPS5430转换效率与输出电流的关系曲线图。

2 功能和结构(1)管脚说明:TPS5430采取8脚SO I C Po w er PAD TM封装,形式如图2。

(2)内部结构及功能:晶振(Osc illator)频率。

固定500k H z转换速率,使得在同样的输出波纹要求下产生更小的输出电感。

基准(Reference)电压。

通过缩放温度稳定能隙带电路的输出范围,基准电压系统产生精确的基准信号。

经测图1 TPS5430芯片的效率-电流关系曲线图图2 TPS5430封装1:BOOT 脚,FET 门驱动;2:空;3:空;4:VSENSE 脚,误差放大器转换节点,基准电压值;5:使能脚;6:地;7:电压输入脚;8:P H 脚,相位端,与外部LC 滤波器连接;9:Po w er PAD 脚,与过孔焊盘连接,用于散热试,在允许的温度范围内,1 221V 电压输出时能隙带和缩放电路保持平衡。