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单片机温度控制系统中英文资料外文翻译文献英文原文DescriptionThe at89s52 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM) and 128 bytes RAM. The device is manufactured using Atmel’s h igh density nonvolatile memory technology and is compatible with the industry standard MCS-51™ instruction set and pinout. The chip combines a versatile 8-bit CPU with Flash on a monolithic chip, the Atmelat89s52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.Features:• Compatible with MCS-51™ Products• 4K Bytes of In-System Reprogrammable Flash Memory• Endurance: 1,000 Write/Erase Cycles• Fully Static Operation: 0 Hz to 24 MHz• Three-Level Program Memory Lock• 128 x 8-Bit Internal RAM• 32 Programmable I/O Lines• Two 16-Bit Timer/Counters• Six Interrupt Sources• Programmable Serial Channel• Low Power Idle and Power Down ModesThe at89s52 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vectortwo-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the at89s52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.Pin Description:VCC Supply voltage.GND Ground.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When is are written to port 0 pins, the pins can be used as high impedance inputs.Port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.Port 1Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internalpull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of theat89s52 as listed below:Port 3 also receives some control signals for Flash programming andverification.RSTReset input. A high on this pin for two machine cycles while theoscillator is running resets the device.ALE/PROGAddress Latch Enable output pulse for latching the low byte of theaddress during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6 theoscillator frequency, and may be used for external timing or clockingpurposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFRlocation 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the at89s52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSENactivations are skipped during each access to external data memory.EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. Port pinalternate functions P3.0rxd (serial input port) P3.1txd (serial output port) P3.2^int0 (external interrupt0) P3.3^int1 (external interrupt1) P3.4t0 (timer0 external input) P3.5t1 (timer1 external input) P3.6^WR (external data memory write strobe) P3.7 ^rd (external data memory read strobe)EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage(VPP) during Flash programming, for parts that require 12-volt VPP.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Oscillator CharacteristicsXTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.Idle ModeIn idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.Status of External Pins During Idle and Power Down Modesmode Program memory ALE ^psen Port0 Port1Port2Port3idle internal 1 1 data data data Data Idle External 1 1 float Data data Data Power down Internal 0 0 Data Data Data Data Power down External 0 0 float data Data data Power Down ModeIn the power down mode the oscillator is stopped, and the instructionthat invokes power down is the last instruction executed. The on-chip RAMand Special Function Registers retain their values until the power down modeis terminated. The only exit from power down is a hardware reset. Resetredefines the SFRs but does not change the on-chip RAM. The reset shouldnot be activated before VCC is restored to its normal operating level andmust be held active long enough to allow the oscillator to restart andstabilize.Program Memory Lock BitsOn the chip are three lock bits which can be left unprogrammed (U) orcan be programmed (P) to obtain the additional features listed in the tablebelow:Lock Bit Protection ModesWhen lock bit 1 is programmed, the logic level at the EA pin issampled and latched during reset. If the device is powered up without a reset,the latch initializes to a random value, and holds that value until reset isactivated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Programming the Flash：The at89s52 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed.The programming interface accepts either a high-voltage (12-volt) or alow-voltage (VCC) program enable signal.The low voltage programming mode provides a convenient way to program the at89s52 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.The at89s52 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.Vpp=12v Vpp=5vTop-side mark at89s52xxxxyywwat89s52xxxx-5yywwsignature (030H)=1EH(031H)=51H(032H)=FFH (030H)=1EH (031H)=51H (032H)=05HThe at89s52 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode.Programming Algorithm:Before programming the at89s52, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the at89s52, take the following steps.1. Input the desired memory location on the address lines.2. Input the appropriate data byte on the data lines.3. Activate the correct combination of control signals.4. Raise EA/VPP to 12V for the high-voltage programming mode.5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.Data Polling: The at89s52 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.Chip Erase: T he entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.(030H) = 1EH indicates manufactured by Atmel(031H) = 51H indicates 89C51(032H) = FFH indicates 12V programming(032H) = 05H indicates 5V programmingProgramming InterfaceEvery code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.中文翻译描述at89s52是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大at89s52单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。

使用本科生毕业论文V外文翻译）译文名称：MCS -51系列单片机地功能和结构专业：自动化班次：学员：指导教员：评阅人：完成时间：2018年11月30日Structure and function of the MCS-51 seriesStructure and function of the MCS-51 series one-chip computer is a name of a piece of on e-chip computer series which In tel Compa ny produces. This compa ny in troduced 8 top-grade on e-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of on e-chip computer the chips have,such as 8051,8031, 8751, 80C51BH, 80C31BH,etc., their basic composition, basic performance and in structi on system are all the same. 8051 daily represe ntatives-51 serial on e-chip computers b5E2RGbCAPAn one-chip computer system is made up of several following parts: ( 1> One microprocessor of 8 (CPU>. ( 2> At slice data memory RAM (128B/256B>,it use not depositting not can reading /data that write, such as result not middle of operati on, final result and data wan ted to show, etc. ( 3> Procedure memory ROM/EPROM (4KB/8KB >, is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some on e-chip computers, such as 8031 , 8032, 80C ,etc.. (4> Four 8 run side by side I/O in terface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5> Two timer / counter, each timer / coun ter may set up and count in the way, used to count to the exter nal in cide nt, can set up into a timing way too, and can according to count or result of timing realize the control of the computer. ( 6> Five cut off cutting off the control system of the source . ( 7> One all duplexing serial I/O mouth of UART (uni versal asynchronous receiver/tra nsmitter (UART> >, is it realize on e-chip computer or on e-chip computer and serial com muni catio n of computer to use for. ( 8> Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity n eed outer. Allow oscillati on freque ncy as 12 megahertas now at most. Every the above-me nti oned part was joined through the in side data bus .Among them, CPU is a core of the one-chip computer, it is the control of the computer and comma nd cen tre, made up of such parts as arithmeticunit and使用controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing device temporarilies of 8, stori ng device 2 temporarily, 8's accumulatio n device ACC, register B and procedure stateregister PSW, etc. Pers on who accumulate ACC count by 2 in put ends en tered of check ing etc. temporarily as one operation often, come from person who store 1 operation is it is it make operation to go on to count temporarily , operation result and loopback ACC withanother one. In addition, ACC is often regarded as the transfer station of data tran smissi on on 8051 in side . The same as gen eral microprocessor, it is the busiest register. Help rememberi ng that agree ing with A expresses in the order. The con troller in cludes the procedure coun ter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of coun ter of 8 for two, amounts to 16. Itis a byte address coun ter of the procedure in fact, the content is the next IA that will carried out in PC. The content which cha nges it can cha nge the directi on that the procedure carries out . Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and freque ncy to fin ely tune the electric capacity, its freque ncy range is its12MHZ of 1.2MHZ. This pulse signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra accord ing to the beat play that is comma nded&nqFDPw There are ROM (procedure memory , can only read > and RAM in 8051 slices (data memory, can is it can write > two to read, they have each in depe ndent memory address space, dispose way to be the same with gen eral memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure and form con sta nt. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B,使用there is unit of 32 byteses that can be appo in ted as the job register, this and gen eral microprocessor is differe nt, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in additi on. Gen eral computer for first address space, ROM and RAM can arrange in differe nt space with in the range of this address at will, n amely the addresses of ROM and RAM, with distributing different address space ina formation. While visiting the memory, corresponding and only an address Memory unit, canROM, it can be RAM too, and by visiting the order similarly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in procedure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the an gle from users, 8051 memory address space is divided into three kin ds: (1> In the slice, arrange blocks of FFFFH , 0000H of locati on , in unison outside the slice (use 16 addresses>. (2> The data memory address space outside one of 64KB, the address is arran ged from 0000H 64KB FFFFH (with 16 addresses> too to the location. (3> Data memory address space of 256B (use 8 addresses>. Three above-mentioned memory space addresses overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice. DXDiTa9E3d8051 one-chip computer have four 8 walk abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported in depe nden tly. Each port in cludes a latch (n amely special fun cti on register >,使用one exports the driver and a introduction buffer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expa nd among the system of memory outside hav ing slice, four port these may serve as accurate two-way mouth of I/O in com mon use. Expand among the system of memory outside having slice, P2 mouth see high 8 address off= P0 mouth is a two-way bus, send the in troduct ion of 8 low addresses and data / export in timesharingr crpuDGiTThe circuit of 8051 on e-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to use ports correctly and rati on ally, and will in spire to desig ning the peripheral logical circuit of on e-chip computer to some exte nt. Load ability and in terface of port have certa in requireme nt, because output grade, P0 of mouth and P1 end output, P3 of mouth grade differe nt at structure, so,the load ability and in terface of its door dema nd to have nothing in com mon with each other. P0 mouth is differe nt from other mouths, its output grade draws the resistance supremly. When using it as the mouth in com mon use to use, output grade is it leak circuit to turn on, is it is it urge NMOS draw the resistance on taking to be outer with it while in putt ing to go out to fail. When being used as in troductio n, should write "1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in com mon use. Different from P0 mouth output of circuit its, draw load resistance link with power on in side have. In fact, the resista nce is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its Preside nt resista nce value cha nge approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate , can draw the pin to the high level fast。

1、外文原文（复印件）A: Fundamentals of Single-chip MicrocomputerTh e si ng le-ch i p mi cr oc om pu ter is t he c ul mi nat i on o f bo th t h e d ev el op me nt o f th e d ig it al com p ut er an d t he int e gr at ed ci rc ui ta r gu ab ly th e t ow m os t s i gn if ic ant i nv en ti on s o f t h e 20t h c en tu ry[1].Th es e to w typ e s of a rc hi te ctu r e ar e fo un d i n s in gl e-ch ip m i cr oc om pu te r. So m e em pl oy t he sp l it p ro gr am/d ata me mo ry o f th e H a rv ar d ar ch it ect u re, sh ow n i n -5A, ot he rs fo ll ow th e ph i lo so ph y, w i de ly a da pt ed fo r g en er al-p ur pos e c om pu te rs an d m i cr op ro ce ss or s, o f m a ki ng no lo gi c al di st in ct io n b e tw ee n p ro gr am a n d da t a m em ory a s i n th e Pr in cet o n ar ch it ec tu re,sh ow n in-5A.In g en er al te r ms a s in gl e-chi p m ic ro co mp ut er i sc h ar ac te ri zed b y the i nc or po ra tio n of al l t he uni t s o f a co mp ut er i n to a s in gl e dev i ce, as s ho wn in Fi g3-5A-3.-5A-1 A Harvard type-5A. A conventional Princeton computerFig3-5A-3. Principal features of a microcomputerRead only memory (ROM).R OM i s u su al ly f or th e p er ma ne nt, n o n-vo la ti le s tor a ge o f an a pp lic a ti on s pr og ra m .M an ym i cr oc om pu te rs an d mi cr oc on tr ol le r s a re in t en de d fo r h ig h-v ol ume a p pl ic at io ns a nd h en ce t he e co nom i ca l ma nu fa ct ure of t he d ev ic es r e qu ir es t ha t the co nt en ts o f the pr og ra m me mo ry b e co mm it te dp e rm an en tl y d ur in g th e m an uf ac tu re o f c hi ps . Cl ear l y, th is im pl ie sa ri g or ou s a pp roa c h t o R OM co de d e ve lo pm en t s in ce c ha ng es ca nn otb e m ad e af te r man u fa ct ur e .T hi s d e ve lo pm en t pr oce s s ma y in vo lv e e m ul at io n us in g a s op hi st ic at ed deve lo pm en t sy st em w i th a ha rd wa re e m ul at io n ca pa bil i ty a s we ll a s th e u se of po we rf ul so ft wa re t oo ls.So me m an uf act u re rs p ro vi de ad d it io na l RO M opt i on s byi n cl ud in g i n th ei r ra ng e de vi ce s wi th (or i nt en de d fo r us e wi th) u s er pr og ra mm ab le m em or y. Th e s im p le st of th es e i s us ua ll y d ev ice w h ic h ca n op er ate in a m ic ro pr oce s so r mo de b y usi n g so me o f th e i n pu t/ou tp ut li ne s as a n ad dr es s an d da ta b us f or acc e ss in g e xt er na l m e mo ry. T hi s t ype o f d ev ic e c an b e ha ve fu nc ti on al l y a s t he si ng le c h ip mi cr oc om pu te r fr om wh ic h i t i s de ri ve d a lb eit w it h r es tr ic ted I/O an d a mo di fie d e xt er na l ci rcu i t. T he u se o f t h es e RO Ml es sd e vi ce s is c om mo n e ve n in p ro du ct io n c ir cu it s wh er e t he v ol um e do es n o t ju st if y th e d e ve lo pm en t co sts of c us to m on-ch i p RO M[2];t he re c a n st il l b e a si g ni fi ca nt s a vi ng in I/O a nd ot he r c hi ps co mp ar ed t o a c on ve nt io nal mi cr op ro ce ss or b as ed c ir cu it. M o re e xa ctr e pl ac em en t fo r RO M d ev ic es c an b e o bt ai ne d in t he f o rm o f va ri an ts w i th 'pi gg y-ba ck'EP RO M(Er as ab le p ro gr am ma bl e ROM)s oc ke ts o rd e vi ce s w it h EP ROM i ns te ad o f R OM 。

动画专业外语文献关于动画专业的外语文献有很多，以下是一些例子：1. "The Art of Animation: The Evolution of the American Feature Film" by John Lasseter (Disney Editions, 2001)2. "The Art of Storyboard: The Complete Guide for Filmmakers and Storyboard Artists" by David B. Levy (Focal Press, 2014)3. "The Animator's Survival Kit: A Manual for Drawing and Thinking" by Richard Williams (Faber and Faber, 2001)4. "The Encyclopedia of Animated Cartoons" by John Cawelti (Facts on File, 1993)5. "The World Encyclopedia of Cartoons" by Gary Groth and Michael Vollmer (Facts on File, 1993)6. "The Animator's Handbook: A Complete Guide to Creating and Developing the Art of Animation" by Don L. Harris (Focal Press, 2003)7. "The Art of SpongeBob SquarePants: The Complete Collection" by The SpongeBob SquarePants Writers' Room (Chronicle Books, 2007)8. "The Art of the Simpsons: The Complete History of the Iconic Characters, Writers, Animators, and Producers Behind the Longest-Running Animated Series" by John Ortved (Hachettespeakersbureau, 2015)9. "The Animator's Eye: A Handbook for Visual Development" by John Lasseter (Focal Press, 1985)10. "The Illusion of Life: Disney Animation" by Ollie Johnston and Frank Thomas (Disney Editions, 1981)这些书籍涵盖了动画的历史、技术和理论等方面，对于深入了解动画专业非常有帮助。

Field-programmable gate array(现场可编程门阵列)1、History ——历史FPGA业界的可编程只读存储器（PROM）和可编程逻辑器件（PLD）萌芽。

可编程只读存储器（PROM）和可编程逻辑器件（PLD）都可以分批在工厂或在现场（现场可编程）编程，然而，可编程逻辑被硬线连接在逻辑门之间。

在80年代末期，为海军水面作战部提供经费的的史蒂夫·卡斯尔曼提出要开发将实现60万可再编程门计算机实验。

卡斯尔曼是成功的，并且与系统有关的专利是在1992年发行的。

1985年，大卫·W·佩奇和卢文R.彼得森获得专利，一些行业的基本概念和可编程逻辑阵列，门，逻辑块技术公司开始成立。

同年，Xilinx共同创始人，Ross Freeman和Bernard Vonderschmitt发明了第一个商业上可行的现场可编程门阵列——XC2064。

该XC2064可实现可编程门与其它门之间可编程互连，是一个新的技术和市场的开端。

XC2064有一个64位可配置逻辑块（CLB），有两个三输入查找表（LUT）。

20多年后，Ross Freeman 进入全国发明家名人堂，名人堂对他的发明赞誉不绝。

Xilinx继续受到挑战，并从1985年到90年代中期迅速增长，当竞争对手如雨后春笋般成立，削弱了显著的市场份额。

到1993年，Actel大约占市场的18％。

上世纪90年代是FPGA的爆炸性时期，无论是在复杂性和生产量。

在90年代初期，FPGA的电信和网络进行了初步应用。

到这个十年结束时，FPGA行业领袖们以他们的方式进入消费电子，汽车和工业应用。

1997年，一个在苏塞克斯大学工作的研究员阿德里安·汤普森，合并遗传算法技术和FPGA来创建一个声音识别装置，使得FPGA的名气可见一斑。

汤姆逊的算法配置10×10的细胞在Xilinx的FPGA芯片阵列，以两个音区分，利用数字芯片的模拟功能。

中英文对照外文翻译原文DESIGN OF TRAFFIC LIGHT BASED ON MCUBecause of the rapid development of our economy resulting in the car number of large and medium-sized cities surged and the urban traffic, is facing serious test, leading to the traffic problem increasingly serious, its basically are behaved as follows: traffic accident frequency, to the human life safety enormous threat, Traffic congestion, resulting in serious travel time increases, energy consumption increase; Air pollution and noise pollution degree of deepening, etc. Daily traffic jams become people commonplace and had to endure. In this context, in combination with the actual situation of urban road traffic, develop truly suitable for our own characteristics of intelligent signal control system has become the main task.PrefaceIn practical application at home and abroad, according to the actual traffic signal control application inspection, planar independent intersection signal control basic using set cycle, much time set cycle, half induction, whole sensor etc in several ways. The former two control mode is completely based on planar intersection always traffic flow data of statistical investigation, due to traffic flow the existence of variable sex and randomicity, the two methods have traffic efficiency is low, the scheme, the defects of aging and half inductive and all the inductive the two methods are in the former two ways based on increased vehicle detector and according to the information provided to adjust cycle is long and green letter of vehicle, it than random arrived adaptability bigger, can make vehicles in the parking cord before as few parking, achieve traffic flowing effectIn modern industrial production,current,voltage,temperature, pressure, and flow rate, velocity, and switch quantity are common mainly controlled parameter. For example: in metallurgical industry, chemical production, power engineering, the papermaking industry, machinery and food processing and so on many domains, people need to transport the orderlycontrol. By single chip microcomputer to control of traffic, not only has the convenient control, configuration simple and flexible wait for an advantage, but also can greatly improve the technical index by control quantity, thus greatly improve product quality and quantity. Therefore, the monolithic integrated circuit to the traffic light control problem is an industrial production we often encounter problems.In the course of industrial production, there are many industries have lots of traffic equipment, in the current system, most of the traffic control signal is accomplished by relays, but relays response time is long, sensitivity low, long-term after use, fault opportunity increases greatly, and adopts single-chip microcomputer control, the accuracy of far greater than relays, short response time, software reliability, not because working time reduced its performance sake, compared with, this solution has the high feasibility.About AT89C511.function characteristics description:AT89C51 is a low power consumption, high performance CMOS8 bit micro-controller, has the 8K in system programmable Flash memory. Use high-density Atmel company the beltpassword nonvolatile storage technology and manufacturing, and industrial 80S51 product instructions and pin fully compatible. Chip Flash allow program memory in system programmable, also suitable for conventional programmer. In a single chip, have dexterous 8 bits CPU and in system programmable Flash, make AT89C51 for many embedded control application system provides the high flexible, super efficient solution. AT89C51 has the following standard function: 8k bytes Flash, 256 bytes RAM, 32-bit I/O mouth line, the watchdog timer, two data pointer, three 16 timer/counter, a 6 vector level 2 interrupt structure, full-duplex serial port, piece inside crystals timely clock circuit. In addition, AT89C51 can drop to 0Hz static logic operation, support two software can choose power saving mode. Idle mode, the CPU to stop working, allowing the RAM, timer/counter, serial ports, interruption continue to work. Power lost protection mode, RAM content being saved, has been frozen, microcontroller all work stop, until the next interruption or hardware reset so far. As shown in figure 1 for the AT89C51 pins allotment.Figure 1 the AT89C51 pins allotment2.interrupt introductionAT89C51 has six interrupt sources: two external interruption, (and), three timer interrupt (timer 0, 1, 2) and a serial interrupts. Each interrupt source can be passed buy bits or remove IE the relevant special register interrupt allow control bit respectively make effective or invalid interrupt source. IE also includes an interrupt allow total control bit EA, it can be a ban all interrupts. IE. Six is not available. For AT89C51, IE. 5 bits are also not be used. User software should not give these bits write 1. They AT89 series for new product reserved. Timer 2 can be TF2 and the T2CON registers EXF2 or logical triggered. Program into an interrupt service, the sign bit can be improved by hardware qing 0. In fact, the interrupt service routine must determine whether TF2 or EXF2 activation disruption, the sign bit must also by software qing 0. Timer 0 and 1 mark a timer TF0 and TF1 has been presented in the cycle count overflow S5P2 074 bits. Their value until the next cycle was circuit capture down. However, the timer 2 marks a TF2 in count overflow of the cycle of S2P2 074 bits, in the same cycle was circuit capture down3.external clock driving characteristicsTable 14.leisure and power lost pattern external pins stateTable 2About 8255 chip1.8255 features:(1)A parallel input/output LSI chips, efficacy of I/O devices, but as CPU bus and peripheral interface.(2)It has 24 programmable Settings of I/O mouth, even three groups of 8 bits I/O mouth to mouth, PB mouth and PA PC mouth. They are divided into two groups 12 I/O mouth, A group including port A and C mouth (high four, PC4 ~ PC7), including group B and C port B mouth (low four, PC0 ~ PC3). A group can be set to give basic I/O mouth, flash control (STROBE) I/O flash controlled, two-way I/O3 modes, Group B can only set to basic I/O or flash controlled the I/O, and these two modes of operation mode entirely by controlling registers control word decision.2. 8255 pins efficacy:(1). RESET: RESET input lines, when the input outside at high levels, all internal registers (including control registers) were removed, all I/O ports are denoting input methods.(2). CS: chip choose a standard lamp line 1, when the input pins for low levels, namely/CS = 0, said chip is selected, allow 8255 and CPU for communications, / CS = 1, 8255 cannot with CPU do data transmission.(3). RD: read a standard lamp line 1, when the input pins for low levels, namely/RD = 0 and/CS = 0, allow 8255 through the data bus to the CPU to send data or state information, namely the CPU 8255 read from the information or data.(4). The WR: write a standard lights, when the input pins for low levels, namely/WR = 0 and/CS = 0, allows the CPU will data or control word write 8255.(5). D7: three states D0 ~ two-way data bus, 8255 and CPU data transmission channel, when the CPU execution input/output instruction, through its realization 8 bits of data read/write operation, control characters and status information transmitted through the data bus.(6). PA0 ~ PA7: port A input and output lines, A 8 bits of data output latches/buffers, an 8 bits of data input latches.(7). PB0 ~ PB7: port B input and output lines, a 8 bits of I/O latches, an 8 bits of input and output buffer.(8). PC0 ~ PC7: port C input and output lines, a 8 bits of data output latches/buffers, an 8 bits of data input buffer. Port C can through the way of working setting into two four ports, every 4 digit port contains A 4 digit latches, respectively with the port A and port B cooperate to use, can be used as control standard lights output or state standard lights input ports.(9). A0, A1: address selection line, used to select the PA 8255 mouth, PB mouth, PC mouth and controlling registers.When A0=0, A1= 0, PA mouth be chosen;When A0=0, A1 = 1, PB mouth be chosen;When A0=0, A1 = 1, PC mouth be chosen;When A0=1, A1= 1, control register is selected.Concerning seven section LED display introductionThrough light emitting diode chip appropriate link (including series and parallel) andappropriate optical structure. May constitute a luminous display light-emitting segments or shine points. By these luminous segments or shine point can be composed digital tube, symbols tube, m word pipe, tube, multilevel matrix display tube etc. Usually the digital tube, symbols tube, m word tube were called stroke display, but the stroke displays and matrix tube collectively referred to as character displays.1. The LED display classification(1) by word high marks: stroke monitors word high least 1mm (monolithic integrated type more digital tube word high in commonly 2 ~ 3mm). Other types of stroke display tiptop1.27 mm (0.5 inch) even up to hundreds of mm.(2) color-coded score red, orange, yellow, green and several kinds.(3) according to the structure points, reflecting cover type, a single point-elastic and monolithic integrated type.(4) from the luminous section electrode connection mode of points of anode and cathode two kinds.2. LED display parametersDue to the LED display is LED based, so its light, and the electrical characteristics and ultimate meaning of the parameters with most of the same light emitting diode. But because the LED monitor containing multiple light emitting diode, it must has the following specific parameters:(1) the luminous intensity ratioDue to the digital tube paragraphs in the same driving voltage, each are not identical, so positive current each different. The luminous intensity All segments of the luminous intensity values the ratio of the maximum and minimum values for the luminous intensity ratio. The ratio between 2.3 in 1.5 ~, the maximum cannot exceed 2.5.(2) pulse positive currentIF each segment of typical strokes displays for positive dc working current IF, then the pulse, positive current can be far outweigh.someotherwordpeopledontthinkoffirst. Pulse 390v smaller, pulse positive current can be bigger.Traffic signal control typeThe purpose of the traffic signal control are three: first,in time and space space intersection traffic in different directions,control traffic operation order; Second, make onplanar cross the road network on the people and objects of transport at the highest efficiency, Third, as the road users to provide necessary information, and help them to effectively use the traffic facilities. Road traffic signal control of basic types have many points method.According to the control geometry characteristic is divided into: single intersection control - point control, the traffic trunk lines of coordinated control - wire, traffic network coordination control surface controlling; -- According to the control principle differentiates: timing control, induced control and adaptive control.About watch-dog circuitBy single-chip computers.the micro computer system, because of single chip work often can be affected by external electromagnetic interference, causing program run fly while into dead circulation, the program's normal operation be interrupted by single chip microcomputer control system was unable to work, can cause the whole system of come to a standstill, happen unpredictable consequences, so out of microcontroller running status real-time.according consideration, they generate a specially used for monitoring microcontroller program running state of the chip, commonly known as "watchdog" (watchdog).MAX692 was slightly system monitoring circuit chip, have back-up battery switching, power lost discriminant functions monitoring, the watchdog. The encapsulation and pin instructions as figure2shows.Figure 2 MAX692 encapsulation and pinsWatch-dog circuit application, make SCM can in no condition to achieve continuous work, its working principle is: the watchdog chip and MCU an I/O pins are linked together, the I/O pins through program control it regularly to the watchdog of the pins on into high level (or the low level), this program statement is scattered on SCM other control statements,once among single-chip due to the interference makes application run into a fly after the procedures section into dead circulation state, write the watchdog pins program cannot be executed, this time, the watch-dog circuit will be without microcontroller sent signals, then at it and MCU reset pin connected pin reset signal give out a a, make SCM reposition occurs, namely the program from program memory splittext started, so we realized the MCU automatic reset.Infrared detection circuitThe infrared radiation photon in semiconductor materials stimutes the non-equilibrium carriers (electronic or holes), cause electrical properties change. Because carrier does not escape in vitro, so called within the photoelectric effect. Quantum photoelectric effect high sensitivity, response speed heat detectors much faster, is optional detectors. In order to achieve the best performance, generally need worked in low temperature. Photoelectric detector can be divided into:(1) optical type: also called photoconductive resistance. The incident photon stimulate the valence band uniform semiconductor electronic across forbidden band into the conduction band and left in valence band, cause cavitation increases, for electric conductance eigen light conductivity. From the band gaps of impurity level also can stimulate light into the conduction band or born carriers valence band, and for impurities light conductivity. The cutoff wavelength by impurity ionization energy (ie) decision. Quantum efficiencies below eigen optical and require lower working temperature.(2) photovoltaic type: mainly p - n knot of light born volts effect. Energy more than the width of infrared photonic band gaps in "area and its nearby of electrons cavitation. Existing "electric field make hole into p area, electronic into n area, two parts appear potentials. Deoxidization device have voltage or current signal. Compared with optical detectors, pv detector detect rate more than forty percent of figure limit, Don't require additional bias electric field and load resistance, no power consumption, having a high impedance. These characteristics of preparation and use of the focal plane array bring great benefits.(3) light emitting - Schottky potential barrier detector: metal and semiconductor contact, typically include PtSi/Si structure and form was Schott potential barrier, infrared photon through Si layer for PtSi absorption, electronic Fermi level, obtain energy leap over left cavitation potential barrier into the Si substrate, PtSi layer of electronic was collected,complete infrared detection. Make full use of Si integration technology, facilitate production, with lower cost and good uniformity wait for an advantage, but make it mass (1024 x 1024 even greater) focal plane array to make up for the defect of quantum low efficiency. Have strict low temperature requirements. With this kind of detector, both at home and abroad has already produced as qualitative good thermography. Pt Si/Si structure made of FPA is the earliest IRFPA.Timing counting and traffic calculationUsing MCS - 51 internal timer/counter for timing, cooperate software delay realizes the timer. This method hardware cost saving, cut allows the reader in timer/counter use, disruptions and programming get exercise and improve. Computation formula is as follows: TC = M - CType in, M for counter touch value, the value and the counter working way concerned.For a traffic intersection, it can in the shortest possible time to achieve maximum traffic, even reached the best performance, we call in unit of time to achieve the maximum flow multi-energy for cars.Use the equation: (traffic = traffic/time) to represent.译文:基于单片机的交通灯设计我国经济快速发展，汽车数量猛增，大中型城市的城市交通正面临着严峻的考验，交通问题日益严重，其主要表现如下：交通事故频发，对人类生命安全造成极大威胁；交通拥堵严重，导致出行时间增加，能源消耗加大；空气污染和噪声污染程度日益加深等。

Thermometer-to-Binary Decoders for FlashAnalog-to-Digital ConvertersAbstract:Decoders for low power, high-speed flash ADCs are investigated. The sensitivity to bubble errors of the ROM decoder with error correction, ones-counter, 4-level folded Wallace-tree, and multiplexer-based decoder are simulated. The ones-counter and multiplexer-based decoder,corresponding to the error insensitive and hardware efficient cases, are implemented in a 130 nm CMOS SOI technology. Measurements yield an ENOB of about 4.1 bit for both, and energy consumption of 80 pJ and 60 pJ, for the respective decoders. Hence we conclude that the MUX-based decoder seems to be a good choice with respect to area, efficiency, and speed.Key words: Thermometer-to-Binary flash ADCs ConvertersI. INTRODUCTIONApplications like ultra-wideband radio and the read channel in hard disk drives generally require high-speed analog-to-digital conversion with resolution four to six bits. These requirements are commonly satisfied by the flash analog-to-digital converter (ADC) architecture [1] that converts the analog input to a binary outputN parallel comparators, where N is the number of bits in with a single stage of 12the output, followed by a digital decoder. The comparators compare the input with the quantization levels from a set of reference voltages generated by a resistive ladder and produce a logical output depending on the outcome of the comparison. The output pattern from this stage corresponds to thermometer code and is subsequently translated to binary code by the digital decoder, i.e. the thermometer-to-binary decoder. For a low speed converter the input to the decoder is indeed a perfect thermometer code, but for high speed there may be some erroneous bits in the thermometer code, so called bubbles [2]. The bubbles are due to a number of sources [3], e.g., metastability, offset, crosstalk, and bandwidth limitations of the comparators, uncertainty in the effective sampling instant, etc. Hence the decoder must be able to perform well even in the presence of the bubble errors in a high-speed converter.Including requirements on power consumption and throughput, we see that the decoder must be paid significant consideration and trade-off in the design of a high-speed converter. In this work we focus on the design of decoders for low-power, high-speed six-bit ADCs. The work is a part of a larger project where the overall aim is to develop design techniques for implementation of high-performance analog circuits in CMOS silicon-on-insulator technology. We have investigated four types of thermometer-to-binarydecoders presented in Sec. II, through behavioral level simulations of the sensitivity to bubble errors presented in Sec. III, from which we have chosen two decoders that have been implemented in a 130 nm CMOS SOI technology. The measurement results are presented in Sec. IV and the conclusions are given in Sec. V.II. DECODERSFour different types of thermometer-to-binary decoders are presented. Two of them, the ROM and folded Wallace tree decoder,are only studied on behavioral level. The ones-counter decoder and the MUX-based decoder have also been implemented in two flash ADCs in a CMOS silicon-on-insulator technology. The corresponding results are thereby based on transistor level simulation results and measurements.A. ROMA common and straightforward approach to encode the thermometer code is to use a gray or binary-encoded ROM. The appropriate row m in the gray encoded ROM is selected by using a row decoder that has the output of comparator m and the inverse of comparator m + 1 as inputs. The output m of the row decoder, connected to memory row m, is high if the output of comparator m is high and the output of comparator m + 1 is low. The row decoder can be realized by, e.g., a number of 2-input NAND gates, where one input to each NAND gate is inverted. This type of row decoder selects multiple rows if a bubble error occurs, which introduces large errors in the output of the decoder [3], [4]. Considering single bubble errors only, these errors can be corrected by using 3-input NAND gates, as shown in Fig. 1. The 3-input NAND gates remove all bubble errors if they are separated by at least three bits in the thermometer scale. The main advantage of the ROM decoder approach isits regular structure that is straightforward to design. A disadvantage is that more bubble errors are introduced as the conversion speed increases and a more advanced bubble error correction scheme is required. As the complexity of the bubble error correction circuit increases, its propagation delay does in general also increase. The longer propagation delay reduces the maximum sampling rate of the overall decoder if not pipelining is applied. The increased complexity of the circuit consumes more chip area and will likely consume more power [5], [6].Figure 1Another bubble error suppression technique is the butterfly sorting technique presented in [7]. Applying this technique the bubbles are propagated upwards in the thermometer scale until the thermometer code is free from bubbles. Then the ROM decoder is used to encode the bubble-free thermometer code to binary code. In [7] the butterfly sorter only has eight levels. Bubbles further away from the transition level than eight positions cannot be removed. To guarantee that no bubbles will be present in the thermometer output code the depth of the butterfly sorter must be equal to the number of comparators, i.e.,12 N .B. Ones-CounterThe output of a thermometer-to-binary decoder is the number of ones on the input represented in, e.g., gray or binary code. Hence a circuit counting the number of ones in the thermometer code, i.e., a ones-counter, can be used as the decoder [8].The use of a ones-counter gives global bubble error suppression [3], [6], [8]. Another benefit of the approach is that a suitable ones-counter topology may be selected by trading speed for power. From this tradeoff the Wallace tree topology [9], illustrated in Fig. 2, is a good candidate as a decoder for high-speed converters [3], [6], [10].Figure 2In this work we use a tree of full adders (FAs) that reduce the 63 inputs to 10 outputs, as illustrated by Fig. 3. The different signal paths through the decoder are matched, i.e., each signal passes through the same number of full adders, where each input has approximately the same propagation delay to the output. The propagation delay of the signals through the decoder should thereby be approximately the same for all signals. The decoding of the 10 outputs to the binary value is done using MATLAB. The depth of the tree is thereby limited to six levels in the hardware implementation presented in the next section, which enables the ADC to operate at higher speed. In an improved design the complete decoding to a binary output can be accomplishedonchip by introducing pipelining in the decoder. Further optimization of the sizing of each FA can also improve the performance to some degree.C. Folded Wallace TreeFigure 3In a folded flash ADC, the idea is to reduce the amount of hardware by using the same comparator for different reference voltages [11]. This is the idea of the folded Wallace tree decoder shown in Fig. 4 [6]. The size of the Wallace tree and the delay depend on the number of bits that are added, i.e. the width of the base of the tree. The idea is to split the output of the comparators into different intervals. They are multiplexed to a reduced Wallace tree decoder, which is smaller compared with the full one [3]. A full adder may be realized from three 2:1 multiplexers with two multiplexers in the critical path.D. MUX-BasedThe multiplexer-based decoder consists entirely of multiplexers, as illustrated in Fig. 5, where N = 4 bit. It requires less hardware and has a shorter critical path than a ones-counter decoder [3], [5]. In addition it gives bubble error suppression, although the suppression is slightly lower than for a ones-counter decoder [5]. Another advantage of the multiplexer-based decoder is the more regular structure than, e.g., the ones-counter decoder. This is a major benefit in the layout of the circuit. Themultiplexers used in this work are based on transmission gates. An inverter is used as a buffer in each transmission gate multiplexer.Figure 4III. B EHA VIORAL LEVEL SIMULATIONThe effect of the chosen decoder topology on the ADC performance was evaluated by behavioral level simulations for the four different architectures. The timing difference ∆t between the clock signal and the input signal to each compar ator was modeled by a Gaussian distribution, according to ),0(~t N t σ∆。

附录A 外文翻译——AT89S52/AT89S51技术手册AT89S52译文主要性能与MCS-51单片机产品兼容8K字节在系统可编程Flash存储器1000次擦写周期全静态操作：0Hz～33Hz三级加密程序存储器32个可编程I/O口线三个16位定时器/计数器八个中断源全双工UART串行通道低功耗空闲和掉电模式掉电后中断可唤醒看门狗定时器双数据指针掉电标识符功能特性描述AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K在系统可编程Flash 存储器。

使用Atmel公司高密度非易失性存储器技术制造，与工业80C51产品指令和引脚完全兼容。

片上Flash 允许程序存储器在系统可编程，亦适于常规编程器。

在单芯片上，拥有灵巧的8位CPU和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。

AT89S52具有以下标准功能：8k字节Flash，256字节RAM，32位I/O口线，看门狗定时器，2个数据指针，三个16位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。

另外，AT89S52可降至0Hz静态逻辑操作，支持2种软件可选择节电模式。

空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。

掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。

引脚结构方框图VCC : 电源GND :地P0口：P0口是一个8位漏极开路的双向I/O口。

作为输出口，每位能驱动8个TTL逻辑电平。

对P0端口写“1”时，引脚用作高阻抗输入。

当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。

在这种模式下，P0具有内部上拉电阻。

在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。

程序校验时，需要外部上拉电阻。

P1口：P1 口是一个具有内部上拉电阻的8位双向I/O 口，p1 输出缓冲器能驱动4个TTL 逻辑电平。

我国的单片机起步虽然较晚，但经过几十年的发展，也取得了巨大的成就。

不论是工业生产还是社会生活的各个方面都离不开单片机的使用。

下面是搜素整理的单片机英文参考文献的分享，以供参考。

单片机英文参考文献一： [1]Hui Wang. Optimal Design of Single Chip Microcomputer Multi-machine Serial Communication based on Signal VerificationTechnology[J]. International Journal of Intelligent Information and Management Science,2020,9（1）。

[2]Philip J. Basford,Steven J. Johnston,Colin S. Perkins,Tony Garnock-Jones,Fung Po Tso,Dimitrios Pezaros,Robert D. Mullins,Eiko Yoneki,Jeremy Singer,Simon J. Cox. Performance analysis of single board computer clusters[J]. Future Generation ComputerSystems,2020,102. [3]. Computers; Reports from University of Southampton Describe Recent Advances in Computers （Performance Analysis of Single Board Computer Clusters）[J]. Computers, Networks & Communications,2020. [4]Yunyu Cao,Jinjin Dang,Chenxu Cao. Design of Automobile Digital Tire Pressure Detector[J]. Journal of Scientific Research and Reports,2019. [5]Sudad J. Ashaj,Ergun Er?elebi. Reduce Cost Smart Power Management System by Utilize Single Board Computer Artificial Neural Networks for Smart Systems[J]. International Journal of Computational Intelligence Systems,2019. [6]Hanhong Tan*, Yanfei Teng. Design of PWM Lighting brightness Control based on LAN QIAO Cup single Chip Microcomputer[J]. International Journal of Computational and Engineering,2019,4（3）。

3d动画制作中英文对照外文翻译文献预览说明:预览图片所展示的格式为文档的源格式展示,下载源文件没有水印,内容可编辑和复制中英文对照外文翻译文献(文档含英文原文和中文翻译)Spin: A 3D Interface for Cooperative WorkAbstract: in this paper, we present a three-dimensional user interface for synchronous co-operative work, Spin, which has been designed for multi-user synchronous real-time applications to be used in, for example, meetings and learning situations. Spin is based on a new metaphor of virtual workspace. We have designed an interface, for an office environment, which recreates the three-dimensional elements needed during a meeting and increases the user's scope of interaction. In order to accomplish these objectives, animation and three-dimensional interaction in real time are used to enhance the feeling of collaboration within the three-dimensional workspace. Spin is designed to maintain a maximum amount of information visible. The workspace is created using artificial geometry - as opposed to true three-dimensional geometry - and spatial distortion, a technique that allows all documents and information to be displayed simultaneously while centering the user's focus of attention. Users interact with each other via their respective clones, which are three-dimensional representations displayed in each user's interface, and are animated with user action on shared documents. An appropriate object manipulation system (direct manipulation, 3D devices and specific interaction metaphors) is used to point out and manipulate 3D documents.Keywords: Synchronous CSCW; CVE; Avatar; Clone; Three-dimensional interface; 3D interactionIntroductionTechnological progress has given us access to fields that previously only existed in our imaginations. Progress made in computers and in communication networks has benefited computer-supported cooperative work (CSCW), an area where many technical and human obstacles need to be overcome before it can be considered as a valid tool. We need to bear in mind the difficulties inherent in cooperative work and in the user's ability to perceive a third dimension.The Shortcomings of Two- Dimensional InterfacesCurrent WIMP (windows icon mouse pointer) office interfaces have considerable ergonomic limitations [1].(a) Two-dimensional space does not display large amounts of data adequately. When it comes to displaying massive amounts of data, 2D displays have shortcomings such as window overlap and the need for iconic representation of information [2]. Moreover, the simultaneous display of too many windows (the key symptom of Windowitis) can be stressful for users [3].(b) WIMP applications are indistinguishable from one another; leading to confusion. Window dis- play systems, be they XII or Windows, do not make the distinction between applications, con- sequently, information is displayed in identical windows regardless of the user's task.(c) 2D applications cannot provide realistic rep- resentation. Until recently, network technology only allowed for asynchronous sessions (electronic mail for example); and because the hardware being used was not powerful enough, interfaces could only use 2D representations of the workspace.Metaphors in this type of environment do not resemble the real space; consequently, it is difficult for the user to move around within a simulated 3D space.(d) 2D applications provide poor graphical user representations. As windows are indistinguish- able and there is no graphical relation between windows, it is difficult to create a visual link between users or between a user and an object when the user's behavior is been displayed [4].(e) 2D applications are not sufficiently immersive, because 2D graphical interaction is not intuitive (proprioception is not exploited) users have difficulties getting and remaining involved in the task at hand.Interfaces: New ScopeSpin is a new interface concept, based on real-time computer animation. Widespread use of 3D graphic cards for personal computers has made real-time animation possible on low-cost computers. The introduction of a new dimension (depth) changes the user's role within the interface, the use of animation is seamless and therefore lightens the user's cognitive load. With appropriate input devices, the user now has new ways of navigating in, interacting with and organizing his workspace. Since 1995, IBM has been working on RealPlaces [5], a 3D interface project. It was developed to study the convergence between business applications and virtual reality. The user environment in RealPlaces is divided into two separate spaces (Fig, 1): ? a 'world view', a 3D model which stores and organizes documents through easy object interaction;a 'work plane', a 2D view of objects with detailed interaction, (what is used in most 2D interfaces).RealPlaces allows for 3D organization of a large number ofobjects. The user can navigatethrough them, and work on a document, which can be viewed and edited in a 2D application that is displayed in the foreground of the 'world'. It solves the problem of 2D documents in a 3D world, although there is still some overlapping of objects. RealPtaces does solve some of the problems common to 2D interfaces but it is not seamless. While it introduces two different dimensions to show documents, the user still has difficulty establishing links between these two dimensions in cases where multi-user activity is being displayed. In our interface, we try to correct the shortcomings of 2D interfaces as IBM did in RealPlaces, and we go a step further, we put forward a solution for problems raised in multi-user cooperation, Spin integrates users into a virtual working place in a manner that imitates reality making cooperation through the use of 3D animation possible. Complex tasks and related data can be represented seamlessly, allowing for a more immersive experience. In this paper we discuss, in the first part, the various concepts inherent in simultaneous distant cooperative work (synchronous CSCW), representation and interaction within a 3D interface. In the second part, we describe our own interface model and how the concepts behind it were developed. We conclude with a description of the various current and impending developments directly related to the prototype and to its assessment.ConceptsWhen designing a 3D interface, several fields need to be taken into consideration. We have already mentioned real-time computer animation and computer-supported cooperative work, which are the backbone of our project. There are also certain fields of the human sciences that have directty contributed to thedevelopment of Spin. Ergon- omics [6], psychology [7] and sociology [8] have broadened our knowIedge of the way in which the user behaves within the interface, both as an individual and as a member of a group.Synchronous Cooperative WorkThe interface must support synchronous cooper- ative work. By this we mean that it must support applications where the users have to communicate in order to make decisions, exchange views or find solutions, as would be the case with tele- conferencing or learning situations. The sense of co-presence is crucial, the user needs to have an immediate feeling that he is with other people; experiments such as Hydra Units [9] and MAJIC [10] have allowed us to isolate some of the aspects that are essential to multimedia interactive meetings.Eye contact." a participant should be able to see that he is being looked at, and should be able to look at someone else. ? Gaze awareness: the user must be able to estab- fish a participant's visual focus of attention. ? Facial expressions: these provide information concerning the participants' reactions, their acquiescence, their annoyance and so on. ? GesCures. ptay an important role in pointing and in 3D interfaces which use a determined set of gestures as commands, and are also used as a means of expressing emotion.Group ActivitySpeech is far from being the sole means of expression during verbal interaction [1 1]. Gestures (voluntary or involuntary) and facial expressions contribute as much information as speech. More- over, collaborative work entails the need to identify other people's points of view as well as their actions [1 2,1 3]. This requires defining the metaphors which witl enable users involvedin collaborative work to understand what other users are doing and to interact withthem. Researchers I1 4] have defined various communication criteria for representing a user in a virtual environment. In DIVE (Distributed Interactive Virtual Environment, see Fig. 2), Benford and Fahl6n lay down rules for each characteristic and apply them to their own system [1 5]. lhey point out the advantages of using a clone (a realistic synthetic 3D representation of a human) to represent the user. With a clone, eye contact (it is possible to guide the eye movements of a clone) as well as gestures and facial expressions can be controlled; this is more difficult to accomplish with video images. tn addition to having a clone, every user must have a telepointer, which is used to designate obiects that can be seen on other users' displays.Task-Oriented InteractionUsers attending a meeting must be abte to work on one or several shared documents, it is therefore preferable to place them in a central position in the user's field of vision, this increases her feeling of participation in a collaborative task. This concept, which consists of positioning the documents so as to focus user attention, was developed in the Xerox Rooms project [1 6]; the underlying principle is to prevent windows from overlapping or becoming too numerous. This is done by classifying them according to specific tasks and placing them in virtual offices so that a singIe window is displayed at any one (given) time. The user needs to have an instance of the interface which is adapted to his role and the way he apprehends things, tn a cooperative work context, the user is physically represented in the interface and has a position relative to the other members of the group.The Conference Table Metaphor NavigationVisually displaying the separation of tasks seems logical - an open and continuous space is not suitable. The concept of 'room', in the visual and in the semantic sense, is frequently encountered in the literature. It is defined as a closed space that has been assigned a single task.A 3D representation of this 'room' is ideal because the user finds himself in a situation that he is familiar with, and the resulting interfaces are friendlier and more intuitive.Perception and Support of Shared AwarenessSome tasks entail focusing attention on a specific issue (when editing a text document) while others call for a more global view of the activity (during a discussion you need an overview of documents and actors). Over a given period, our attention shifts back and forth between these two types of activities [17]. CSCW requires each user to know what is being done, what is being changed, where and by whom. Consequently, the interface has to be able to support shared awareness. Ideally, the user would be able to see everything going on in the room at all times (an everything visible situation). Nonetheless, there are limits to the amount of information that can be simultaneously displayed on a screen. Improvements can be made by drawing on and adopting certain aspects of human perception. Namely, a field of vision with a central zone where images are extremely clear, and a peripheral vision zone, where objects are not well defined, but where movement and other types of change can be perceived.Interactive Computer AnimationInteractive computer animation allows for two things: first, the amount of information displayed can be increased, andsecond, only a small amount of this information can be made legible [18,19]. The remainder of the information continues to be displayed but is less legible (the user only has a rough view of the contents). The use of specific 3D algorithms and interactive animation to display each object enables the user visually to analyse the data quickly and correctly. The interface needs to be seamless. We want to avoid abstract breaks in the continuity of the scene, which would increase the user's cognitive load.We define navigation as changes in the user's point of view. With traditional virtual reality applica- tions, navigation also includes movement in the 3D world. Interaction, on the other hand, refers to how the user acts in the scene: the user manipulates objects without changing his overall point of view of the scene. Navigation and interaction are intrinsically linked; in order to interact with the interface the user has to be able to move within the interface. Unfortunately, the existence of a third dimension creates new problems with positioning and with user orientation; these need to be dealt with in order to avoid disorienting the user [20].Our ModelIn this section, we describe our interface model by expounding the aforementioned concepts, by defining spatial organization, and finally, by explaining how the user works and collaborates with others through the interface.Spatial OrganizationThe WorkspaceWhile certain aspects of our model are related to virtual reality, we have decided that since our model iS aimed at an office environment, the use of cumbersome helmets or gloves is not desirable. Our model's working environment is non-immersive.Frequently, immersive virtual reality environments tack precision and hinder perception: what humans need to perceive to believe in virtual worlds is out of reach of present simulation systems [26]. We try to eliminate many of the gestures linked to natural constraints, (turning pages in a book, for example) and which are not necessary during a meeting. Our workspace has been designed to resolve navigation problems by reducing the number of superfluous gestures which slow down the user. In a maI-life situation, for example, people sitting around a table could not easily read the same document at the same time. To create a simple and convenient workspace, situations are analysed and information which is not indispensable is discarded [27]. We often use interactive computer animation, but we do not abruptly suppress objects and create new icons; consequently, the user no longer has to strive to establish a mental link between two different representations of the same object. Because visual recognition decreases cognitive load, objects are seamlessly animated. We use animation to illustrate all changes in the working environment, i.e. the arrival of a new participant, the telepointer is always animated. There are two basic objects in our workspace: the actors and the artefacts. The actors are representations of the remote users or of artificial assistants. The artefacts are the applications and the interaction tools.The Conference tableThe metaphor used by the interface is the con- ference table. It corresponds to a single activity (our task-oriented interface solves the (b) shortcoming of the 2D interface, see Introduction). This activity is divided spatially and semantically into two parts. The first is asimulated panoramic view on which actors and sharedapplications are displayed. Second, within this view there is a workspace located near the center of the simulated panoramic screen, where the user can easily manipulate a specific document. The actors and the shared applications (2D and 3D) are placed side by side around the table (Fig. 4), and in the interest of comfort, there is one document or actor per 'wail'. As many applications as desired may be placed in a semi-circle so that all of the applications remain visible. The user can adjust the screen so that the focus of her attention is in the center; this type of motion resembles head- turning. The workspace is seamless and intuitive,Fig, 4. Objects placed around our virtual table.And simulates a real meeting where there are several people seated around a table. Participants joining the meeting and additional applications are on an equal footing with those already present. Our metaphor solves the (c) shortcoming of the 2D interface (see Introduction),DistortionIf the number of objects around the table increases, they become too thin to be useful. To resolve this problem we have defined a focus-of-attention zone located in the center of the screen. Documents on either side of this zone are distorted (Fig.5). Distortion is symmetrical in relation to the coordinate frame x=0. Each object is uniformly scaled with the following formula: x'=l-(1-x) '~, O<x<l< bdsfid="116" p=""></x<l<>Where is the deformation factor. When a= 1 the scene is not distorted. When all, points are drawn closer to the edge; this results in centrally positioned objects being stretched out, while those in the periphery are squeezed towards the edge. This distortion is similar to a fish-eye with only one dimension [28].By placing the main document in the centre of the screen and continuing to display all the other documents, our model simulates a human field of vision (with a central zone and a peripheral zone). By reducing the space taken up by less important objects, an 'everything perceivable' situation is obtained and, although objects on the periphery are neither legible nor clear, they are visible and all the information is available on the screen. The number of actors and documents that it is possible to place around the table depends, for the most part, on screen resolution. Our project is designed for small meetings with four people for example (three clones) and a few documents (three for example). Under these conditions, if participants are using 17-inch, 800 pixels screens all six objects are visible, and the system works.Everything VisibleWith this type of distortion, the important applications remain entirely legible, while all others are still part of the environment. When the simulated panoramic screen is reoriented, what disappears on one side immediately reappears on the other. This allows the user to have all applications visible in the interface. In CSCW it is crucial that each and every actor and artefact taking part in a task are displayed on the screen (it solves the (a) shortcoming of 2D interface, see Introduction),A Focus-of-Attention AreaWhen the workspace is distorted in this fashion, the user intuitively places the application on which she is working in the center, in the focus-of- attention area. Clone head movements correspond to changes of the participants' focus of attention area. So, each participant sees theother participants' clones and is able to perceive their headmovements. It gives users the impression of establishing eye contact and reinforces gaze awareness without the use of special devices. When a participant places a private document (one that is only visible on her own interface) in her focus in order to read it or modify it, her clone appears to be looking at the conference table.In front of the simulated panoramic screen is the workspace where the user can place (and enlarge) the applications (2D or 3D) she is working on, she can edit or manipulate them. Navigation is therefore limited to rotating the screen and zooming in on the applications in the focus-of-attention zone.ConclusionIn the future, research needs to be oriented towards clone animation, and the amount of information clones can convey about participant activity. The aim being to increase user collaboration and strengthen the feeling of shared presence. New tools that enable participants to adopt another participant's point of view or to work on another participant's document, need to be introduced. Tools should allow for direct interaction with documents and users. We will continue to develop visual metaphors that will provide more information about shared documents, who is manipulating what, and who has the right to use which documents, etc. In order to make Spin more flexible, it should integrate standards such as VRML 97, MPEG 4, and CORBA. And finally, Spin needs to be extended so that it can be used with bigger groups and more specifically in learning situations.旋转：3D界面的协同工作摘要：本文提出了一种三维用户界面的同步协同工作—旋转，它是为多用户同步实时应用程而设计，可用于例如会议和学习情况。

外文翻译英文原文：STM32 MicrocontrollerIntroductionRequirements based STM32 family is designed for high-performance, low-cost, low-power embedded applications designed specifically for ARM Cortex-M3 core. According to the performance into two different series: STM32F103 "Enhanced" series and STM32F101 "Basic" series. Enhanced Series clock frequency of 72MHz, the highest performance of similar products product; basic clock frequency of 36MHz, 16-bit product prices get more than 16 products significantly enhance the performance and is 16 product users the best choice. Both series have built-in 32K to 128K of flash memory, the difference is the maximum capacity of the SRAM and peripheral combinations. At 72MHz, executing from Flash, STM32 power consumption 36mA, are 32 products on the market's lowest power, the equivalent of 0.5mA/MHz.STM32F103 Performance Characteristics1)Kernel. ARM32 bit CPU, the maximum operating frequency of 72MHz,1.25DMIPS/MHz. Single-cycle multiply and hardware divide.2)Memory. Integrated on-chip 32-512KB of Flash memory. 6-64KB SRAM memory.3)Clock, reset, and power management. 2.0-3.6V power supply and I / O interface, the drive voltage. POR, PDR and programmable voltage detector. 4-16MHz crystal. Embedded factory tuned 8MHz RC oscillator circuit. 40 kHz internal RC oscillator circuit. CPU clock for the PLL. With calibration for the RTC 32kHz crystal.4)Low power consumption. Three kinds of low-power mode. Sleep, stop, standby mode. For RTC and backup registers supply VBAT.5)Debug mode. Serial debugging and JTAG interface.6)Direct data storage. 12-channel direct data storage controller. Supported peripherals: timers, ADC, DAC, SPI, IIC and USART.7)Up to a maximum of 112 fast I / O ports. Depending on the model, there are 26,37,51,80, and 112 I / O ports, all ports can be mapped to 16 external interruptvectors. In addition to the analog input, all of them can accept the input of 5V or less.8)Up to a maximum of 11 timers. Four 16-bit timers, each with 4 IC / OC / PWM or pulse counter. 2 16 6-channel advanced control timer: up to 6 channels can be used for PWM output. 2 watchdog timer. Systick timer: 24 down counter. Two 16-bit basic timer for driving DAC.9)Up to a maximum of 13 communication interfaces. 2 IIC interface. 5 USART interfaces. 3 SPI interface, two and IIS reuse. CAN interface. USB 2.0 full-speed interface. SDIO interface.System Function1)Integration of embedded Flash and SRAM memory ARM Cortex-M3 core. And 8/16 equipment compared, ARM Cortex-M3 32-bit RISC processor provides a higher code efficiency. STM32F103xx microcontrollers with an embedded ARM core, so it can be compatible with all ARM tools and software.2)Embedded Flash memory and RAM memory. Built up to 512KB embedded Flash, can be used to store programs and data. Up to 64KB of embedded SRAM clock speed of the CPU can read and write.3)Variable static memory. Variable static memory with 4 chip selects, supports four modes: Flash, RAM, PSRAM, NOR and NAND. After three FSMC interrupt lines connected to the OR after the nested vector interrupt controller. No read / write FIFO, except PCCARD, the code is executed from external memory is not supported Boot, the target frequency is equal to SYSCLK / 2, so the time when the system clock is 72MHz, 36MHz conducted in accordance with external access.4)Nested Vectored Interrupt Controller. Can handle 43 maskable interrupt channels, providing 16 interrupt priority levels. Tightly coupled nested vectored interrupt controller to achieve lower latency interrupt handling directly passed to the kernel interrupt vector table entry address, tightly coupled nested vectored interrupt controller kernel interface, allowing early treatment interruption, the latter to be more high-priority interrupt processing, support tail chain, auto-save processor state terrupts automatically restored on interrupt exit, no instructions intervention.5)External interrupt / event controller. External interrupt / event controller consists for 19 to generate interrupt / event requests edge detector lines. Each line can be individually configured to select the trigger event, it can be individually masked. There is a pending interrupt request registers to maintain state. When an external line appear longer than the internal APB2 clock-cycle pulse, the external interrupt / eventcontroller is able to detect. Up to 112 GPIO connected to the 16 external interrupt lines.6)Clocks and startup. At boot time or to the system clock selection, but the reset when the internal 8MHz crystal oscillator is selected as the CPU clock. Can choose a 4-16MHz external clock, and will be monitored to determine the success. During this time, the interrupt controller is disabled and the software management is subsequently disabled. Also, if there is a need, PLL clock interrupt management fully available. Comparator can be used more pre-configuration of the AHB frequency, including high-speed and low-speed APB APB, APB highest frequency of high-speed 72MHz, low-speed APB highest frequency of 36MHz.Architectural AdvantagesIn addition to the new features Enhanced peripheral interfaces, STM32 series also interconnect with other STM32 microcontrollers offer the same standard interface, such sharing of peripherals to enhance the entire product family, application flexibility, so that developers can a plurality of design reuse the same software. New STM32 standard peripherals include 10 timers, two 12-bit ADC, two 12-bit DAC, two I2C interfaces, five USART interfaces and three SPI ports. There are 12 new products peripherals direct data storage channel, there is a CRC calculation unit, like other STM32 microcontrollers, the supports 96 unique identifier.New series also has followed the STM32 microcontroller family of products low voltage and energy saving are two advantages. 2.0V to 3.6V operating voltage range compatible with the mainstream of battery technologies such as lithium batteries and nickel-metal hydride batteries, the package also features a battery operation mode dedicated pin Vbat. 72MHz frequency to execute code from flash consumes only 27mA current. There are four low-power mode, the current consumption can be reduced to two microamps. Quick Start from low power mode to save energy too; starting circuit using STM32 internally generated 8MHz signal, the microcontroller from stop mode when you wake up with less than 6 microseconds.中文翻译：单片机STM321 STM32的介绍STM32系列基于专为要求高性能、低成本、低功耗的嵌入式应用专门设计的ARM Cortex-M3内核。

外文翻译英文原文：STM32 MicrocontrollerIntroductionRequirements based STM32 family is designed for high-performance, low-cost, low-power embedded applications designed specifically for ARM Cortex-M3 core. According to the performance into two different series: STM32F103 "Enhanced" series and STM32F101 "Basic" series. Enhanced Series clock frequency of 72MHz, the highest performance of similar products product; basic clock frequency of 36MHz, 16-bit product prices get more than 16 products significantly enhance the performance and is 16 product users the best choice. Both series have built-in 32K to 128K of flash memory, the difference is the maximum capacity of the SRAM and peripheral combinations. At 72MHz, executing from Flash, STM32 power consumption 36mA, are 32 products on the market's lowest power, the equivalent of 0.5mA/MHz.STM32F103 Performance Characteristics1)Kernel. ARM32 bit CPU, the maximum operating frequency of 72MHz,1.25DMIPS/MHz. Single-cycle multiply and hardware divide.2)Memory. Integrated on-chip 32-512KB of Flash memory. 6-64KB SRAM memory.3)Clock, reset, and power management. 2.0-3.6V power supply and I / O interface, the drive voltage. POR, PDR and programmable voltage detector. 4-16MHz crystal. Embedded factory tuned 8MHz RC oscillator circuit. 40 kHz internal RC oscillator circuit. CPU clock for the PLL. With calibration for the RTC 32kHz crystal.4)Low power consumption. Three kinds of low-power mode. Sleep, stop, standby mode. For RTC and backup registers supply VBAT.5)Debug mode. Serial debugging and JTAG interface.6)Direct data storage. 12-channel direct data storage controller. Supported peripherals: timers, ADC, DAC, SPI, IIC and USART.7)Up to a maximum of 112 fast I / O ports. Depending on the model, there are 26,37,51,80, and 112 I / O ports, all ports can be mapped to 16 external interruptvectors. In addition to the analog input, all of them can accept the input of 5V or less.8)Up to a maximum of 11 timers. Four 16-bit timers, each with 4 IC / OC / PWM or pulse counter. 2 16 6-channel advanced control timer: up to 6 channels can be used for PWM output. 2 watchdog timer. Systick timer: 24 down counter. Two 16-bit basic timer for driving DAC.9)Up to a maximum of 13 communication interfaces. 2 IIC interface. 5 USART interfaces. 3 SPI interface, two and IIS reuse. CAN interface. USB 2.0 full-speed interface. SDIO interface.System Function1)Integration of embedded Flash and SRAM memory ARM Cortex-M3 core. And 8/16 equipment compared, ARM Cortex-M3 32-bit RISC processor provides a higher code efficiency. STM32F103xx microcontrollers with an embedded ARM core, so it can be compatible with all ARM tools and software.2)Embedded Flash memory and RAM memory. Built up to 512KB embedded Flash, can be used to store programs and data. Up to 64KB of embedded SRAM clock speed of the CPU can read and write.3)Variable static memory. Variable static memory with 4 chip selects, supports four modes: Flash, RAM, PSRAM, NOR and NAND. After three FSMC interrupt lines connected to the OR after the nested vector interrupt controller. No read / write FIFO, except PCCARD, the code is executed from external memory is not supported Boot, the target frequency is equal to SYSCLK / 2, so the time when the system clock is 72MHz, 36MHz conducted in accordance with external access.4)Nested Vectored Interrupt Controller. Can handle 43 maskable interrupt channels, providing 16 interrupt priority levels. Tightly coupled nested vectored interrupt controller to achieve lower latency interrupt handling directly passed to the kernel interrupt vector table entry address, tightly coupled nested vectored interrupt controller kernel interface, allowing early treatment interruption, the latter to be more high-priority interrupt processing, support tail chain, auto-save processor state terrupts automatically restored on interrupt exit, no instructions intervention.5)External interrupt / event controller. External interrupt / event controller consists for 19 to generate interrupt / event requests edge detector lines. Each line can be individually configured to select the trigger event, it can be individually masked. There is a pending interrupt request registers to maintain state. When an external line appear longer than the internal APB2 clock-cycle pulse, the external interrupt / eventcontroller is able to detect. Up to 112 GPIO connected to the 16 external interrupt lines.6)Clocks and startup. At boot time or to the system clock selection, but the reset when the internal 8MHz crystal oscillator is selected as the CPU clock. Can choose a 4-16MHz external clock, and will be monitored to determine the success. During this time, the interrupt controller is disabled and the software management is subsequently disabled. Also, if there is a need, PLL clock interrupt management fully available. Comparator can be used more pre-configuration of the AHB frequency, including high-speed and low-speed APB APB, APB highest frequency of high-speed 72MHz, low-speed APB highest frequency of 36MHz.Architectural AdvantagesIn addition to the new features Enhanced peripheral interfaces, STM32 series also interconnect with other STM32 microcontrollers offer the same standard interface, such sharing of peripherals to enhance the entire product family, application flexibility, so that developers can a plurality of design reuse the same software. New STM32 standard peripherals include 10 timers, two 12-bit ADC, two 12-bit DAC, two I2C interfaces, five USART interfaces and three SPI ports. There are 12 new products peripherals direct data storage channel, there is a CRC calculation unit, like other STM32 microcontrollers, the supports 96 unique identifier.New series also has followed the STM32 microcontroller family of products low voltage and energy saving are two advantages. 2.0V to 3.6V operating voltage range compatible with the mainstream of battery technologies such as lithium batteries and nickel-metal hydride batteries, the package also features a battery operation mode dedicated pin Vbat. 72MHz frequency to execute code from flash consumes only 27mA current. There are four low-power mode, the current consumption can be reduced to two microamps. Quick Start from low power mode to save energy too; starting circuit using STM32 internally generated 8MHz signal, the microcontroller from stop mode when you wake up with less than 6 microseconds.中文翻译：单片机STM321 STM32的介绍STM32系列基于专为要求高性能、低成本、低功耗的嵌入式应用专门设计的ARM Cortex-M3内核。

1、外文原文（复印件）A: The Utility Interface with Power Electronic SystemIntroductionWe discussed various powerline disturbances and how power electronic converters can perform as power conditioners and uninterruptible power supplies to prevent these poweline disturbances from disrupting the operation of critical loads such as computers used for controlling important processes, medical equipment, and the like. However, all power electronic converters (including those used to protect critical loads) can add to the inherent powerline disturbances by distorting the utility waveform due to harmonic currents injected into the utility grid and by producing electromagnetic interference, To illustrate the problems due to current harmonics ih in the input current i s of a power electronic load, consider the simple block diagram of Fig. 1-6A-1. Due to the finite (non-zero) internal impedance of the utility source which is simply represented by Ls in Fig. l-6A-1, the voltage waveform at the point of common coupling to the other loads will become distorted, which may cause them to malfunction. In addition to the voltage waveform distortion, some other problems due to the harmonic currents are as follows: additional heating and possibly overvoltages (due to resonance conditions) in the utility's distribution and transmission equipment, errors in metering and malfunction of utility relays, interference with communication and control signals, and so on. In addition to these problems, phase-controlled converters cause notches in the utility voltage waveform and many draw power at a very low displacement power factor which results in a very poor power factor of operation.The foregoing discussion shows that the proliferation of power electronic systems and loads has the potential for significant negative impact on the utilities themselves, as well as on their customers. One approach to minimize this impact is to filter the harmonic currents and the electromagnetic interference (EMI) produced by the power electronic loads. A better alternative, in spite of a small increase in the initial cost, may be to design the power electronic equipment such that the harmoniccurrents and the EMI are prevented or minimized from being generated in the first place. Both, the concerns about the utility interface and the design of power electronic equipment to minimize these concerns are discussed here.Generation of Current HarmonicsIn most power electronic equipment, such as switch-mode dc power supplies, uninterruptible power supplies (UPS), and ac and dc motor drives, ac-to-dc converters are used as the interface with the utility voltage source. Commonly, a line-frequency diode rectifier bridge as shown in Fig.1-6A-2 is used to convert line frequency ac into dc. The rectifier output is a dc voltage whose average magnitude Ud is uncontrolled.A large filter capacitor is used at the rectifier output to reduce the ripple in the dc voltage Ud. The dc voltage Ud and the dc current Id are unipolar and unidirectional, respectively. Therefore, the power flow is always from the utility ac input to the dc side. These line-frequency rectifiers with a falter capacitor at the dc side were discussed in detail in other section.A class of power electronic systems utilizes line-frequency thyristor-controlled ac-to-dc converters as the utility interface. In these converters, which were discussed in detail, the average dc output voltage Ud is controllable in magnitude and polarity, but the dc current Id remains unidirectional. Because of the reversible polarity of the dc voltage, the power flow through these converters is reversible. As was pointed out, the trend is to use these converters only at very high power levels, such as in high-voltage dc transmission systems. Because of the very high power levels, the techniques to ffdter the current harmonics and to improve the power factor of operation are quite different in these converters, as discussed in other section, than those for the line-frequency diode rectifiers.The diode rectifiers are used to interface with both the single-phase and the three-phase utility voltages. Typical ac current waveforms with minimal filtering were shown in other section. Typical harmonics in a single-phase input current waveform are listed in Table 1-6A-1, where the harmonic currents Ih are expressed as a ratio of the fundamental current Il. As is shown by Table 1-6A-l, such current waveformsconsist of large harmonic magnitudes. Therefore, for a finite internal per-phase source impedance Ls, the voltage distortion at the point of common coupling in Fig. 1-6A-1 can be substantial. The higher the internal source inductance Ls, the greater would be the voltage distortion.Current Harmonics and Power FactorAs we discussed in other section, the power factor PF at which an equipment operates is the product of the current ratio Il / Is and the displacement power factor DPF:In Eq. (1-6A-I), the displacement power factor equals the cosine of the angle Φ1. The current ratio Il / Is in Eq. (1-6A-l) is the ratio of the rms value of the fundamental frequency current component to the rms value of the total current. The power factor indicates how effectively the equipment draws power from the utility; at a low power factor of operation for a given voltage and power level, the current drawn by the equipment will be large, thus requiting increased volt-ampere ratings of the utility equipment such as transformers, transmission lines, and generators. The importance of the high power factor has been recognized by residential and office equipment manufacturers for their own benefit to maximize the power available from a wall outlet. For example from a 120V, 15A electrical circuit in a building, the maximum power available is 1.8 kW, provided the power factor is unity. The maximum power that can be drawn without exceeding the 15A limit decreases with decreasing power factor. The foregoing arguments indicate the responsibility and desirability on the part of the equipment manufacturers and users to design power electronic equipment with a high power factor of operation. This requires that the displacement power factor DPF should be high in Eq. (1-6A-I). Moreover, the current harmonics should be low to yield a high current ratio I1 / Is in Eq. (1-6A- 1).B: A Three-phase Pre-converter for Induction HeatingMOSFETBridge InvertersIntroductionHigh frequency power supplies, based on MOSFET bridge inverters, are already widely used for induction heating applications. These units require dc input voltages of about 400V to allow efficient operation of the MOSFETs employed. This supply voltage is usually obtained by using a three-phase rectifier stage, appropriate smoothing components or by employing thyristor phase- angle control to the mains supply. This kind of mains frequency power supply allows output power control of the induction heater, but it suffers from highly distorted input current waveforms with a low power factor. New legislation has been proposed to limit the maximum magnitude of harmonics drawn from the mains supply and different strategies have been suggested to reduce mains pollution.Investigations have been made to replace mains frequency power supplies by switched mode pre-converters. Switched mode converters can be designed to draw sinusoidal input currents thus avoiding the need for large and expensive mains frequency filters. At the same time these converters provide output power control and implementation of a small size high frequency isolation transformer. Power factor corrected three-phase ac-dc switched mode converter systems have usually been obtained using three identical single-phase converters with a common output filter. These systems overcome problems of mains pollution, but suffer from the disadvantage of a relatively large number of components and the need for complicated control and synchronization circuits. To reduce component costs, a structure based on a boost converter with three-phase input diode rectifier has been suggested. However, when operated direct-off-line from a three-phase 415V mains supply, this structure leads to high output voltages above lkV.In this paper, a novel method to achieve power factor correction for three-phase ac to dc power converters is described. The proposed topology is based on the buck converter and allows therefore output voltages to be below the maximum input voltage. The proposed topology utilizes a three- phase diode rectifier at the mains input and a single active switching device. The active switching device operates underzero-current switching conditions, resulting in very high converter efficiencies and low RFI emissions.Zero-current switching technique allows semiconductor devices to be operated at much higher switching frequencies and with reduced drive requirements compared with conventional switched mode operation.The proposed single-ended resonant converter with three-phase diode rectifier offers good opportunities for medium power, ac to dc applications. It combines simplicity and ease of control with high converter efficiency and high output power capabilities. It will be shown in the paper, that these characteristics make the converter very suitable as a direct replacement for the conventional mains frequency power supply used to supply induction heating MOSFET bridge inverters.General DescriptionA block diagram of the proposed induction heating system is shown in Fig. 1-6B-1. Block 1 represents the pre-converter that produces the dc supply voltage to feed to the RF MOSFET bridge inverter. Its output voltage should be controllable over a wide range to control the output power of the inverter and it must be able to operate with a wide range of load resistance to compensate load changes of the induction heating inverter stage. The pre-converter should operate direct-off-line from a three-phase 415V mains supply, drawing sinusoidal input current waveforms with a power factor approaching unity.Block 2 shows the RF MOSFET bridge inverter.The required maximum supply voltage of the MOSFET bridge lies between 300V and 400V. Block 3 represents the control and protection circuit used to stabilise the output power and to allow reliable operation of the induction heater in an industrial environment.Principle of Converter OperationA circuit diagram of the proposed three-phase ac to dc converter topology is shown in Fig. 1- 6B-2. The converter input currents are filtered through the input inductors L1, L2, L3. These inductors are designed so that the converter input currents are approximately constant over a whole switching cycle.During the OFF time of switch S, all three capacitors are charged by the inputcurrents I1, I2,I3. Consequently the three capacitor voltages Uc1, Uc1, Uc1 begin simultaneously to increase at a rate proportional to their respective input currents. If discontinuous operation is assumed the initial voltages of all capacitors C1, C2, C3 are zero when the switch ceases conducting. Hence, the peak voltage across each capacitor at the end of the OFF interval is proportional to their respective phase input current during the same OFF interval. Since capacitor voltages always begin at zero, it means that their average values during OFF time are linearly dependent on the phase input currents.During the ON time of switch S the energy stored in the three input capacitors C1, C2 and C3 is discharged through the six rectifier diodes VD1 –VD6, the switch S and the resonant inductor Lr. The rate of current decrease is dependent on the phase currents I1, I2, I3 and the switch current I0. The average value of the capacitor voltages Uc1, Uc2, Uc3 during the ON time are not linearly dependant on their phase input currents.To draw sinusoidal input currents from the mains supply the converter must draw input currents averaged over each switching cycle which are proportional to the phase voltages. Assuming steady state converter operation, the average phase input voltages over each switching cycle must be equal to the appropriate average input capacitor voltages during the switch OFF time plus the average input capacitor voltages during the switch ON time.Average input capacitor voltages during the switch OFF time have been shown to be proportional to the phase input currents, but during the switch ON time this is not true. However, if the switch ON time of the converter is mucteshorter than the switch OFF time, then the shape of the phase input currents will approach a sinusoidal waveform with unity power factor.2、外文资料翻译译文A:效用界面与电力电子系统介绍我们之前介绍了许多种电力线的干扰情况和电力系统转换器是如何在作为电力调节器和电力电子变换器时,用来防止那些电力线扰动干扰操作的临界荷载,例如电脑用于控制重要步骤,医疗设备,以及类似其他情况。

FLASH是美国MACROMEDIA公司推出的优秀软件。

它是一种交互式动画设计工具。

如今，FLASH作为网络动画的创作软件，已经越来越多地深入到传媒的各个领域，包括广告、影视、动漫、游戏、网页、课件、演示产品宣传等。

FLASH作为一个矢量动画的制作软件，其用途和功能已经超越了普通动画制作软件的标准，正在向一个交互平台的方向前进，在全球范围内，它已经成为网络多媒体的代名词、这些都说明FLASH软件的真正用途，那就是交互多媒体，它有着信息传递效率高、受众接受度高、宣传效果好的显著优势。

本次毕业设计以FLASH软件作为主要的动画制作工具，并用ACDSEE软件进行图片格式的转化和大小的压缩，完成了电子相册的制作。

本论文主要介绍了电子相册的设计过程和实现方法。

最后，在论文的结尾部分，对动画设计过程中出现的问题作了深入的思考和总结，并向在本次制作毕业设计过程中为我提供帮助的老师和同学表示感谢.简介FLASH的前身是FUTURE W A VE公司的FUTURE SPLASH，是世界上第一个商用的二维矢量动画软件，用于设计和编辑FLASH文档。

1996年11月，美国MACROMEDIA公司收购了FUTURE W A VE，并将其改名为FLASH。

在出到FLASH 8以后，MACROMEDIA又被ADOBE公司收购。

，最新版本为：ADOBE FLASH CS5。

FLASH 是一种创作工具，设计人员和开发人员可使用它来创建演示文稿、应用程序和其它允许用户交互的内容。

FLASH 可以包含简单的动画、视频内容、复杂演示文稿和应用程序以及介于它们之间的任何内容。

通常，使用FLASH 创作的各个内容单元称为应用程序，即使它们可能只是很简单的动画。

您也可以通过添加图片、声音、视频和特殊效果，构建包含丰富媒体的FLASH 应用程序。

FLASH 特别适用于创建通过INTERNET 提供的内容，因为它的文件非常小。

FLASH 是通过广泛使用矢量图形做到这一点的。

单片机的外文文献及中文翻译一、外文文献Title: The Application and Development of SingleChip Microcontrollers in Modern ElectronicsSinglechip microcontrollers have become an indispensable part of modern electronic systems They are small, yet powerful integrated circuits that combine a microprocessor core, memory, and input/output peripherals on a single chip These devices offer significant advantages in terms of cost, size, and power consumption, making them ideal for a wide range of applicationsThe history of singlechip microcontrollers can be traced back to the 1970s when the first microcontrollers were developed Since then, they have undergone significant advancements in technology and performance Today, singlechip microcontrollers are available in a wide variety of architectures and capabilities, ranging from simple 8-bit devices to complex 32-bit and 64-bit systemsOne of the key features of singlechip microcontrollers is their programmability They can be programmed using various languages such as C, Assembly, and Python This flexibility allows developers to customize the functionality of the microcontroller to meet the specific requirements of their applications For example, in embedded systems for automotive, industrial control, and consumer electronics, singlechip microcontrollers can be programmed to control sensors, actuators, and communication interfacesAnother important aspect of singlechip microcontrollers is their low power consumption This is crucial in batterypowered devices and portable electronics where energy efficiency is of paramount importance Modern singlechip microcontrollers incorporate advanced power management techniques to minimize power consumption while maintaining optimal performanceIn addition to their use in traditional electronics, singlechip microcontrollers are also playing a significant role in the emerging fields of the Internet of Things （IoT) and wearable technology In IoT applications, they can be used to collect and process data from various sensors and communicate it wirelessly to a central server Wearable devices such as smartwatches and fitness trackers rely on singlechip microcontrollers to monitor vital signs and perform other functionsHowever, the design and development of systems using singlechip microcontrollers also present certain challenges Issues such as realtime performance, memory management, and software reliability need to be carefully addressed to ensure the successful implementation of the applications Moreover, the rapid evolution of technology requires developers to constantly update their knowledge and skills to keep up with the latest advancements in singlechip microcontroller technologyIn conclusion, singlechip microcontrollers have revolutionized the field of electronics and continue to play a vital role in driving technological innovation Their versatility, low cost, and small form factor make them an attractive choice for a wide range of applications, and their importance is expected to grow further in the years to come二、中文翻译标题：单片机在现代电子领域的应用与发展单片机已成为现代电子系统中不可或缺的一部分。

外文翻译DC GENENRATORS1. INTRODUCTIONFor all practical purposes, the direct-current generator is only used for special applications and local dc power generation. This limitation is due to the commutator required to rectify the internal generated ac voltage, thereby making largescale dc power generators not feasible.Consequently, all electrical energy produced commercially is generated and distributed in the form of three-phase ac power. The use of solid state converters nowadays makes conversion to dc economical. However, the operating characteristics of dc generators are still important, because most concepts can be applied to all other machines.2. FIELD WINDING CONNECTIONSThe general arrangement of brushes and field winding for a four-pole machine is as shown in Fig.1. The four brushes ride on the commutator. The positive brusher are connected to terminal A1 while the negative brushes are connected to terminal A2 of the machine. As indicated in the sketch, the brushes are positioned approximately midway under the poles. They make contact with coils that have little or no EMF induced in them, since their sides are situated between poles.Figure 1 Sketch of four-pole dc matchineThe four excitation or field poles are usually joined in series and their ends brought out to terminals marked F1 and F2. They are connected such that they produce north and south poles alternately.The type of dc generator is characterized by the manner in which the fieldexcitation is provided. In general, the method employed to connect the field and armature windings falls into the following groups (see Fig.2):Figure2 Field connections for dc generators:(a)separately excited generator;(b)self-excited,shunt generator;(c)series generator;(d)compound generator;short-shunt connection;(e)compoundgenerator,long-shunt connection.The shunt field contains many turns of relatively fine wire and carries a comparatively small current, only a few percent of rated current. The series field winding, on the other hand, has few turns of heavy wire since it is in series with the armature and therefore carries the load current.Before discussing the dc generator terminal characteristics, let us examine the relationship between the generated voltage and excitation current of a generator on no load. The generated EMF is proportional to both the flux per pole and the speed at which the generator is driven, EG=kn. By holding the speed constant it can be shown the EG depends directly on the flux. To test this dependency on actual generators is not very practical, as it involves a magnetic flux measurement. The flux is produced by the ampere-turns of the field coils: in turn, the flux must depend on the amount of field current flowing since the number of turns on the field winding is constant. This relationship is not linear because of magnetic saturation after the field current reaches a certain value. The variation of EG versus the field current If may be shown by a curve known as the magnetization curve or open-circuit characteristic. For this a given generator is driven at a constant speed, is not delivering load current, and has its fieldwinding separately excited.The value of EG appearing at the machine terminals is measured as If is progressively increased from zero to a value well above rated voltage of that machine. The resulting curve is shown is Fig.3. When Ij=0, that is, with the field circuit open circuited, a small voltage Et is measured, due to residual magnetism. As the field current increases, the generated EMF increases linearly up to the knee of the magnetization curve. Beyond this point, increasing the field current still further causes saturation of the magnetic structure to set in.Figure 3 Magnetization curve or open-circuit characteristic of a separately excited dc machine The means that a larger increase in field current is required to produce a given increase in voltage.Since the generated voltage EG is also directly proportional to the speed, a magnetization curve can be drawn for any other speed once the curve is determined. This merely requires an adjustment of all points on the curve according ton n x E E G G ''where the quantities values at the various speeds.3. VOLTAGE REGULATIONLet us next consider adding a load on generator. The terminal voltage will then decrease (because the armature winding ha resistance) unless some provision is made to keep it constant. A curve that shows the value of terminal voltage for various load currents is called the load or characteristic of the generator.Figure 4 (a) directs current it to urge the generator load characteristics; (b) circuit diagramFig.4 shows the external characteristic of a separately excited generator. The decrease in the terminal voltage is due mainly to the armature circuit resistance RA. In general,A A G t R I E V -=where Vt is the terminal voltage and IA is the armature current (or load current IL) supplied by the generator to the load.Another factor that contributes to the decrease in terminal voltage is the decrease in flux due to armature reaction. The armature current established an MMF that distorts the main flux, resulting in a weakened flux, especially in noninterpole machines. This effect is called armature reaction. As Fig.4 shows, the terminal voltage versus load current curve does not drop off linearly since the iron behaves nonlinear. Because armature reaction depends on the armature current it gives the curve its drooping characteristic.4. SHUNT OR SELF-EXCIITED GENRATORSA shunt generator has its shunt field winding connected in parallel with the armature so that the machine provides its own excitation, as indicated in Fig.5. The question arises whether the machine will generate a voltage and what determines the voltage.For voltage to “build up ” as it is called, there must be some remanent magnetism in the field poles. Ordinarily, if the generator has been used previously, there will be some remanent magnetism. We have seen in Section 3 that if the field would be disconnected, there will be small voltage Ef generated due to this remanent magnetism, provided that the generator is driven at some speed. Connecting the field for self-excitation, this small voltage will be applied to the shunts field and drive a small current through the field circuit. If this resulting small current in the shunt field is of such a direction that it weakens the residual flux, the voltage remains near zeroand the terminal voltage does not build up. In this situation the weak main pole flux opposes the residual flux.Figure 5 Shunt generator:(a)circuit;(b)load characteristicIf the connection is such that the weak main pole flux aids the residual flux, the induced voltage increases rapidly to a large, constant value. The build-up process is readily seen to be cumulanve. That is, more voltage increases the field current, which in turn increases the voltage, and so on. The fact that this process terminates at a finite voltage is due to the nonlinear behavior of the magnctic circuit. In steady state the generated voltage is causes a field current to flow that is just sufficient to develop a flux required for the generated EMF that causes the field current to flow.The circuit carries only dc current, so that the field current depends only on the field circuit resistance, Rf. This may consist of the field circuit resistance Rf, the field current depends on the generated voltage in accordance with Ohm ’s law.It should be evident that on a new machine or one that has lost its residual flux because of a long idle period, some magnetism must be created. This is usually done by connecting the field winding only to a separate dc source for a few seconds. This procedure is generally known as flashing the field.Series GeneratorsAs mentioned previously, the field winding of a series generator is in series with the armature. Since it carries the load current the series field winding consists of only a few turns of thick wire. At no load, the generated voltage is small due to residual field flux only. When a load is added, the flux increases, and so does the generated voltage. Fig.7 shows the load characteristic of a series generator driven at a certain speed. The dashed line indicates the generated EMF of the same machine with the armature open-circuited and the field separately excited. The difference between the two curves is simply the IR drop in the series field and armature winding, such that)(S A A G t R R I E V +-=where RS is the series field winding resistance.Figure 7 Series generator: (a)circuit diagram;(b)load characteristicsCompound Generators The compound generator has both a shunt and a series field winding, the latter winding wound on top of the shunt winding. Fig.8 shows the circuit diagram. The two windings are usually connected such that their ampere-turns act in the same direction. As such the generator is said to be cumulatively compounded.The shunt connection illustrated in Fig.8 is called a long shunt connection. If the shunt field winding is directly connected across the armature terminals, the connection is referred to as a short shunt. In practice the connection used is of little consequence, since the shunt field winding carries a small current compared to the full-load current. Furthermore, the number of turns on the series field winding. This implies it has a low resistance value and the corresponding voltage drop across it at full load is minimal.Curves in Fig.9 represents the terminal characteristic of the shunt field winding alone. By the addition of a small series field winding the drop in terminal voltage with increased loading is reduced as indicated. Such a generator is said to be undercompounded. By increasing the number of series turns, the no-load and full-load terminal voltage can be made equal; the generator is then said to be flatcompounded. If the number of series turns is more than necessary to compensate for the voltage drop, the generator is overcome pounded. In that case the full-load voltage is higher than the no-load voltage.Figure 9 Terminal characteristics of compound generators compared with that of the shunt generatorThe overcompounded generator may be used in instances where the load is at some distance from the generator. The voltage drops in the feeder lines are the compensated for with increased loading. Reversing the polarity of the series field in relation to the shunt field, the fields will oppose each other more and more as the load current increase. Such a generator is said to be differentially compounded. It is used in applications where feeder lines could occur approaching those of a short circuit. An example would be where feeder lines could break and short circuit the generator. The short-circuit current, however, is then limited to a “safe”value. The terminal characteristic for this type of generator is also shown in Fig.9. Compound generators are used more extensively than the other types because they may be designed to have a wide varity of terminal characteristics.As illustrated, the full-load terminal voltage can be maintained at the no-load value by the proper degree of compounding. Other methods of voltage control are the use of rheostats, for instance, in the field circuit. However, with changing loads it requires a constant adjustment of the field rheostat to maintain the voltage. A more useful arrangement, which is now common practice, is to use an automatic voltage regulator with the generator. In essence, the voltage regulator is a feedback control system. The generator output voltage is sensed and compared to a fixed reference voltage deviation from the reference voltage gives an error signal that is fed to a power amplifier. The power amplifier supplies the field excitation current. If the error signal is positive, for example, the output voltage is larger than desired and the amplifier will reduce its current drive. In doing so the error signal will be reduced to zero.中文翻译直流发电机1.介绍对于所有实际目的来说，直流发电机仅用于特殊场合和地方性发电厂。

AnimationAnimation is the rapid display of a sequence of images of 2—D or 3-D artwork or model positions to create an illusion of movement. The effect is an optical illusion of motion due to the phenomenon of persistence of vision ， and can be created and demonstrated in several ways 。

The most common method of presenting animation is as a motion picture or video program ， although there are other methods.Early examplesAn Egyptian burial chamber mural, approximately 4000 years old ， showing wrestlers in action 。

Even though this may appear similar to a series of animation drawings ， there was no way of viewing the images in motion 。

It does ， however, indicate the artist’s intention of depicting motion.Five images sequence from a vase foundin IranThere is no single person who can be considered the ”crea tor" of film animation ， as there were several people working on projects which could be considered animation at about the same time.Georges Méliès was a creator of special —effect films; he was generally one of the first people to use animation with his technique. He discovered a technique by accident which was to stop the camera rolling to change something in the scene, and then continue rolling the film 。