Process and temperature insensitive CMOS oscillator using current sinker compensation

  • 格式:pdf
  • 大小:636.45 KB
  • 文档页数:4

frequencies which are200,500,800,and1000MHz.The pat-terns are called divisive as they are consists of main lobes as shown in Figure7.The energy distributed is not equal which is right lobe is smaller in magnitude compared to the left lobes because some energy released has been absorbed by the resistor.4.CONCLUSIONBased on Refs.3,5,8,and9,the physical dimensions of the planar monopole antenna presented are considered small in size and broadband.This antenna is fed from the bottom of the patch.After a lot of parameter optimization routine,the compact size with optimum performance is obtained.By integrating50 dual bevel angle with a single100X resistor,the more current flow to the ground and the radiating element has become more magnetic.Thus,the proposed antenna achieved a very wideband impedance bandwidth of approximately more than200%.A pro-totype antenna was designed,fabricate and the performance measure is presented.The antenna has the ability to operate for the VHF and partial of UHF spectrum.Besides the targeted white spaces(broadcasting spectrum)is also catered by this antenna.This gives it more credit as a great choice for the CR applications in the future.ACKNOWLEDGMENTSThe authors thank the Government of Malaysia,Ministry of Sci-ence,Technology and Innovations for the funding(Vote79300) that enabled this work to be accomplished and also special thanks to the members of Wireless Communication Centre(WCC),Fac-ulty of Electrical Engineering,Universiti Teknologi Malaysia for their help and kindness.REFERENCES1.M.J.Marcus,Unlicensed cognitive sharing of TV spectrum:Thecontroversy at the federal communications commission,IEEE Commun Mag43(2005),24–25.2.J.R.Kelly,E.Ebrahimi,P.S.Hall,P.Gardner,and F.Ghanem,Combined wideband and narrowband antennas for radio applica-tions,In:Cognitive Radio and Software Defined Radios:Technolo-gies and Techniques,London,2008.3.W.-S.Lee,D.-Z.Kim,K.-J.Kim,and J.-W.Yu,Wideband planarmonopole antennas with dual band-notched characteristics,IEEE Trans Microwave Theory Tech54(2006),2800–2806.4.T.Chakravarty,S.M.Roy,S.K.Sanyal,and A.De,A novel micro-strip patch antenna with large impedance bandwidth in VHF/UHF range,Prog Electromagn Res54(2005),83–93.5.M.J.Ammann and Z.N.Chen,A wide-band shorted planar monop-ole with bevel,IEEE Trans Antennas Propag51(2003),901–903.6.J.Chu,C.Ruan,X.Liao,and Y.Cui,A small size broadbandantenna used in VHF/UHF band,Presented at the8th International Symposium on IEEE Antennas,Propagation and EM Theory, 2008.ISAPE2008.7.Y.Y.Kyi,L.Jianying,and G.Y.Beng,Study of broadband smallsize conical antenna,Presented at the IEEE Antennas and Propaga-tion Society International Symposium,Albuquerque,NM,2006. 8.M.T.Islam,M.N.Shakib,N.Misran,and T.S.Sun,Broadbandmicrostrip patch antenna,Eur J Sci Res27(2009),174–180.9.D.Y.Xia,H.Zhang, F.Z.Geng,and Q.Y.Zhang,A study ofsphere-loaded and dielectric-covered mono-conical antenna for broadband application,Presented at the IEEE Antennas and Propo-gation Society International Symposium,Albuquerque,NM,2006. V C2011Wiley Periodicals,Inc.PROCESS AND TEMPERATURE INSENSITIVE CMOS OSCILLATOR USING CURRENT SINKER COMPENSATIONM.Kim,1S.Jung,2and Y.Yang11School of Information and Communication Engineering, Sungkyunkwan University,Suwon440-746,Republic of Korea; Corresponding author:yang09@2Samsung Techwin,Sungnam,Republic of KoreaReceived25March2011ABSTRACT:This article presents a simple complementary metal-oxide-semiconductor(CMOS)ring oscillator using a voltage-controlled delay and RS-latch,including a compensation circuit for the process and temperature variations.The compensation circuit,added to the original bias circuit,is a simple current sinker which is referenced through a current mirror circuit.The proposed oscillator was designed and implemented using a0.13l m CMOS process.The oscillator exhibited a significantly improved frequency variation of64.25%for a wide temperature range of fromÀ40to80 C.Without the compensation circuit,the variation would have been613.39%from the center frequency of2.33MHz.The oscillator also showed a low sensitivity of 0.084%to process variation,according to a Monte-Carlo simulation with1000iterations.V C2011Wiley Periodicals,Inc.Microwave Opt Technol Lett54:160–163,2012;View this article online at .DOI10.1002/mop.26493Key words:oscillator;temperature compensation;CMOS1.INTRODUCTIONA clock generator in general provides analog,digital,or mixed-signal systems with a system clock[1].For precision clock gen-eration,a phase-locked loop(PLL)is ordinarily used[2–4].The PLL includes an off-chip temperature compensated crystal oscil-lator(TCXO)or even an oven-controlled crystal oscillator (OCXO)to supply a stable and accurate frequency reference[4]. Despite having an excellent precision in frequency over temper-ature variations,such compensation methods involve a complex circuit structure and require some external components.A slightly simpler method is the use of a frequency-locked loop (FLL)[5].This does not need an external oscillator for refer-ence,but the circuits are still very complex.Therefore,in some low-cost applications,which require mod-erate-precision clocks,fully integrated oscillators with an improved insensitivity in frequency over temperature or process variation can be adopted.Conventional CMOS oscillators have significant frequency variation mainly because of the carrier mo-bility and threshold voltage variations of the transistor according to the process or temperature variation[6,7].For this reason, many previous researchers have been attempting to design more insensitive oscillators[1,5,8–14].Except for PLL and FLL methods,which are too expensive for low-cost applications,many compensation schemes for tem-perature and/or process variations have been proposed[1,8–14]. Most of them are methods that use compensated bias circuits.A temperature compensation circuit based on a bias circuit with Vt sensing and its replica bias circuit has been proposed [1].This circuit exhibited an excellent compensation perform-ance but it still requires a complex compensation circuit.A sim-ple compensation circuit,based on a stack of PMOS and bipolar junction transistor(BJTs),was demonstrated with provide just a moderate compensation performance[9].In[12],a compensa-tion circuit with an adjustable current ratio was presented.It has a moderate compensation capability,but requires a verycomplex digital switching part.A reference voltage generator with a positive temperature coefficient using two OP amps was proposed in [13].A good performance was reported,but the cir-cuits involved were significantly complex.A method using a con-stant gm bias and its replica circuit was presented in [14].This approach provides a moderate complexity and performance.In this article,a simple CMOS ring oscillator using voltage-controlled delays (VCDs)and an RS-latch,including a compen-sation circuit based on simple current mirror,is proposed for low-end clock generators.Though the proposed compensationcircuit has a simpler structure than those described in previous works [1,8–14],it has comparable or even better compensation capability over a wide temperature range.This circuit consists of PMOS and NMOS diodes which pro-vide an appropriate reference voltage for an NMOS current sinker according to the process and temperature variations.For a reduced variation of the oscillation frequency,theNMOSFigure 1Schematic diagram of the CMOS oscillator with VCDs and anRS-latchFigure 2Simulation results (a)Oscillation frequencies according to the varying control voltages for VCD as parameters of temperature.(b)Required control voltages to have a fixed oscillation frequency overtemperatureFigure 3Proposed compensation circuit with an NMOS currentsinkerFigure 4Simulation results (a)Simulated control voltages,V1.(b)Oscillation frequencies according to the temperature with and without the compensation circuitcurrent sinker diverts an appropriate amount of current accord-ing to the temperature from the original bias circuit of the oscillator.For verification,the ring oscillators with and without the compensation circuit were designed and implemented using a 0.13l m CMOS process.Temperature variation was measured and compared for both oscillators.Monte-Carlo simulation was used to evaluate the process variation.2.CIRCUIT DESIGN2.1.CMOS OscillatorFigure 1shows a schematic diagram of the CMOS ring oscilla-tor based on VCD circuits and an RS-latch.The oscillator also consists of a simple bias circuit,which supplies a control volt-age of V1to the VCD blocks,and has two buffer stages.The voltage V1controls the delay of each VCD block so that the os-cillation frequency is determined.The oscillation frequency is directly changed by the delay variation of the VCD which is controlled by V1.Conversely,the oscillation frequency,which tends to vary for the process and temperature variations,can be fixed by appropriately chang-ing V1.Therefore,the VCD needs a compensated bias circuit to have an adjustable control voltage of V1against the environ-mental changes.On the basis of the schematic diagram of the oscillator,shown in Figure 1,a 2.33MHz CMOS ring oscillator,including VCDs and an RS-latch,was initially designed.Figure 2(a)shows oscil-lation frequencies according to the varying control voltages for the VCD at various temperatures.If an application requires a clock generator to operate with an oscillation frequency of 2.33MHz,the clock generator has to include a bias circuit with a con-trol voltage range of approximately from 0.45to 0.85V.Figure 2(b)is a plot for the extracted control voltages to have a fixed os-cillation frequency over a temperature ranges from À40to 80 pensation CircuitFigure 3shows the proposed compensation circuit which is composed of a reference generator and an NMOS current sinker.Both are adjusted by each degeneration resistor,R2and R3,respectively.Another reference voltage,V2,in the compensation circuit is generated by the reference circuit using M5,M6,and R2,which has exactly the same configuration with the reference circuit as used for V1.Controlled by V2,the current sinker,based on M8and R3,diverts the compensation current (Icomp)from the original bias circuit through which flows a current,I1.The simulated control voltages,V1,with and without the compensation circuits are shown in Figure 4.As shown,the voltage curve of V1without the compensation circuit is significantly steeper than the required control voltage curve over the temperature range of interest.If voltage V1increases as the temperature increases,the volt-age V2in the compensation circuit also increases.The increased voltage,V2,diverts more current Icomp,so that thecontrolFigure 5Layout of the CMOS oscillator with the compensationcircuitFigure 6Simulated and measured oscillation frequencies overtemperatureFigure 7Monte-Carlo simulation results of the designed oscillators with and without the compensation circuitTABLE 1Performance SummaryW/O CompensationW/CompensationFrequency (MHz)2.33Temperature range ( C)À40to 80Power consumption (l W) 2.182.19Size (l m 2)125.51Â89.34138.22Â90.62Freq.variation (%)over temp.613.3964.25Process sensitivity (r /l )(%)0.1320.084r ,standard deviation;l ,average frequency.voltage,V1,decreases.This negative feedback behavior of the temperature compensation circuit allows the control voltage,V1, to have aflatter oscillation frequency response over the tempera-ture range,as shown in Figure4(b).A little mismatch in the voltage in the high temperature region after compensation does not cause much change in frequency.Degeneration resistors of R2and R3are used to optimize the level of compensation in terms of the oscillation frequency.3.EXPERIMENTAL RESULTSThe CMOS ring oscillator with the proposed temperature com-pensation circuit is designed and fabricated using Samsung’s 0.13l m commercial CMOS process.Figure5shows the layout of the proposed oscillator with a size of138.22Â90.62l m2. The implemented IC was evaluated with a bias supply of1.15V with a very low current consumption of as low as1.91l A.Figure6shows the simulated and measured oscillation fre-quencies according to the temperature variations.The proposed oscillator with the compensation circuit has a significantly smaller frequency variation of8.5%from the center frequency, whilst the same oscillator used without the compensation circuit has a frequency variation of26.79%over the wide temperature range ofÀ40to80 C.To check the performance of the compensation circuit over the process variation,a Monte-Carlo simulation with1000itera-tions was carried out using Cadence’s Spectre.Figure7shows the resultant statistical distributions:in terms of the number of samples per each10kHz step.It is clearly shown that the pro-posed oscillator with the compensation circuit has a sharper and taller histogram which guarantees a better yield in the presence of process variation.The proposed oscillator with the compensa-tion circuit has a significantly smaller process sensitivity of 0.084%,whilst the oscillator without compensation has a process sensitivity of about0.132%.The process sensitivity is obtained using a standard deviation over its average frequency(r/l).Table1summarizes the performances of the implemented oscillator ICs with and without the proposed compensation cir-cuit.Table2compares the performances of the proposed oscilla-tor with those obtained from previously published work.4.CONCLUSIONSIn this article,a temperature and process insensitive CMOS os-cillator with a very simple compensation circuit is proposed. The compensation circuit,which is added to the original bias circuit,is just a current sinker referenced using a current mirror.The proposed oscillator was implemented using a commer-cial0.13l m CMOS process.The performance of the oscillator was measured and compared with the performance achievable without the compensation circuit.As a result,the proposed CMOS oscillator was found to exhibit a very small frequency variation of64.25%from the center frequency,whilst the same oscillator without compensation showed a variation of613.39% across the temperature variation of fromÀ40to80 C.The oscillator also displayed a significantly improved process sensitivity of0.084%at an average frequency of2.33MHz,which was simulated using a Monte-Carlo simulation with1000itera-tions.The proposed oscillator can be applied to realize a number of different low-cost and low-end clock generator designs. ACKNOWLEDGMENTSThis work was supported by National Research Foundation of Korea Grant funded by the Korean Government(2009-0067097).REFERENCES1.K.Sundaresan,P.E.Allen,and F.Ayazi,Process and temperaturecompensation in a7-MHz CMOS clock oscillator,IEEE J Solid--State Circuits41(2006),433–442.2.H.Ma,X.Tang,T.Wu,and Z.Cao,New method to design a low-phase-noise millimeter-wave PLL frequency synthesizer,Micro-wave Opt Technol Lett48(2006),1194–1197.3.F.Plessas and G.Kalivas,A5-GHz injection-locked phase-lockedloop,Microwave Opt Technol Lett46(2005),80–84.4.H.Chen,E.Lee,and R.Geiger,A2-GHz VCO with process andtemperature compensation,In:Proceedings of IEEE International Symposium Circuits and Systems2,1999,pp.569–572.5.K.Ueno,T.Asai,and Y.Amemiya,A30-MHz,90-ppm/C fully-integrated clock reference generator with frequency-locked loop, In:Proceedings of ESSCIRC,2009,pp.392–395.6.F.Fiori and P.S.Crovetti,A new compact temperature-compen-sated CMOS current reference,IEEE Trans Circuits and Systems 52(2005),724–728.7.R.Kumar and V.Kursun,Voltage optimization for temperature vari-ation insensitive CMOS circuits,Presented at the IEEE International Midwest Symposium Circuits and Systems1,2005,pp.476–479. 8.K.Kato,T.Sase,and H.Sato,A low-power128-MHz VCO formonolithic PLL IC’s,IEEE J Solid-State Circuits23(1988), 474–479.9.Y.-S.Shyu and J.-C.Wu,A process and temperature compensatedring oscillator,Presented at the IEEE Asia Pacific ASIC Confer-ence,1999,pp.283–286.10.T.S.Cheung,H.Wong,and Y.C.Cheng,250MHz NMOS relaxa-tion oscillator with enhanced linear voltage-frequency characteristic and temperature stability,Electron Lett28(1992),1917–1919. 11.D.-S.Min,S.Cho,D.S.Jun,D.-J.Lee,Y.Seok,and D.Chin,Temperature-compensation circuit techniques for high-density CMOS DRAM’s,IEEE J Solid-State Circuits27(1992),626–631.12.U.Denier,Analysis and design of an ultralow-power CMOS relax-ation oscillator,IEEE Trans Circuits and Systems I57(2010), 1973–1982.13.G.D.Vita,F.Marraccini,and G.Iannaccone,Low-voltage low-power CMOS oscillator with low temperature and process sensitiv-ity,Presented at the IEEE International Symposium Circuits and Systems,2007,pp.2152–2155.kshmikumar,V.Mukundagiri,and S.L.J.Gierkink,A pro-cess and temperature compensated two-stage ring oscillator,Pre-sented at the IEEE Custom Integrated Circuits Conference,2007, pp.691–694.V C2011Wiley Periodicals,Inc.TABLE2Performance Comparison[1][9][12][13][14]This Work Process(l m)0.250.60.350.350.130.13 Oscillation frequency7.02MHz680KHz 3.3KHz80KHz 1.25GHz 2.33MHz Temperature range( C)À40to12535to1350to700to80À40to120À40to80 Frequency variation(%)60.8464.765.563.4765.064.25Structure Vtsensing StackedPMOSand BJTAdjustablecurrent ratioFeedbackusing twoOP-AmpsConstant gmand its replicaCurrentsinker。