H265 HDMI高清视频编码器使用教程技术手册说明书

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HDMI高清编码器使用说明一、产品图：单机箱产品图3U结构产品图：二、产品概述：HDMI高清编码器是一款专业的高清音视频编码及复用产品，该产品具有1路HDMI音视频输入接口，支持H.264编码格式，可同时对视频音频进行编码。

输出TS双码流设计，可根据不同需要设置每一路的输出码流分辨率，该设备具有高集成，低成本的优势，可广泛应用于各种数字电视播出系统中。

支持3U结构，一台机箱可插入16张采集卡，双电源冗余结构，系统更稳定。

全面支持VLC解码操作。

三、应用范围：1、网络电视高清编码器2、可接入NVR硬盘录像机2、数字标牌高清流服务器3、视频会议系统视频服务器4、网络会议系统视频采集5、代替高清视频采集卡6、酒店宾馆有线电视系统四、主要特性：·H.264 Baseline Profile编码·H.264 Main Profile编码. H.264 High Profile编码·MJPEG/JPEG Baseline编码·音频编码支持MPEG1 Audio Layer 2. CBR/VBR/ABR码率控制，16kbit/s～40Mbit/s. 网络接口采用1000M 全双工模式·1通道HDMI输入，支持VGA转HDMI输入·支持高达720P，1080P的高清视频输入·支持图像参数设置·支持HDCP协议，支持蓝光高清·支持HTTP，UTP，RTSP，RTMP，ONVIF 协议·WEB操作界面，中英文配置界面可选. WEB操作界面权限管理·支持广域网远程管理(WEB)·支持双码流输出. 主码流与副码流可以采用不同的网络协议进行传输·支持流分辨率设置·支持音频MP3与AAC格式选择·支持音频输出流单声道与立体声切换·支持GOP帧率设置. 支持码流增加水印功能，XY轴，字体可设置. 支持一键恢复默认配置·支持机顶盒解码·低功耗电源设计·3U高档机箱，主备电源自动切换功能，保证了系统的稳定输入：音频：系统：通用：五、系统设置：WEB操作界面设置时，需修改配置电脑的IP 192.168.1.* ，HDMI高清编码器出厂默认IP为：192.168.1.168复位初始化：面板上有个RST用于对HDMI高清编码器进行初始化复位，在通电状态下，按住不放10秒后会自动重启，所以参数会初始化。

H.265/H.264 HDMI编码器产品使用说明书目录一、产品概述1．产品概述2．应用场景3．产品参数二、浏览器使用说明1．系统登录2．预览界面3．编码器设置3.1 系统设置3.2 网络设置3.3 音视频设置3.4 安全设置三、VLC播放器设置前言感谢您使用本公司网络高清编码器产品，该产品是针对安防视频监控、IPTV网络直播、远程教学、远程医疗、庆典典礼、远程视频会议、自媒体直播应用的HDMI网络高清编码器。

采用高性能、单片SOC 芯片实现集音视频采集、压缩、传输于一体的媒体处理器，标准的H.265和H.264 Baseline 以及 Mainprofile 编码算法确保了更清晰、更流畅的视频传输效果。

内嵌 Web Server 允许用户通过 IE 浏览器方便地实现对前端视频的实时监看和远程控制。

该产品实际测试乐视云、百度云、目睹、Youtube和Wowza等服务媒体服务器，兼容海康威视H.265的NVR产品，支持TS流、RTMP、HTTP、RTSP和ONVIF等视频协议；支持AAC、G.711U和G.711A等音频编码。

以及需要运用到远程网络视频传输及直播的各种场合，本产品易于安装，操作简便。

声明：我们保留随时更改产品和规格，恕不另行通知。

这些信息不会被任何暗示或其他任何专利或其它权利转让任何许可。

读者对象：本手册主要适用于以下工程师：系统规化人员现场技术支持与维护人员负责系统安装、配置和维护的管理员进行产品功能业务操作的用户型号：TS-H264-B一、产品概述1．产品概述，该产品采用华为最先进的H.265网络高清数字音视频芯片压缩技术，具有稳定可靠、高清晰、低码率、低延时等技术特点。

该产品输入为高清HDMI视频信号，经过主芯片视频压缩编码处理，通过网络输出标准的TS流和RTMP视频流。

该产品的推出填补了行业内空白，直接取代了传统的视频采集卡，使用嵌入式操作系统保证产品更加稳定。

采用工业级铝合金外壳设计，体积小，方便安装。

H.265/H.264高清视频编码器上海禾鸟电子科技有限公司荣誉出品一、产品简介HDMI、SDI、VGA高清编码器H.265/H.264高清视频编码器有HN-HDMI-H-E（HDMI高清编码器）、HN-SDI-H-E（SDI 高清编码器）、HN-VGA-H-E（VGA高清编码器）三款产品，是上海禾鸟电子自主研发的用于高清视频信号（1080P60Hz）编码及网络传输的硬件设备，采用最新高效H.265/H.264高清数字视频压缩技术，具备稳定可靠、高清晰度、低码率、低延时等特点。

输入高清HDMI、SDI、VGA高清视频、音频信号，进行编码处理，经过DSP芯片压缩处理，输出标准的TS网络流，该产品的推出填补了业内空白，直接取代了传统的采集卡或软件编码的方式，采用硬编码方式，系统更加稳定，图像效果更加完美，广泛用于各种需要对高清视频信号及高分辨率、高帧率进行采集并基于IP 网络传送的场合,强大的扩展性更可轻易应对不同的行业及需求，可作为视频直播编码器。

采用工业控制精密设计，体积小，方便安装，功率小于5W，更节能，更稳定。

特点：●硬件编码●支持H.265高效视频编码●支持H.264 BP/MP/HP●支持AAC/ G.711高级音频编码格式●CBR/VBR码率控制，16Kbps～12Mbps●网络接口采用1000M 全双工模式●1通道HDMI或SDI或VGA+Audio输入●支持高达720P，1080P@60HZ的高清视频输入●支持图像参数设置● HDMI编码支持HDCP协议，支持蓝光高清●支持HTTP，UTP，RTSP，RTMP，ONVIF 协议●WEB操作界面，中英文配置界面可选●WEB操作界面权限管理●支持广域网远程管理(WEB)●支持双码流输出●主码流与副码流可以采用不同的网络协议进行传输●支持流分辨率自定义输出设置●支持码流插入文字功能，XY轴，字体可设置●支持码流插入图像水印功能，XY轴可设置●支持一键恢复出厂配置●低功耗电源设计二、产品应用：1、网络电视IPTV高清编码器2、可接入NVR硬盘录像机2、数字标牌高清流服务器3、视频会议系统视频服务器4、网络会议系统视频采集5、高清视频直播服务器6、有线电视系统前端采集7、移动直播高清前端采集8、医疗高清视频直播系统三、接口说明：说明：A、电源输入----- 12V/DC 输入接口，采用12V1A电源，如果是5V输入时，选用5V/2AB、初始化按钮------用于复位设备，当开机后，按住不放15秒后，设备IP恢复至出厂IP，192.168.0.31C、视频输入------用于输入高清HDMI、SDI、VGA、Audio信号。

Focus On FPGA/SOC Video IPZoBoVison H.265 Encoder FPGA IPFor Xilinx Kintex-7 SeriesE50B_Xilinx_K7_DemoUser GuideShen Zhen, CHINA Document Data: July 2015深圳市中博视清科技开发有限公司 Document Version: V3.0 service@video265@Release InformationItem Description Version V3.0IP Name E50B_Xilinx_K7_DemoRelease Data Aug 1th, 2015FPGA Support Xilinx Kintex-7k325xx and aboveLimitationCompare to Licensed version, the Demo Version have some limitations: ■ The ZoBo logo is added to encoded picture in some cases.■ Other special processing for picture used only in rare cases.■ Only 1080p/720p/480p frame size supported■ Slight performance lossKey Features■ HEVC/H.265 Main Profile■YUV420 , BitDepth 8■ Max. 1080p@60fps / 720p@120fps with single core■1920x1080p@30fps < 130MHz ( Demo Version, <115Mhz for licensed Version )■ low CPU load : only register setting needed■GOP configuration: I / P / B (max. BBBBBBBP )■CTU size: 64×64■ CU sizes: 8×8 ~ 64×64■Inter PU size: 8×8/8×16/16×8/16×16/32×32/ 64×64■Intra PU size: 4×4/ 8×8/16×16，■TU size: 4×4 /8×8 /16×16■ ¼ sub-pixel support■[±64H, ±32V] Search Range ( Larger range may supported for future version)■full-search for [±32H, ±16V] and almost full-search for other range.■all 35 intra prediction modes for supported PU sizes■RDO with TU4x4 /8x8 /16x16 simultaneously■ Hadamard Rdcost support■Single Slice or Title suported for 1080P@60fps encoding■High throughput CABAC architecture with max input 10bin/clock encoding capabilities ■All one CTU cabac data encoded within CTU encoding time，no entropy fifo overflow risk ■ Ultra low latency coding, Min encoder latency can be limited to CTU unit time.■high DRAM latency resilience■ Rate Control: JCTVC – K0103Implement Features■ 1920x1080p@60fps : 260MHz (230Mhz for licensed Version)■ 1280x720p@60fps : 125MHz■Fmax(xilinx_Kintex-7): 235M hz ( -3 speed) / 210Mhz ( -2 speed) / 190Mhz (-1 speed) ■LUTs utilization: ~180,000 (for xilinx_k7)■Registers utilization: ~150,000 (for xilinx_k7)■Memory utilization: 300 ( 5,500 kbits RAM)■DSPs utilization: 0■DDRx BandWidth: Max. 1.2GByte/s for 1080P@60fpsBlock DiagramFig 1. Encoder System Block DiagramI/O Signal DescriptionsTab 1. Encoder Interface SignalsSignal Name Direct Descriptionrstn Input Active LOW asynchronous reset .en Input Always be‘1’.clkenc Input Encoder core clock. The minimum of real-time clock is set accordingto encoder frame size and frame rate:■ clkenc (min_val) = ( Frame_num(CTU_64*64) + 6 ) × 8400 × Frame_rate■ Frame_num(CTU_64*64) = (Frame_Width/64 + (Frame_Width%64)? 1：0)×(Frame_Height/64 + (Frame_Height%64)? 1：0)For exsample:■ 1920*1080p@30fps : clkenc (min_val) = 130Mhz■ 1280*720p@30fps : clkenc (min_val) = 62Mhz■ 832*480p@30fps: clkenc (min_val) = 28Mhzclkcpu Input Encoder Configuration/Status Register R/W clock.Range : [ 1Mhz, 200Mhz]cpu_we Input Active high indicating that configuration register is written.cpu_addr[5:0] Input Config/Status Register R/W addr .cpu_wdata[9:0] Input Config Register write data.cpu_rdata[9:0] Output Config/Status Register read data.clkddr Input DDRx user domain clock. clkddr <= 200Mhzddr_oprq Output Active HIGH output indicating that encoder requesting thebeginning of a new DDRx batch data transfer. The signal will keepactive until ddr_opask assert and will keep LOW during the time ofthe data transmission.ddr_opwrt Output DDRx write or read flag. Valid data is indicated by ddr_oprqassertion.‘1’： DDRx write.‘0’: DDRx read.ddr_opfst Output Within One CTU(64x64) unit coding time, there may have multipleDDRx batch data transfer , when the signal is set to ‘1’, itindicating that the current batch data transfer is the first batch.■The signal is not necessary for DDRx wrtie or read.ddr_opnum[9:0] Output The number of data(128bit) to be transferred for a DDRx batch datatranfer. Valid data is indicated by ddr_oprq assertion.ddr_opaddr[27:0] Output 128bit aligned memory address of the first data(128bit) of a DDRxbatch data tranfer. Valid data is indicated by ddr_oprq assertion.Important Note:■ ddr_opaddr represent the first 128bit data address for a DDRxbatch data transfer, and the other 128bit data of the batch datatransfer have consecutive address increment by 1 .■ if the address range beyond external DDRx valid range, the highbits of the address can be discarded. For example, 1GB DDRxmemory requires 26 address bits to uniquely address each128bit and only ddr_opaddr[25:0] used.ddr_opask Input Active HIGH pulse indicating that external DDRx module is responseto encoder DDRx R/W requries.ddr_opwdrq Input Active HIGH pulse indicating that external DDRx module requires anew ddr_opdo[127:0] which will write to DDRx. When ddr_opwdrqset to ‘0’, ddr_opdo will keep unchanged.Important Note:■ When ddr_opwdrq active high, a new ddr_opdo will occurs in themean time, not the next rising clkddr.■ The first valid write data of the batch data transfer occurs whenddr_oprq assertion, and when the first ddr_opwdrq assert, thesecond data of the batch data transfer will occurs on ddr_opdo. ddr_opdo[127:0] Output The data write to DDRx.The first data of a new batch data transfer will occurs when ddr_oprqassert, and will keep unchanged until ddr_opwdrq assert. Onceddr_opwdrq active high, a new ddr_opdo occurs meanwhile.ddr_oprvld Input Active HIGH indicating a new read data is valid.ddr_oprdin[127:0] Input The data read from DDRx. Valid data is indicated by ddr_oprvldassertion.ddr_operr Output Active HIGH indicating that a error occurs during DDRx datatransfer. The reason of the error occurs is that all the data transferfor one CTU unit can not be done within the limit time.Once ddr_operr assert, it will keep unchanged until rstn assert.When ddr_operr assert, the result of the encoder may have wrongfor some frames.■The signal is not necessary for DDRx wrtie or read.bso_we Output Encoder bitstream output valid strobe.bso_do[15:0] Output Encoder bitstream output data.Configuration RegistersThe encoder working on the basis of video frame. When start a new frame encoding, Some registers should be cofigured again. When all the necessary configuration done, the enc_frm_start signal is written to corresponding register last to start a frame encoding.The Encoder have 32 configuration registers as shown in Tab2.The configuration register descripition is shown in Tab 3.Fig 2. show the timing sequence of read/write configuration registers. The input clkcpu is limited to 180Mhz.Figure 2. Config/Status Registers wrtie and readTab 2. Configuration Registers AddressAddress[5:0] Type Configuration Register [9:0]00h RW [9:1]: Reserved [0]: enc_frm_start01h RW [9:1]: Reserved [0]: enc_fstfrm02h RW [9:0]: enc_frm_pix_width[9:0] 03h RW [9:1]: Reserved [0]: enc_frm_pix_width[10] 04h RW [9:0]: enc_frm_pix_height[9:0] 05h RW [9:1]: Reserved [0]: enc_frm_pix_height[10] 06h RW Reserved07h RW [9:4]: Reserved[3]: bfrm_en [2:0]: bfrm_num[2:0]08h RW [9]: Reserved [8:0]: [8:0]: ifrm_period[8:0]09h RW [9:1]: Reserved [0]: rate_en0Ah RW [9:3]: Reserved [2:0]: rate_kbps[12:10]0Bh RW [9:0]: rate_kbps[9:0]0Ch RW [9:7]: Reserved [6:0]: rate_fps[6:0]0Dh RW [9:6]: Reserved [5:0]: frmqp_norate[5:0]0Eh RW [9:7]: Reserved[6]: rate_ifrmqp_force [5:0]: rate_ifrm_qp[5:0]0Fh RW [9:0]: Reserved10h RW [9:0]: ddr_src_frminit_addr[9:0]11h RW [9:0]: ddr_src_frminit_addr[19:10]12h RW [9:8]: Reserved [7:0]: ddr_src_frminit_addr[27:20] 13h RW [9:8]: Reserved [7:0]: ddr_ref_baseaddr_16MB[7:0] 14h RW [9:8]: Reserved [7:0]: ddr_bs_baseaddr_16MB[7:0] 15h RW [9]: ddr_bs_write [8]: ddr_bs_write_loop[7:0]: ddr_bs_space_16MB[7:0]16h RW Reserved17h RW Reserved18h~1Fh RW ReservedTab 3. Configuration Register DescriptionName Width Reset Descriptionenc_frm_start 1b 1 When all the necessary configuration done,wrtie enc_frm_start (value: 1) to correspondingregister to start a new frame encoding.enc_fstfrm 1b ■‘1’ : The first frame of the same videosequence to be encoded. In normal case, onlythe first frame of a new video source neededset ‘1’.■‘0’: Not the first frame of the same videosequence.enc_frm_pix_width 11b 1280 frame width (1920, etc); Must be multiple of 8;for Demo version, only support:1920*1080 / 1280*720 / 832*480enc_frm_pix_height 11b 720 frame height (1080, etc); Must be multiple of 8for Demo version, only support:1920*1080 / 1280*720 / 832*480ifrm_period 9 100 the number of non-iframe between twoconsecutive iframe, when set to ‘0’, allencoded frames treated as iframe.when B frame support, the value of ifrm_periodmust be multiple of (bfrm_num + 1 ).bfrm_en 1 0 when set to ‘1’, B-frame used.bfrm_num 3 3 the number of B-frame between twoconsecutive non-bframe.rate_en 1b 0 ■‘1’ : Enalble Rate Control■‘0’ : Disalble Rate Controlrate_kbps 13b 1000 Rate Control kbps (kbps unit).■ max limite: <8Mbps (For Demo Version) rate_fps 7b 30 Rate Control frame rate.■ fps range: [1, 120]rate_ifrmqp_force 1b 0 ■‘1’ : use rate_ifrm_qp as i_frame QP■‘0’ : use Rate Control result as i_frame QP. rate_ifrm_qp 6b 28 When rate_ifrmqp_force set ‘1’, i_frame QP isset to rate_ifrm_qp. range: [12,51]■Reset : 28frmqp_norate 6b 32 When rate_en set ‘0’, use frmqp_norate asframe QP. range: [12,51]ddr_src_frminit_addr 28b 0 Video source frame initial DDRx address (for128bit data width).■ Each frame to be encoded should configurethe DDRx initial address.ddr_ref_baseaddr_16MB 8b 4 Video reference frame space initial DDRxaddress (16MByte unit).■All 16MB space allocated for reference framecan not be used for other purposes.ddr_bs_baseaddr_16MB 8b 6 Encoder bit stream space initial DDRx address(16MByte unit).ddr_bs_space_16MB 8b 2 Encoder bitstream space size in 16Mbyte.■All space allocated for bitstream can not beused for other purposes.ddr_bs_write 1b 1 When this bit is set to ‘1’, the encoderbitstream will write to external DDRx.When set to ‘0’, only direct export modesupported.ddr_bs_write_loop 1b 1 When this bit is set to ‘1’, and when theDDRx bitstream space is write full, nextbitstream data will write to the beginning of thebitstream space again.when set ‘0’ and the DDRx bitstream space iswrite full, no more bitstream data writeStatus Registers.The result or status of the encoder can be acquried by status register, such as frame bitstream length or frame done flag.Tab 4. Status Registers AddressAddress[5:0]Type Status Register [9:0]20h R [9:8]: Reserved [7:0]: Device_ID[7:0]21h R [9:8]: Reserved [7:0]: Vendor_ID[7:0]22h R [9:8]: Reserved [7:0]: Revision_ID[7:0]23h R Reserved24h R Reserved25h R [9:1]: Reserved [0]: enco_frm_done26h R [9:0]: enco_frm_bs_numbyte[9:0]27h R [9:0]: enco_frm_bs_numbyte[19:10]28h R [9:2]: Reserved[1:0]: enco_frm_bs_numbyte[21:20]29h~3Fh R ReservedTab 5. Status Registers DescriptionName Width DescriptionDevice_ID 8 ffhVendor_ID 8 65hRevision_ID 8 30henco_frm_done 1 A ‘1’in this bit indicating that encoder now is in idlestate. When enc_frm_start assert, enco_frm_done willkeep‘0’until the frame done.enco_frm_bs_numbyte 23 Number of byte of the bitstream for video frame havejust been encoded.DDRx write/readFig 3. show the DDRx write timing sequence of the encoder user interface.Fig 4. show the DDRx read timing sequence of the encoder user interface.No matter write or read, the memory address of a batch data transfer is consecutive for any two neighboring 128bit data.Fig 3. DDRx Write for batch data tranfserFig 4. DDRx Read for batch data tranfserFig 5. DDRx write and read within CTU encoding timeAs shown in Fig 5, for each CTU64 encoding unit, max. 5 batch data transfers is required and they should be done within one CTU64 encoding time. For current version encoder, 8400 fixed clkenc period (not clkddr) is required for each CTU64 unit.■ When one batch data transfer is finished, the subsequent batch data transfer (ddr_opfst=0), if exist, will request to transfer data immediately by assert ddr_oprq. This characteristic can be used for DDRx read or write latency control.■ All the batch data tranfer for the same CTU unit, which the first batch transfer with ddr_opfst assert and max. 3 subsequent batch transfers with ddr_opfst deassert, should be done within one CTU64 encoding time.Bitstream Outputthere are two ways to export the encoder bitstream. One is write to external DDRx memory, and the other is directly output.Fig 6. show the timing sequence of the bitstream output. The first valid data of the frame bitstream is acquired after video frame encoding start, and the last valid data of the frame bitstream acquired before frame encoding done (Status register : enco_frm_done=1).■The bitstream of the encoder is byte aligned, and the output data bit width used for bitstream is 16bit, so the last byte (bso_do[7:0]) of the frame bitstream may be discarded when the value is zero.Fig 6. Encoder Bitstream direct outputDDRx Vsrc Frame Arrangement■ When start a new video frame encoding, the source frame to be encoded should avalible on the external DDRx memory.■ The video frame stored in DDRx memory is based on CTU(64×64) unit and all of the CTU units are stored in sequence order.■ As shown in Fig 7, the video frame is split into some CTU units. Each CTU unit have 64 pixel in horizontal and vertical direction. In the case of frame boundary, the CTU unit may have less than 64 pixel in Horizontal or Vertical, the region byond frame boundary should be filled by constant data.■ Each CTU unit have 4096 luma data and 2048 chroma data (YUV420). DDRx allocate 8192 byte memory space to store one CTU unit. The first 4096 byte space is used to store 4096 luma data and next 2048 byte for chroma data, the last 2048 byte not used.■ The DDRx user data width of the encoder is 128bit. For 64*64 CTU unit, 16 consecutive luma data or chroma data constitute a 128bit data. As shown in Fig8, For example, lumadata Y00 to Y015 constitute a 128bit data(MSB: Y00), chroma data U00V00 to U07V07 constitute a 128bit data(MSB: U00), etc.Figure 7. DDRx Video source frame arrangementFig 8. DDRx CTU unit arrangementE50B_Xilinx_K7_Demo V3.0 ZoBoVision H.265 Encoder IP User Guide 21深圳市中博视清科技开发有限公司video265@service@。

H.265/H.264HDMI STREAMING ENCODERUSING THE UNIT SAFELYBefore using this unit,please read below warning and precautions which provide important information concerning the proper operation of the unit.Besides,to assure that you have gained a good grasp of every feature of your new unit,read below manual.This manual should be saved and kept on hand for further convenient reference.Warning and Cautions※To avoid falling or damage,please do not place this unit on an unstable cart,stand,or table.※Operate unit only on the specified supply voltage.※Disconnect power cord by connector only.Do not pull on cable portion.※Do not place or drop heavy or sharp-edged objects on power cord.A damaged cord can cause fire or electrical shock hazards.Regularly check power cord for excessive wear or damage to avoid possible fire/electrical hazards.※Ensure unit is always properly grounded to prevent electrical shock hazard.※Do not operate unit in hazardous or potentially explosive atmospheres.Doing so could result in fire,explosion,or other dangerous results.※Do not use this unit in or near water.※Do not allow liquids,metal pieces,or other foreign materials to enter the unit.※Handle with care to avoid shocks in transit.Shocks may cause malfunction.When you need to transport the unit,use the original packing materials,or alternate adequate packing.※Do not remove covers,panels,casing,or access circuitry with power applied to the unit! Turn power off and disconnect power cord prior to removal.Internal servicing/adjustment of unit should only be performed by qualified personnel.※Turn off the unit if an abnormality or malfunction occurs.Disconnect everything before moving the unit.Note:due to constant effort to improve products and product features,specifications may change without notice.CONTENTS1.BRIEF INTRODUCTION (1)1.1.Overview (1)1.2.Main Features (1)1.3.Interfaces (1)2.SPECIFICATION (2)3.OPERATIONS GUIDE (2)work Configuration and Login (2)3.2.Management Web Page (3)nguage Settings (3)3.2.2.Device Status (3)work Settings (4)3.2.4.Main Stream Settings (4)3.2.5.Sub Stream Settings (6)3.2.6.Audio and Extension (7)3.2.7.System Settings (8)1.BRIEF INTRODUCTION1.1.OverviewSE1217is a HD audio and video encoder which can encode and compress HDMI video and audio source into IP stream,and then transmit it to streaming media server via network IP address to live broadcast on platforms like Facebook,YouTube,Ustream, Twitch,Wowza etc.1.2.Main Features●1×HDMI input,1×HDMI loop out,1×Analog audio input●Up to60fps at1920x1080streaming●H.265/H.264Stream Protocol●Dual-stream(Main stream and Sub stream)●RTSP/RTP/RTMP/HTTP/UDP/SRT unicast and multicast protocol●OSD Image and Text overlay●Mirror Image&Upside-down Image●Replace the capture,no computer to achieve the push stream.●Live stream without a computer connection1.3.Interfaces1LAN PORT FOR STREAM2AUDIO INPUT3HDMI INPUT4RESET/LED INDICATOR5DC12V IN6HDMI LOOPOUT2.SPECIFICATIONS3.OPERATIONS GUIDEwork Configuration and LoginConnect the encoder to network via a network cable.The default IP address of the encoder is192.168.1.168.The encoder can auto obtain a new IP address when it is using DHCP on the network,Or disable DHCP and configure the encoder and computer’s network in the same network segment.The default IP address as below.IP Address:192.168.1.168Subnet Mask:255.255.255.0Default Gateway:192.168.1.1Visit encoder’s IP address192.168.1.168through an Internet browser to login the WEB page for setting up.The default Username is admin,and password is admin.3.2.Management Web PageThe encoding settings can be set on the encoder management web page.nguage SettingsThere are languages of Chinese(中文),Japanese(日本語)and English for option on the top-right corner of the encoder management web page.3.2.2.Device StatusThe status of MAIN STREAM and SUB STREAM can be checked on the web page.And we also can have a preview on the streaming video from PREVIEW VIDEO.work SettingsThe network can be set to dynamic IP(DHCP Enable)or static IP(DHCP Disable).The default IP information can be checked in Part3.1.3.2.4.Main Stream SettingsThe main stream can be set to mirror image and upside-down image from MAIN PARAMETER tab.Configure main stream network protocol RTMP/HTTP/RTSP/ UNICAST/MULTICAST/RTP/SRT accordingly.Please note that only one of HTTP/ RTSP/UNICAST/MULTICAST/RTP can be enable at same time.3.2.5.Sub Stream SettingsConfigure sub stream network protocol RTMP/HTTP/RTSP/UNICAST/MULTICAST/ RTP/SRT accordingly.Please note that only one of HTTP/RTSP/UNICAST/ MULTICAST/RTP can be enable at same time.3.2.6.Audio and ExtensionThe audio can be from HDMI embedded audio or analog Line in audio.Audio Encode Mode can be ACC/MP3/MP2.83.2.7.SystemSettings。

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适用型号本手册适用于以下产品：产品型号产品名称及说明DS-6901UD 单路输出H.265高清解码器DS-6904UD 4路输出H.265高清解码器DS-6908UD 8路输出H.265高清解码器DS-6910UD 10路输出H.265高清解码器DS-6912UD 12路输出H.265高清解码器DS-6916UD 16路输出H.265高清解码器声明●设备接入互联网可能面临网络安全问题，请您加强个人信息及数据安全的保护。

目录目录 (1)一、硬件说明 (4)1.1硬件参数介绍 (4)1.1.1解码拼控一体云卡/拼控一体编码卡/解码拼控一体云主机参数介绍 (4)1.1.2单路网络视频解码器参数介绍 (6)1.2硬件接口介绍 (7)1.2.1解码拼控一体云主机接口板硬件接口介绍 (7)1.2.2解码拼控一体云主机主控卡硬件接口介绍 (8)1.2.3解码拼控一体云卡硬件接口介绍 (9)1.2.4拼控一体编码卡硬件接口介绍 (10)1.2.5单路解码器硬件接口介绍 (10)二、内置web网页使用说明 (11)2.1系统登录 (11)2.2修改设备IP地址 (11)2.3显示设置 (12)2.4参数配置 (23)2.4.1底图叠加 (23)2.4.2电视墙管理 (23)2.4.3预案管理 (25)2.4.4高级设置 (26)2.5集群配置 (35)2.5.1集群信息 (35)2.5.2集群管理 (37)2.6日志查询 (38)三、键盘控制说明 (38)3.1 RS-485键盘 (38)3.1.1透明通道 (38)3.1.2 PelcoP协议 (39)3.2网络键盘 (40)3.2.1键盘设置 (40)3.2.2设置键盘的IP地址 (40)3.2.3使用键盘控制解码器 (40)3.2.4按键说明 (40)四、虚拟矩阵控制 (41)4.1 TC-5820键盘虚拟矩阵控制 (41)4.2 TC-5880键盘虚拟矩阵控制 (42)附录1：适合监控使用的6x15布局 (43)附录2: 适合超大屏演示的8x12布局 (44)免责声明●本手册可能包含不准确的地方、产品功能操作方面的不符情况、或印刷错误。

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H.265/H.264高清视频编码器禾鸟电子科技荣誉出品一、产品简介H.265/H.264高清视频编码器有HDMI\SDI\VGA三种高清接口产品，是由禾鸟电子自主研发的用于高清视频信号编码及网络传输直播的硬件设备，采用最新高效H.265/H.264高清数字视频压缩技术，具备稳定可靠、高清晰度、低码率、低延时等特点。

输入高清HDMI、SDI、VGA高清视频、音频信号，进行编码处理，经过DSP芯片压缩处理，输出标准的TS网络流，直接取代了传统的采集卡或软件编码的方式，采用硬编码方式，系统更加稳定，图像效果更加完美，广泛用于各种需要对高清视频信号及高分辨率、高帧率进行采集并基于IP 网络传送的场合,强大的扩展性更可轻易应对不同的行业及需求，可作为视频直播编码器，录像，传输等应用。

采用工业控制精密设计，体积小，方便安装，功率小于5W，更节能，更稳定。

特点：●高性能硬件编码压缩●支持H.265高效视频编码●支持H.264 BP/MP/HP●支持AAC/G.711高级音频质编码格式●CBR/VBR码率控制，16Kbps～12Mbps●网络接口采用100M、1000M 全双工模式●主流，副流可推流不同的服务器●支持高达720P，1080P60HZ的高清视频输入●支持图像参数设置●HDMI编码支持HDCP协议，支持蓝光高清●支持HTTP，UTP，RTSP，RTMP，ONVIF 协议●主流与副流采用不同的网络协议进行传输●WEB操作界面，中英文配置界面可选●WEB操作界面权限管理●支持广域网远程管理(WEB)●支持流分辨率自定义输出设置●支持码流插入中英文字功能，字体背景、颜色可选●支持码流插入3幅透明图像水印功能，XY轴可设置●支持一键恢复出厂配置二、产品应用：1、4G移动直播高清前端采集2、高清视频直播服务器3、视频会议系统视频服务器4、数字标牌高清流服务器5、教学直播录像系统前端采集6、IPTV电视系统前端采集7、微信直播系统前端采集8、医疗视频直播与录像系统9、可接入NVR硬盘录像机三、接口说明：HDMI高清编码器（H265、H264）SDI高清编码器（H265、H264）VGA高清编码器（H265、H264）HDMI高清编码器（H264）SDI高清编码器（H264）VGA高清编码器（H264）3U结构编码器说明：A、电源输入----- 12V/DC 输入接口，采用12V1A电源，如果是5V输入时，选用5V/2AB、初始化按钮------用于复位设备，当开机后，按住不放15秒后，设备IP恢复至出厂IP，192.168.0.31C、视频输入------用于输入高清HDMI、SDI、VGA、Audio信号。

AVR-1716-4K16 Channel Penta-brid 4K 1U Digital Video RecorderWith the surveillance operators pursuing HD/UHD, which further adds to the storage and transmission cost, HDAVS H.265+/H.265 has been released to decrease the required bitrate while ensuring the video quality in realizing high resolution surveillance such as 4MP/4K. This series is designed for high cost performance and quality. The range offers a great solution for users facing budget constraints who require both quality and performance. This series improves encoding efficiency with the adoption of Smart H.265+/H.265, saving on bandwidth/storage costs, and significantly reducing the Total Cost of Ownership (TCO).Smart H.265+Smart H.265+ is the optimized implementation of the H.265 codec that uses a scene-adaptive encoding strategy, dynamic GOP, dynamic ROI, flexiblemulti-frame reference structure and intelligent noise reduction to deliver high-quality video without straining the network. Smart H.265+ technology reduces bit rate and storage requirements by up to 70% when compared to standard H.265 video compression.HDAVS/AHD/TVI/CVBS Auto DetectThe AVR can auto-recognize the signal of a camera without any configuration needing to be done. It makes operations friendlier and more convenient.●H.265+/H.265 dual-stream video compression ●Supports HDCVI/AHD/TVI/CVBS/IP videoinputs●Supports 32 channels of IPC access, eachchannel up to 8MP input; Max 128MbpsIncoming Bandwidth●IoT & POS functionalities●Smart Search and Intelligent Video SystemSystem Overview H igh Definition Camera InputThe AVR supports up to 5MP HDAVS cameras and6MP IP cameras input.Long Distance TransmissionThe HDAVS system supports long distancetransmission over coaxial cable and UTP, max. 700mfor 4K/4MP, 800m for 1080P and 1200m for 720P.Smart Fan DesignThe smart fan can automatically turn on or turn offaccording to the CPU temperature. This function caneffectively reduce the fan noise to provide a betteruser experience.Intelligent Video System (IVS)With built-in intelligent video analytics, the AVR hasthe ability to detect and analyze moving objects forimproved video surveillance. The AVR providesoptional standard intelligence at the edge allowingdetection of multiple object behaviors such asabandoned or missing objects. IVS also supportsTripwire analytics, allowing the camera to detectwhen a predetermined line has been crossed.Technical SpecificationMain Processor Embedded Processor Operating SystemEmbedded LINUXSystemVideo/Audio Compression H.265+/H.265/H.264+/H.264Image Resolution4K, 6MP, 5MP, 4MP, 3MP, 4M-N, 1080P, 720P, 960H, D1, CIFRecord RateMain stream: 4K(1~7fps); 6MP(1~10fps); 5MP(1~12fps); 4MP/3MP(1~15fps); 4M-N/1080P/720P/960H/D1/ CIF(1~25/30fps)Sub stream: 960H(1~15fps); D1/CIF(1~25/30fps)Bit Rate 32Kbps ~ 6144Kbps Per ChannelRecord ModeManual, Schedule (Regular, Continuous), MD (Video detection: Motion Detection, Video Loss,Tampering), Alarm, StopRecord Interval1 ~ 60 min (default: 60 min), Pre-record: 1 ~ 30 sec,Post-record: 10 ~ 300 secRecordingEthernet1 RJ-45 Port (1000M)Network FunctionsHTTP, TCP/IP, IPv4/IPv6, UPnP, RTSP, UDP, SMTP,NTP, DHCP, DNS, IP Filter, PPPoE,DDNS, FTP, Alarm Server, P2P, IP Search (Support IP camera,DVR, NVS, etc.)Max. User Access 128 usersSmart PhoneAndroid, iOS, iPhoneNetworkUSB 2 USB Ports (1 USB 2.0 , 1 USB 3.0)RS232 N/ARS4851 Port, for PTZ ControlAuxiliary InterfaceInternal HDD 2 SATA Ports, up to 10TB capacity for each disk External HDDN/AStoragePower Supply DC12V/5APower Consumption <20W (Without HDD)Working Environment -10°C ~ +55°C (+14°F ~ +131°F), 0~ 90% RH Dimensions (W×D×H)1U, 375mm×287mm×53mm (14.8" x 11.3" x 2.1")Weight3.2kg (7.0 lb) (without HDD)GeneralIP Video Input 16+16 Channel, each channel up to 8MP Analog Video Input 16Loop Output N/AAVS Resolution 4K, 6MP, 4MP, 1080P@25/30fps, 720P@50/60fps, 720P@25/30fpsAHD Resolution 5MP, 4MP, 3MP, 1080P@25/30, 720P@25/30fps TVI Resolution 5MP, 4MP, 3MP, 1080P@25/30, 720P@25/30fps CVBS StandardPAL/NTSCVideoInput 4 channel, RCA Output 1 channel, RCA Two-way TalkReuse audio in/out, RCAAudioDisplayTrigger Events Recording, PTZ, Tour, Alarm Out, Video Push, Email, FTP, Snapshot, Buzzer and Screen TipsVideo Detection Motion Detection, MD Zones: 396 (22 × 18), Video Loss, Tampering and Diagnosis Alarm Input 16 channel Relay Output3 channelInterface 1 HDMI, 1 VGAResolutionHDMI: 3840×2160, 2560×1440, 1920×1080, 1280×1024, 1280×720VGA: 1920×1080, 1280×1024, 1280×720Display SplitWhen IP extension mode not enabled: 16CH: 1/4/8/9/16When IP extension mode enabled: 16CH: 1/4/8/9/16/25Privacy Masking N/AOSDCamera title, Time, Video loss, Camera lock, Motion detection, RecordingVideo Detection & AlarmSync Playback 1/4/9/16Search ModeTime /Date, Alarm, MD and Exact Search (accurate to second)Playback FunctionsPlay, Pause, Stop, Rewind, Fast play, Slow Play, Next File, Previous File, Next Camera, Previous Camera,Full Screen, Repeat, Shuffle, Backup Selection,Digital Zoom Backup ModeUSB Device/NetworkPlayback & BackupCertificationsFCC: Part 15 Subpart BCE: CE-LVD: EN 60950-1/IEC 60950-1CE-EMC: EN 61000-3-2, EN 61000-3-3, EN 55032, EN 50130, EN 55024UL: UL 60950-1CertificationsDimensions (mm/in) Panels。