GRSPW资料

  • 格式:pdf
  • 大小:1.63 MB
  • 文档页数:48

Copyright Aeroflex Gaisler ABDecember 2008, Version 1.0.2SpaceWire CODEC with RMAP

GRSPW / GRSPW-FT

CompanionCore Data Sheet

GAISLER

Features

•Full implementation of SpaceWire standardECSS-E-ST-50-12C

•Protocol ID extension ECSS-E-ST-50-11C

•RMAP protocol ECSS-E-ST-50-11C

•AMBA AHB back-end with DMA

•Descriptor-based autonomous multi-packettransfer

•SEU protection and fault-tolerance

•Low area and high transfer frequency

•100 Mbit/s data transfer on Actel RTAX

•Support for Fusion, IGLOO, RT-ProASIC3/E,Axcelerator and RTAX-S Product FamiliesDescription

The GRSPW core implements a SpaceWireCodec with RMAP support and AMBATM hostinterface. The core implements the SpaceWirestandard with the protocol identificationextension and RMAP protocol draft. Receive andtransmit data is autonomously transferredbetween the SpaceWire Codec and the AMBAAHB bus using DMA transfers.

Through the use of receive and transmitdescriptors, multiple SpaceWire packets can bereceived and transmitted without processorinvolvement. The GRSPW control registers areaccessed through an APB interface.

Applications

The fault tolerant design of the SpaceWire core incombination with the radiation tolerant ActelFPGA gives total immunity to radiation effectsand makes it well suited for space applications.Transmitter

ReceiverD

S

SD

RxClockRecoveryTxClk

RxClockAHB MasterInterfaceTransmitterFIFO

N-CharFIFOLinkInterfaceFSMAHB clock domain

Tx clock domain

Rx clock domain

Data ParallelizationReceiver AHB FIFOTransmitterDMA Engine

RegistersAPBInterfaceReceiverDMA EngineSendFSM

RMAPReceiverRMAPTransmitter元器件交易网www.cecb2b.com2GRSPW / GRSPW-FT

Copyright Aeroflex Gaisler ABDecember 2008, Version 1.0.2

GAISLER

1Introduction

1.1Overview

The GRSPW core implements a SpaceWire Codec with RMAP support and AMBA host interface.The core implements the ECSS SpaceWire standard with the protocol identification extension andRemote Memory Access Protocol (RMAP).

Receive and transmit data is autonomously transferred between the SpaceWire Codec and the AMBAAHB bus using DMA transfers. Through the use of receive and transmit descriptors, multipleSpaceWire packets can be received and transmitted without CPU involvement. The GRSPW control

registers are accessed through an APB interface.

1.2Example application

The GRSPW core has been designed to fit into an architecture from which a large variety of applica-

tions can be derived. The architecture is centered around the AMBA Advanced High-speed Bus(AHB), to which the GRSPW core and other high-bandwidth units are connected. Low-bandwidthunits connected to the AMBA Advanced Peripheral Bus (APB) which is accessed through an AHB to

APB bridge. The architecture is shown in figure 2.

Figure 1. GRSPW block diagramAMBA AHBGRSPW

SpaceWire

APB slaveAHB masterSpaceWire signals

AMBA APBRMAP CtrlCodec

Registers

Figure 2. Architectural block diagram of a typical system using the SpaceWire codecLEON3FT32-bit SPARCInteger Unit

I-cacheDebugSupportUnitD-cache

CAN2.0ControllerMemoryControllerwith EDACSDRAMControllerwith EDACSpaceWireCodecInterfaceMil-Std-1553BC/RT/MTInterface2 x UART16 x GPIO

Mil-Std-1553RTInterface32-bit AMBA AHBTimersInterrupt

AHB/APBUARTDebugLinkJTAGDebugLinkOn-ChipMemorywith EDACFPU

PROM/SRAMSDRAMLVDS I/F3232

CAN-2.0Dual-1553Dual-1553AHBCTRL元器件交易网www.cecb2b.com3GRSPW / GRSPW-FT

Copyright Aeroflex Gaisler ABDecember 2008, Version 1.0.2

GAISLER

1.3Signal overview

The GRSPW signals are shown in figure 3. Note that the AMBA AHB and APB signals are imple-mented VHDL records and are not shown in detail.

1.4Implementation characteristics

The GRSPW is inherently portable and can be implemented on most FPGA and ASIC technologies.Table 1 shows the approximate cell count and frequency for four different GRSPW configurations onActel RTAX.

The GRSPW core is available in VHDL source code or as a pre-synthesized netlist. It can be deliveredfor stand-alone operation or with a wrapper for GRLIB AMBA plug&play interface.Table 1.Implementation characteristics (Cells (comb. / seq.) / RAM blocks / AHB MHz / SPW MHz)Core configurationRTAX2000S-1ASIC

GRSPW3,100 (2,100 / 1,000) / 3 / 40 / 10010,000 gates

GRSPW + RMAP4,700 (3,450 / 1,250) / 4 / 40 / 10015,000 gates

GRSPW-FT3,100 (2,100 / 1,000) / 5 / 40 / 10011,000 gates

GRSPW-FT + RMAP4,800 (3,550 / 1,250) / 6 / 40 / 10016,000 gatesFigure 3. Signal overviewclkrsttxclk

swni.dswni.sswni.tickinswni.clkdiv10swno.dswno.sswno.tickoutSpaceWire LinkClock & Reset

swni.timerrstvalswni.dcrstval

swni.rmapen

ahbmoahbmiapboapbiAMBAConfiguration元器件交易网www.cecb2b.com