SiP Design Tutorial

– U3: fixed die, flip chip, 130nm analog
Technology Shortfalls
Most design tools and data models were designed to handle one design mapped onto a single technology
Consumer
Functional density [+] Time to new product [+] Performance [+] Battery powered handheld: DAP, DSC, DVD, game console, CD, Camcorder Driving new IC technologies
Sept. 12-15, 2005 Napa, California 2005 DPC
High orders of design reuse (die, die stacks, sub-sys, ..)
Note: These comments are summarized from in depth customer engagements over the last two years.
Still an expert design process Does not live up to promises Difficult to know what is right product Lack of a robust design environment Poor control over concurrent design
3DIC
M1 M2
U3
Complex 3D Structures & Technologies
– U1: flip chip, 90nm digital – 3DIC:
U2: wire bond 130nm digital M1 & M2: direct die to die attach
Sept. 12-15, 2005 Napa, California 2005 DPC
Agenda
SiP Market Drivers Design & Technology Challenges Forming a System-level Solution Conclusions from the speaker
Sept. 12-15, 2005 Napa, California 2005 DPC
Si based substrates Wafer scale integration Bare DIE design chain
Sept. 12-15, 2005 Napa, California 2005 DPC
complexity
SiP Design Challenges
Most major IC companies and package foundries can and do design and produce SiP
SiP Design Challenges
SiP sub-system assembly System Sub U2 M1,2 System Design Hierarchy Concurrent designs & independent teams Unique IC processes Design chain geographically diverse U1 SiP U1 U3 U2
SiP Design Tutorial
Bill McCaffrey
Chief Architect SiP
Cadence Design Systems
Agenda
SiP Market Drivers Design & Technology Challenges Forming a System-level Solution Conclusions from the speaker
Sept. 12-15, 2005 Napa, California 2005 DPC
Q&A
Scope of Solution Concept
Focus only on key areas design flow Avoid specific tool discussions Demonstrate key concepts Based on a top-down systems approach
Q&A
Vertical Design Trends
Wafer-scale Integration Component data model for wafer Stacked Wafer 10 micron thick
SiP Die to Die Extreme memory integration sity Embedded Passives nal den e Complex wafer level testing r ctio anc Complex Technology Fun Powe rform Low tem pe MCM Data model Sys RF Digital Integration Flip-chip Multi-technology IC dB Hierarchical DFT Co-design of IC ? PKG ? PCB Complex Power System High-speed Ultra-high speed IO Interconnect High pin count More Complex MEMs RF Modules Design Kits and model standards 90’ s 00’ s 10’ s
Sept. 12-15, 2005 Napa, CaliforniaБайду номын сангаас 2005 DPC
Note: These comments are summarized from in depth customer engagements over the last two years.
Agenda
SiP Market Drivers Design & Technology Challenges Forming a System-level Solution Conclusions from the speaker
Sept. 12-15, 2005 Napa, California 2005 DPC
SiP Solution Building Blocks
Co-design environment
– – – – Common and qualified simulation models for Systems interconnects Package & silicon design-in kits Bare die component model Distributed design data management across domains and design chain Multi-die floorplanning (stacked, side by side, face to face) Advanced interactive wire-bonding Design for manufacturing 2D and 3D checking Autorouting Package selection IO planning and constraint assignment Feasibility and analysis of complex structures: multi-die stacking, 3DIC, passives, discrete components SiP connectivity management solution Signal and Power analysis Capture of specification of system interconnects System connectivity management solution Multi-component co-design with PCB driven constraints Integrated solution between RF design and package design Embedded passives, RF-IC, discrete components Mixed technology simulation, extraction
– – – – –
Sept. 12-15, 2005 Napa, California 2005 DPC
Note: These challenges are summarized from in depth customer engagements over the last two years.
– SiP requires a multi-domain / multi-technology design solution – Gaps between System design, implementation, and manufacturing must be closed – Lack of standard data model for die as components
Reduce time-to-new product concepts Overall system cost reduction Size reduction; fewer packages & stacked die Opportunity for higher performance and lower power Higher leverage of an open market design chain Leverage existing design and manufacturing capabilities Integration of mixed technologies in a single module Mixed function: RF, digital, MEMS