OM2E.1-CMOS Photonic Integrated Circuits

Integrated circuitIn electronics，an integrated circuit （also known as IC, microcircuit, microchip，silicon chip，or chip) is a miniaturized electronic circuit (consisting mainly of semiconductor devices, as well as passive components) that has been manufactured in the surface of a thin substrate of semiconductor material. Integrated circuits are used in almost all electronic equipment in use today and have revolutionized the world of electronics.Integrated circuits were made possible by experimental discoveries which showed that semiconductor devices could perform the functions of vacuum tubes，and by mid-20th-century technology advancements in semiconductor device fabrication. The integration of large numbers of tiny transistors into a small chip was an enormous improvement over the manual assembly of circuits using electronic components。

模拟CMOS基础知识一、什么是CMOS1.1 CMOS的定义和作用CMOS（Complementary Metal-Oxide-Semiconductor，互补金属-氧化物-半导体）是一种集成电路的制造工艺，也是一种特定类型的晶体管。

CMOS技术被广泛应用于逻辑电路、模拟电路和数模混合电路中。

CMOS在数字电路方面具有优异的性能，相比于传统的TTL（Transistor-Transistor Logic）和ECL（Emitter-Coupled Logic），CMOS电路功耗低、可靠性高。

它还具有良好的抗噪声特性和工作频率范围广的特点。

1.2 CMOS的组成结构CMOS电路由nMOS（n型金属-氧化物-半导体）和pMOS（p型金属-氧化物-半导体）两种晶体管组成。

nMOS晶体管的工作原理是通过控制门电压，使得通道导电或截止，实现电流的控制。

pMOS晶体管则与nMOS相反，通过控制门电压控制通道的导电或截止。

这两种晶体管可以根据不同的逻辑功能进行灵活组合，从而实现复杂的电路功能。

二、CMOS工作原理2.1 nMOS的工作原理•当门端施加了高电压（高于阈值电压），nMOS的沟道导通，形成通路，电流通过；•当门端施加了低电压（低于阈值电压），nMOS的沟道截止，电流停止。

2.2 pMOS的工作原理•当门端施加了低电压（低于阈值电压），pMOS的沟道导通，形成通路，电流通过；•当门端施加了高电压（高于阈值电压），pMOS的沟道截止，电流停止。

2.3 CMOS的工作原理CMOS电路由nMOS和pMOS组成，其工作原理有以下几个重要特点：1.CMOS电路在静态时消耗的功率几乎为零，只有在切换过程中才会有瞬态功率消耗；2.CMOS电路的输出具有较大的幅度和较小的延迟，能够同时输出高电平和低电平信号；3.CMOS电路的噪声干扰较小，具有良好的抗噪声特性；4.CMOS电路的工作速度较快，能够适应高频率的工作要求。

浅谈Silicon Photonics芯片Silicon Photonics芯片吸引着公司和研究人员的主要原因是成本低，功耗低，其中Si是导光的良好材料。

随着CMOS晶体管尺寸逐渐减小，光学器件却无法继续缩减，成了研究人员极其关注的一个研究方向。

其实，从上个世纪八九十年代开始，谈摩尔定律色变的各位先行者就开始探索半导体芯片的继任者，企图在硅芯片发展到物理极限时取而代之。

笔者还记得当初上学时，老师告诉我们CMOS工艺发展到十几纳米左右就会到物理极限。

结果现在7nm的芯片都造出来了，代替CMOS工艺的成熟技术还没有大规模应用。

这里，我们就介绍一下一种传说中在More than Moore中的技术。

Silicon Photonics。

早在1969年，贝尔实验室的ler首次提出了集成光学的概念。

随着微电子集成电路的发展，1972年，S.Somekh和A.Yarive提出了在同一半导体衬底上集成光学器件和电器件的设想。

上世纪90年代，随着硅基集成电路尺寸逐渐减小，其特征尺寸已进入光通讯波长范围。

另外，Si和SiO2材料之间的折射率差别较大，（Si大约3.45，SiO2大约1.44），容易发生全反射，这也有利于减小光集成器件尺寸，提高光芯片的密度。

然而，从另一方面来说，在CMOS晶体管尺寸已经缩小到10nm左右的今天，由于光学衍射效应，集成光学器件的尺寸无法继续缩小，这也在一方面限制了硅光芯片的发展。

因此，目前所说的Photonic Integrated Circuits （PIC），都是指在片上集成光连接和光电转换器件，再转换成电学信号用CMOS集成电路进行处理。

而不再是如最初提出时一般，用光学器件来完全取代晶体管。

正如上图所示，现在我们也只是发展到光纤到户，许多data center会用到光纤的板级互连。

但最下面的芯片级通讯，现在各大公司和科研院所已经有了demo的chip，100G的模块已经基本成熟，但距离市场级的全面应用还尚有很大的距离。

CMOS超大规模集成简述CMOS图像传感器集成电路是用CMOS工艺制造的，即便是只具有最基本功能的传感器芯片，也是一个相当复杂的超大规模系统集成。

芯片包括模拟电路、数字电路和光电传感器，属于特殊的混合型超大规模集成技术类型。

本节简单地叙述CMOS超大规模集成的一些基本概念，作为在后面的章节中对CMOS图像传感器集成电路芯片更详细讨论的铺垫和准备。

2.3.1CMOS器件的基本结构和原理CMOS是互补金属氧化物半导体（Complementary Metal Oxide Semiconductor）的英文缩写，这种半导体结构和工艺技术是本书讨论的CMOS图像传感器芯片的基础。

CMOS是由N型和P型两种极性类型互补的MOS场效应晶体管（FET）构成的。

一个N型MOSFET的结构如图2.6所示。

MOSFET的栅极是一个导体矩形面积，它下面有一个二氧化硅薄绝缘层，把栅极与下面的半导体衬底绝缘隔离开来。

N型MOSFET制作在P型硅衬底上，在衬底上的栅极两侧制作两个选择掺杂的N＋扩散区作为FET的源极S和漏极D，P型衬底由电极引出为B。

在栅极和薄氧化层的正下方，源极和漏极两个N＋扩散区之间的衬底区域在栅极正电压的作用下形成导电的N型沟道（N-channel），栅极和衬底之间形成的电场控制沟道中的电流。

图2.6（a）是晶体管结构的剖面图，图2.6（b）其俯视图，图2.6（c）是本书所采用的N 型MOSFET电路符号。

在MOS这个缩写名称中，字母M所代表的“金属”（Metal）是指栅极G所使用的导体材料。

而在现代的许多场效应管（FET）器件中，尤其是在CMOS超大规模集成电路芯片上，已经放弃了金属而采用同样导电的多晶硅（Poly Silicon）作为栅极，但是代表“金属”的字母M还是习惯地保留在名称MOS中。

图2.6N型MOSFET结构示意图在图2.7（a）、（b）所示的测试电路中，N型MOSFET的源极接0电位，衬底通过一个P＋扩散接触与源极连在一起，在栅极G和漏极D上各加上正电压V G和V D。

CMOS photodetector systems for low-level light applicationsNaser Faramarzpour ÆMunir M.El-Desouki ÆM.Jamal Deen ÆShahram Shirani ÆQiyin FangReceived:19August 2007/Accepted:17October 2007/Published online:8November 2007ÓSpringer Science+Business Media,LLC 2007Abstract In this work,we have designed,fabricated and measured the performance of three different active pixel sensor (APS)structures.These APS structures are studied in the context of applications that require low-level light detection systems.The three APS structures studied were—a conventional APS,an APS with a comparator,and an APS with an integrator.A special focus of our study was on both the signal and noise characteristics of each APS structure so the key performance metric of signal-to-noise ratio can be computed and compared.The pixel structures that are introduced in this work can cover a wide range of applications,such as high resolution digital photography using the APS with a comparator,to ultra-sensitive bio-medical measurements using the APS with an integrator.1IntroductionThe advances in deep submicron CMOS technologies and integrated microlens have made CMOS image sensors (especially the active pixel sensor—APS)a practical alternative to charge-coupled device (CCD)imaging technology.A key advantage of CMOS image sensors is that they are fabricated in standard CMOS technologies,which allows for full integration of the image sensor withthe analog and digital processing and control circuits on the same chip.This ‘‘camera-on-chip’’system leads to reduc-tion in power consumption,cost and sensor size,and it allows for integration of new sensor functionalities [1].The advantages of CMOS image sensors over CCDs [1–3]include lower power consumption,lower system cost,on-chip functionality leading to camera-on-chip solutions,smaller overall system size,random access of image data,selective readout,higher speed imaging,and finally the capability to avoid blooming and smearing.Some of the disadvantages of CMOS image sensors com-pared to CCDs are lower sensitivity,lower fill-factor,lower quantum efficiency,lower dynamic range (DR),all of which translate into the CMOS imager’s lower overall image quality [1–3].Typical APS sensors have a fill-factor (FF)of around 30%and the FF is typically limited by the interconnection metals and silicides that shadow the pho-tosensitive area and recombination of the photo-generated carriers with majority carriers [2].Among the many emerging CMOS imaging applica-tions,biomedical applications that require very low-level light imaging systems are considered a major design challenge.Low-level light bioluminescence applications [4]require novel techniques to reduce the sensor noise and dark current and to increase the gain and sensitivity to low-light levels.Such techniques may involve designs such as the one described in [5],where sensitivity to low-light levels was increased by biasing the photodiode of each pixel to near zero volts and by separating the photodiode from the integration node.Most successful designs that offer higher dynamic range and lower noise comprise of a smart APS,where data processing is done on the pixel level [1].Pixel level processing,which can be referred to as interpixel analog processing [6],can provide high SNR,low-power consumption,increased DR through adaptiveN.Faramarzpour ÁM.M.El-Desouki ÁM.J.Deen (&)ÁS.ShiraniDepartment of Electrical and Computer Engineering (CRL 226),McMaster University,Hamilton,ON,Canada L8S 4K1e-mail:jamal@mcmaster.caQ.FangDepartment of Engineering Physics,McMaster University,Hamilton,ON,Canada L8S 4K1J Mater Sci:Mater Electron (2009)20:S87–S93DOI 10.1007/s10854-007-9455-6image capturing and processing,and high speed due to parallelism and processing during the integration time[6]. Since there is a practical limit on the minimum pixel size (4–5l m),then CMOS technology scaling can be used to increase the number of transistors to be integrated into each pixel.For example,when using a CMOS0.18l m tech-nology with a595l m2pixel and a30%FF,eight analog transistors or32digital transistors can be integrated within the pixel[6].Since digital transistors take more advantage of CMOS scaling properties,digital pixel sensors(DPS)have become very attractive[1].A digital pixel sensor integrates an analog-to-digital converter(ADC)in each pixel and the digital data is read out from each pixel,thus resulting in a massively parallel readout and conversion that can allow for very high speed operation[7–10].The low FF of DPS sensors is no longer an issue for CMOS technologies of 0.18l m and below[1,6].The high speed readout makes CMOS image sensors suitable for very high-resolution imagers(multi-megapixels),especially for video applica-tions.For example,in[8],a3529288pixel CMOS image sensor was presented that is capable of operating at 10,000frames/s(1Gpixel/s)with a power consumption of 50mW.Smart pixels have been reported to reduce thefixed-pattern noise(FPN)by more than10times and to increase the dynamic range[11–13].For example,in[14],the high DR of132dB was achieved in a CMOS APS structure.In another example[15],the low-power design(40nW per pixel from a3.3V supply)with an in-pixel ADC and a free running continuous oscillator achieved a DR of104dB. Block-of-pixel readout was achieved in[16]using a DPS design that allowed for seamlessly scanning a595pixel kernelfilter across a pixel array of64932rather than a line-readout that would require readingfive lines to obtain the595block.In[17],a1-bitfirst order Sigma-Delta (RD)modulator used17transistors for each292block of pixels, 4.25transistors per pixel,to directly convert photocharge to bits.The design is suitable for infrared (IR)applications which require large charge handling capabilities andfine quantization levels.A Nyquist rate multi-channel-bit-serial(MCBS)ADC using successive comparisons,4.5transistors per pixel,to convert the pixel voltage to bits,was presented in[18].This design[18]is suitable for visible applications where lowfixed-pattern noise and low data rates are required.A pulse-frequency modulation(PFM)scheme was used in[19]to achieve pixel level ADC with a23%FF to allow for low-light adaptation by adjusting the saturation level.The average power consumption per pixel is85l W in a0.25l m CMOS ing two integration times,a linear APS sensor achieved a DR of92dB as compared to a DR of61dB with only one integration time[3].Despite the many improvements in CMOS sensors, some of which were highlighted above,there are currently no CMOS image sensors that can provide the image quality of CCDs in terms of noise,sensitivity and dynamic range [3].This makes CMOS image sensors application specific, since it is possible to improve some of the characteristics of the sensor,but not all of them.Different kinds of image sensors satisfy different performance requirements such as for digital photography,industrial vision,or for medical or space applications.In this article,three APS structures—the conventional APS sensor,the APS with an integrator,and the APS with a comparator,are discussed and compared to show their applicability to different applications.The article is orga-nized as follows.Section2introduces the three different APS structures,and the measurements performed—the conventional APS(Sect.2.1),the APS with comparator (Sect.2.2),and the APS with integrator(Sect.2.3).In Sect.3,the performance of the three different APS struc-tures is compared and their suitability for specific applications discussed.Finally,in Sect.4,the conclusions are presented.2Pixel structures studiedIn this work,we have designed and fabricated(using a foundry process)three different APS structures.The pixels are fabricated in a0.18l m,single poly,six-metal layer, salicide commercial CMOS technology.The different pixel structures are fabricated in the same technology and on the same die.In this way,a fair comparison of their perfor-mance can be made.The performance characteristics of the pixels are compared to verify their suitability for low-level light and other applications.2.1Three transistor APSThree transistor APS is the simplest and most commonly used APS structure.Each pixel in this structure consists of a photodiode and three transistors.Figure1a shows the APS circuit,with its designed layout shown later in Fig.7a. The pixel operates in repeating integration and reset peri-ods.During the integration time,transistor M1is off and the photodiode junction capacitance discharges by the internally generated photocurrent and dark current.The voltage drop during the integration period is proportional to the light intensity.At the end of integration,this voltage drop is read through transistor M2which acts as a buffer. Transistor M3connects the pixel to the readout bus.At the beginning of reset period,transistor M1is turned on for a few microseconds to charge the photodiode junctioncapacitance and to make the pixel ready for the next reading.Figure 1b shows the measured output waveform of the APS along with the reset signal.The integration time in this measurement is 20ms and the voltage drop is about 400mV.Low-level light applications require detectors with high signal-to-noise ratios (SNRs).The noise at lower levels of light can limit the detection capability of the optical sensor.There are different noise sources that affect the perfor-mance of an APS.During reset,the dominant noise source is the thermal noise.The noise power in the sense node voltage generated during reset is given by:n ¼kT 2C;ð1Þwhere k is the Boltzmann’s constant,T is the temperature in Kelvin,and C is the sense node capacitance.The effect of 1/f noise during reset has been analyzed in [20],and it has been shown that the reset noise is dominated by thermal noise.During integration,the shot noise is the dominating source of the noise.The noise power in the sense node voltage at the end of integration is approximately given by:n ’q ði PH þi DK ÞC 2t int ;ð2Þwhere q is the electronic charge,t int is the integration time,i PH is the photocurrent,and i DK is the dark current.The signal at the end of integration can be approximated with (i PH /C )t int .Assuming that all other sources of noise are small compared to the shot noise and that the dark current is negligible,then the SNR of the output (in dB),before saturation,can be approximated by:SNR ’10logi PH t int qð3ÞFigure 2shows the measured signal-to-noise ratio (SNR)of our APS,at different light levels for different durations of integration time.Equation 3indicates that SNR improves by increasing the integration time [21],given that the pixel capacity is not saturated at the end of integration.Figure 2implies that the SNR curve will cross zero at lower levels of light for a longer integration time.However,the integration time is limited in length by the rate of temporal variation of the signal to be measured.Also,the dark current of the pixel may saturate the pixel capacity before the long integration time ends.The number of transistors that could fit into a pixel was limited in past.This was due to the large size of transistors compared to the desired pixel pitch for medium-to high-resolution imagers.Deep submicron technologies have made it possible to put more transistors into the same die area.This has made the transition from passivepixelFig.1(a )Structure of a three transistor active pixel sensor.(b )Output of the APS on channel 1and reset signal on channel 2,captured on the oscilloscopescreenFig.2Signal-to-noise ratio (SNR)of the APS measured at different light powers and for different integration times.Equation 3suggests,and our measurements indicate,that in the region of operation of APS where the shot noise during integration is the dominant noise source,that the output SNR varies linearly with the logarithm of light powersensors(one transistor per pixel)to active pixel sensors (three transistors)and beyond,now possible.It is now feasible to do parts of the data processing within the pixel and develop smart pixels.Smart pixel systems are inte-grated and can perform sophisticated tasks faster than conventional imaging systems.In the following subsec-tions we analyze two APS pixels with in-pixel circuitry that are the core of many smart pixels.2.2APS with comparatorThe general structure of our APS pixel with an internal comparator is shown in Fig.3a.The pixel consists of eight transistors including the reset transistor,with the layout shown later in Fig.7b.The pixel has a reference level input and its output has a digital‘‘High’’or‘‘Low’’value,depending on the value of the sense node voltage across the photodiode relative to the value of the refer-ence voltage of the comparator v ref.The photodiode and reset transistor combination of the pixel works in the same manner as the conventional APS.Figure3b shows different signals from the pixel and how they correspond to each other.Waveforms1and2in Fig.3b are the measured reset signal and output of the pixel.Wave-forms3is an illustration of the internal sense node voltage,and waveform4is the reference level.After reset,the sense node voltage is above the reference level and the output is low.The sense node voltage will decrease during integration,and if the light level is high enough,it will cross the reference level.Therefore,the duration of the output pulse at low will be inverselyproportional to the light level and this is the output signal of the pixel.The time at which the output of the pixel goes from ‘‘High’’to‘‘Low’’isfixed by the externally applied reset. The time at which the pulse comes back to‘‘High’’how-ever,is affected by the noise that is present in the sense node voltage.The noise sources that contribute to the total noise of the sense node voltage are the same as the three-transistor APS described above in Sect.2.1.In this APS with a comparator,an easy way to quantify the noise is from the jitter in the rising edge of the output pulse of the comparator.Figure4a shows the jitter of the output,cap-tured on the oscilloscope screen.Figure4b shows the root-mean-square(RMS)value of the jitter of the output, compared to the output pulse width.Figure4b shows that the SNR of the output is not the limiting factor in detection of the low-light-levels using this structure.However, sensing lower light levels requires higher integration times to let the sense node voltage drop enough to cross the reference level.This is similar to the three transistor APS, with the difference being that now the reference level can also be adjusted to optimize the detection of the light intensity range of interest.The main advantage of this structure is the immediate analog-to-digital conversion of the signal,inside the pixel, thus eliminating the readout noise of the consequent stages of the imager.It will also provide a parallel and fast A/D conversion of the signal,making it possible to achieve faster scanning times.2.3APS with integratorIn most of the APS structures,including the two that are described above,the photocurrent is integrated by the junction capacitance of the photodiode.A diode however, is not a perfect capacitor,as the junction capacitance changes with the applied bias[21].As a result,output of the APS becomes nonlinear[21,22]and this has an impact on both the signal and SNR characteristics[23].It should be mentioned that the sense node voltage capacitance of an APS has a parallel component equal to thegate-source Fig.3APS with comparator.(a)General schematic of the pixel and (b)Its measured and illustrated waveforms.Channel1shows the reset signal applied to the pixel,for a10ms readout time.Channel2shows the measured output of the pixel.Channel3shows the internal sense node voltage and compares it to the reference level of channel4capacitance of the buffer transistor (M2in Fig.1a).One can reduce the effect of nonlinear capacitance of the pho-todiode,by making the gate-source capacitance of M2high,such that it dominates the sense node capacitance.This solution will keep the capacitance at the sense node relatively constant.However,it will result in an increase in the size of the buffer transistor,thus reducing the fill-factor of the pixel.It will also reduce the charge-to-voltage conversion gain of the pixel,thus degrading its sensitivity.An integrator,using an operational amplifier,can solve this problem by keeping the sense node voltage constant and integrating the photocurrent in its fixed capacitor.We have designed a pixel with a current integrator that integrates the photocurrent into an on-chip metal-oxide-metal capacitor.The schematic of the APS with integrator is shown in Fig.5a,with its layout shown in Fig.7c.The measured output of the APS with integrator is shown in Fig.5b.After the reset period,the capacitance of the integrator discharges.During integration,theoperational amplifier of the integrator keeps the bias over the photodiode fixed.This causes the photocurrent gener-ated in the photodiode to be integrated in the capacitor rather than the photodiode.The output of the integrator will then increase in proportion to the generated photocurrent during the integration time.Figure 6shows how the output of the APS with integrator varies with the incident light power.The measurements are done for light at different wavelengths and they show good linearity of the output with respect to the power of incident light,unless the pixel is saturated.Analysis of the shot noise during integration,for the APS with integrator,is similar to the three transistor APS with the only difference being in the value of the capaci-tance.However,the effect of 1/f noise will be more important now,as different elements of the integrator also contribute to the 1/f noise.It is important to remember that frequency domain analysis is not applicable for the analysis of 1/f noise in this circuit,as APS is a switched circuit,and the 1/f noise will appear as a cyclo-stationary process initsFig.4(a )Measured output of the APS with comparator,zoomed in to show the jitter in its output.This jitter is the noise of the output as the pulse width is the output of the pixel.(b )Measured signal (pulse width)and noise (jitter)of the output of the pixel,as a function of lightpowerFig.5APS with integrator.(a )General schematic of the pixel and (b )Its measured waveforms.Channel 1shows the measured output of the pixel,while channel 2shows the reset signal applied to the pixel,for a 2.5ms readout timeoutput [20].A time domain analysis of the noise,using the auto-covariance function of the equivalent total trap num-ber in the trap model of the 1/f noise d ,can be performed to get the power of noise [21],and the result is:V 2n ¼qCAt r Z t r 0Z t r0d s 1;s 2Às 1j j ðÞd s 2d s 1ð4Þwhere A is the channel area of the reset transistor and t r is the reset time.The output noise level of the APS with integrator,in general,is higher than the equivalent three transistor APS pixel.One advantage of the proposed APS with integrator design is that the size of the photodiode and the capaci-tance of the integrator can be chosen independently.Thus the capacity of the pixel can be adjusted while keeping the photosensitive area of the pixel fixed.The main advantage of this structure,however,is its performance in dark.The amplifier of the structure keeps the bias applied to the photodiode fixed.The bias level is controlled by the inputv b which is very close to zero.At these small bias voltages,the dark current generated in the photodiode is small compared to the dark current of the conventional APS generated at a bias close to V DD [24].As a result,the output voltage read from the pixel at dark will be small,compared to the three transistor APS.3Comparison and discussionThree different APS structures are introduced in this work.Each of the structures has characteristics that make it suitable for certain types of applications.Table 1compares these structures and some of their key performance mea-sures.The three transistor APS has the simplest structure and highest fill-factor.It is suitable for applications that require ultra-high resolution imaging.It has also the least noisy output,because it has the least number of transistors in its data path to the output.The APS with the comparator structure has an accept-able fill-factor of 36%due to our compact design,and this is shown in Fig.7b.It has a digital output,which makes it applicable to ultra-fast digital imagers.It is possible to adjust the reference level and integration time,and thus to achieve good sensitivity at the desired light levels.It also has the widest dynamic range,as the sense node voltageisFig.6Output of the APS with integrator,sampled at different levels of incident light power.Measurements are done at different wave-lengths.It can be observed that a good linearity exists in the output,unless the output saturates,as shown in the curve for the 700nmlightFig.7Layouts of different APS structures.(a )Threetransistor APS has the simplest layout and highest fill-factor.(b )The APS with comparator has eight transistors.However,our compact design has kept the fill-factor at a high level.(c )The APS with integrator.Thisdesign considers a capacitor in each pixel that reduces the fill-factor of the pixel.However,the fill-factor is still at a reasonable levelTable 1Comparison of the APS structures studiedAPSAPS with comparator APS with integrator Photodiode size 20920l m 210910l m 210910l m 2Number of transistors 386Fill-factor 63%36%15%Output swing 1V 2.2V 0.8V Dark output rate50mV/s210mV/s16mV/sread and converted to digital level immediately,and the overhead voltage drops of amplifier and buffer stages do not affect the output.The APS with integrator structure has a lowfill-factor.It has a low dynamic range,is slow,thus it is not suitable for applications that require high scanning rates.However,its output is the most linear with respect to incident light power,and it has an internal dark current cancellation mechanism.These two features make this APS structure a good candidate for low-level light imaging using longer integration times.4ConclusionsIn this research,we have carefully compared the key per-formance characteristics of three different active pixel sensor structures—size of photodiode,number of transis-tors in pixel,fill-factor,output swing and dark output rate. The pixel structure with control transistors inside the imager pixel provides advantages such as easy integration in a two-dimensional array with readout capabilities com-pared to using only a photodiode.The simple three transistor APS is effective for high resolution and low noise applications.The APS with a comparator pixel is good for fast digital imaging and provides high dynamic range.Finally,the APS with a comparator has linear response and has the lowest dark output rate. Acknowledgments The authors are grateful to the Natural Sciences and Engineering Research Council(NSERC)of Canada,the Canada Research Chair program and KACST of Saudi Arabia for partially funding this research work.References1.A.El Gamal,H.Eltoukhy,IEEE Circuit.Devic.21(3),6–20(2005)2.E.R.Fossum,IEEE T.Electron.Dev.44(10),1689–1698(1997)3.M.Bigas,E.Cabruja,J.Forest,J.Salvi,Microelectr.J.37,433–451(2006)4.H.Eltoukhy,K.Salama,A.El Gamal,M.Ronaghi,R.Davis,Proc.Technical Digest of the IEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,2004,pp.222–2235.J.Honghao,P.A.Abshire,IEEE International Symposium onCircuits and Systems(ISCAS2006)pp.1651–16546.A.El Gamal,D.Yang,B.Fowler,Proc.SPIE.3650,2–13(1999)7.B.Fowler,A.El Gamal,D.X.D.Yang,Technical Digest of theIEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,(1994)pp.226–2278.S.Kleinfelder,S.H.Lim,X.Q.Liu,A.El Gamal,TechnicalDigest of the IEEE International Solid-State Circuits Conference (ISSCC),San Francisco,CA,(2001)pp.88–899.D.Yang,A.El Gamal,B.Fowler,H.Tian,IEEE J.Solid-St.Circ.34,1821–1834(1999)10.W.Bidermann,A.El Gamal,S.Ewedemi,J.Reyneri,H.Tian,D.Wile,D.Yang,Technical Digest of the IEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,(2003) pp.212–213.11.N.Faramarzpour,M.J.Deen,S.Shirani,Q.Fang,L.W.C.Liu,F.Campos,J.W.Swart,IEEE T.Electron.Dev.54,9(2007) December12.L.Liang-Wei,i,Y.-C.King,IEEE Sensors J.4(1),122–126(2004)13.J.L.Trepanier,M.Sawan,Y.Audet,J.Coulombe,IEEE Inter-national Midwest Symposium on Circuits and Systems Vol.2, 437–440(2002)14.D.Stoppa,A.Simoni,L.Gonzo,M.Gottardi,G.-F.Dalla Betta,IEEE J Solid-St Circ37(12),1846–1852(2002)15.L.G.McIlrath,IEEE J.Solid-St.Circ.36,846–853(2001)16.B.Tongprasit,K.Ito,T.Shibata,IEEE International Symposiumon Circuits and Systems Vol.3,(2005ISCAS),pp.2389–2392 17.B.Fowler,A.El-Gamal,Proc.Infrared Readout Elect.IV,SPIE3360,2–12(1998)18.D.Yang,B.Fowler,A.El Gamal,IEEE J Solid-St.Circ.34,348–356(1999)19.A.Bermak, A.Bouzerdoum,K.Eshraghian,Microelectr.J.33(12),1091–1096(2002)20.H.Tian,A.El Gamal,IEEE T.Circuits Syst.48(1),151–157(2001)21.N.Faramarzpour,M.J.Deen,S.Shirani,J.Vac.Sci.Technol.A(Special Issue Canadian Semiconductor Technology Conference) A24(3),879–882(2006)22.N.Faramarzpour,M.J.Deen,S.Shirani,IEEE T.Electron.Dev.53(9),2384–2391(2006)September23.Y.Ardeshirpour,M.J.Deen,S.Shirani,J.Vac.Sci.Technol.A(Special Issue Canadian Semiconductor Technology Conference) A24(3)(May/June2006)pp.860–86524.Y.C.Shih,C.Y.Wu,IEEE International Symposium on Circuitsand Systems Vol.1,(ISCAS2003),pp.809–812。

集成电路版图与⼯艺课程设计之⽤CMOS实现Y=AB+C电路与版图1 绪论1.1 设计背景集成电路设计（Integrated circuit design, IC design），亦可称之为超⼤规模集成电路设计（VLSI design），是指以集成电路、超⼤规模集成电路为⽬标的设计流程。

集成电路设计涉及对电⼦器件（例如晶体管、电阻器、电容器等）、器件间互连线模型的建⽴。

所有的器件和互连线都需安置在⼀块半导体衬底材料之上，这些组件通过半导体器件制造⼯艺（例如光刻等）安置在单⼀的硅衬底上，从⽽形成电路。

近些年来，集成电路技术发展迅猛，促使半导体技术不断地发展，半导体技术正在进⼊将整个系统整合在单⼀晶⽚上的时代。

故对VLSI的版图设计的要求也越来越⾼。

Tanner软件可提供完整的集成电路设计环境，帮助初学者进⼊VLSI设计领域。

本设计采⽤Tanner Tools Pro ⼯具，对逻辑为Y=AB+C进⾏电路设计与仿真、版图设计与仿真，在报告中给出电路图、版图与仿真结果。

1.2 设计⽬标设计⽬标逻辑：Y=AB+C⽤CMOS⼯艺设计逻辑为Y=AB+C的电路和版图。

因为CMOS是天然的反逻辑输出，所以需要先设计出逻辑为/Y=/（AB+C）的电路，再将输出接⼊⼀个CMOS反相器实现逻辑功能。

设计电路图（Schematic）时，N⽹络A与B串联且与C并联，P⽹络A与B并联且与C串联，在N和P⽹络的交界节点接⼊反相器后引出输出Y。

设计版图（Layout）时，在P型衬底（P-Sub）上进⾏制作，所以N-MOS管可以直接掺杂制作，⽽P-MOS管需要先制作⼀个N阱（N-Well），并在N阱⾥制作P-MOS管。

整个设计⽐较简单，仅仅使⽤单层⾦属布线（Meteal）。

导出电路和版图⽹表（spice）⽂件，⽤Tspice软件进⾏仿真波形，分析电路和版图是否设计正确性以及其性能如何。

在LVS验证中匹配电路原理图和版图逻辑和尺⼨匹配性，完成整个设计过程。

FEATURESAll-silicon time delayModels with 0.25 ns and 0.5 ns stepsProgrammable using 3-wire serial port or 8-bit parallel portLeading and trailing edge accuracy EconomicalAuto-insertable, low profile, 16-pin SOIC packageLow-power CMOS TTL/CMOS-compatibleVapor phase, IR and wave solderablePIN ASSIGNMENTPIN DESCRIPTIONIN - Delay Input P0-P7- Parallel Program Pins GND - Ground OUT - Delay Output V CC - +5 Volts S - Mode Select E - Enable C - Serial Port Clock Q - Serial Data Output D - Serial Data InputDESCRIPTIONThe DS1021 Programmable 8-Bit Silicon Delay Line consists of an 8-bit, user-programmable CMOSsilicon integrated circuit. Delay values, programmed using either the 3-wire serial port or the 8-bit parallel port, can be varied over 256 equal steps. The faster model (-25) offers a maximum delay of 73.75ns with an incremental delay of 0.25 ns, while the slower model (-50) has a maximum delay of 137.5 ns with an incremental delay of 0.5 ns. Both models have an inherent (step zero) delay of 10 ns. After the user-determined delay, the input logic state is reproduced at the output without inversion. The DS1021 is TTL- and CMOS-compatible, capable of driving 10 74LS-type loads, and features both rising and falling edge accuracy.The all-CMOS DS1021 integrated circuit has been designed as a reliable, economic alternative to hybrid programmable delay lines. It is offered in a space-saving surface mount 16-pin SOIC.Programmable 8-BitSee Mech. Drawings SectionIN E Q/PO P1P3P2GNDOUT P6P5DC P7V CC P4S 查询DS1021供应商PARALLEL MODE (S = 1)In the PARALLEL programming mode, the output of the DS1021 will reproduce the logic state of the input after a delay determined by the state of the 8 program input pins P0 - P7. The parallel inputs can be programmed using DC levels or computer-generated data. For infrequent modification of the delay value, jumpers may be used to connect the input pins to V CC and ground. For applications requiring frequent timing adjustment, DIP switches should be used. The enable pin (E) must be at a logic 1 in hardwired implementations.Maximum flexibility is obtained when the 8 parallel programming bits are set using computer-generated data. When the data setup (t DSE) and data hold (t DHE) requirements are observed, the enable pin can be used to latch data supplied on an 8-bit bus. Enable must be held at a logic 1 if it is not used to latch the data. After each change in delay value, a settling time (t EDV or t PDV) is required before input logic levels are accurately delayed.Since the DS1021 is a CMOS design, unused input pins (D and C) must be connected to well-defined logic levels; they must not be allowed to float.SERIAL MODE (S = 0)In the SERIAL programming mode, the output of the DS1021 will reproduce the logic state of the input after a delay time determined by an 8-bit value clocked into serial port D. While observing data setup (t DSC) and data hold (t DHC) requirements, timing data is loaded in MSB-to-LSB order by the rising edge of the serial clock (C). The enable pin (E) must be at a logic 1 to load or read the internal 8-bit input register, during which time the delay is determined by the last value activated. Data transfer ends and the new delay value is activated when enable (E) returns to a logic 0. After each change, a settling time (t EDV) is required before the delay is accurate.As timing values are shifted into the serial data input (D), the previous contents of the 8-bit input register are shifted out of the serial output pin (Q) in MSB-to-LSB order. By connecting the serial output of one DS1021 to the serial input of a second DS1021, multiple devices can be daisy-chained (cascaded) for programming purposes (Figure 3). The total number of serial bits must be eight times the number of units daisy-chained and each group of 8 bits must be sent in MSB-to-LSB order.Applications can read the setting of the DS1021 delay line by connecting the serial output pin (Q) to the serial input (D) through a resistor with a value of 1K to 10K ohms (Figure 2). Since the read process is destructive, the resistor restores the value read and provides isolation when writing to the device. The resistor must connect the serial output (Q) of the last device to the serial input (D) of the first device of a daisy-chain (Figure 3). For serial readout with automatic restoration through a resistor, the device used to write serial data must go to a high impedance state.To initiate a serial read, enable (E) is taken to a logic 1 while serial clock (C) is at a logic 0. After a waiting time (t EQV), bit 7 (MSB) appears on the serial output (Q). On the first rising (0 → 1) transition of the serial clock (C), bit 7 (MSB) is rewritten and bit 6 appears on the output after a time t CQV. To restore the input register to its original state, this clocking process must be repeated eight times. In the case of a daisy-chain, the process must be repeated eight times per package. If the value read is restored before enable (E) is returned to logic 0, no settling time (t EDV) is required and the programmed delay remains unchanged.Since the DS1021 is a CMOS design, unused input pins (P1 - P7) must be connected to well-defined logic levels; they must not be allowed to float. Serial output Q/P0 should be allowed to float if unused.FUNCTION BLOCK DIAGRAM Figure 1SERIAL READOUT Figure 2DS1021CASCADING MULTIPLE DEVICES (DAISY CHAIN) Figure 3PART NUMBER TABLE Table 1DELAYS AND TOLERANCES (IN ns)PART NUMBERSTEP ZERO DELAY TIMEMAX DELAY TIME (NOM)DELAY CHANGE PER STEP (NOM)MAX DEVIATION FROM PROGRAMMED DELAYDS1020-2510 ± 273.750.25±6DS1020-5010 ± 2137.50.5±8DELAY VS. PROGRAMMED VALUE Table 2M I N D E L A Y (S T E P Z E R O )M A X D E L A YP A R A L L E L P O R TS E R I A L P O R T000000111P7MSB000000111P6BINARYPROGRAMMED VALUE000000111P5000000111P4000000111P3000011111P2001100011P1PART NUMBER010101101P0LSBDS1021-2510.0010.2510.5010.7511.0011.2573.2573.5073.75DS1021-5010.010.511.011.512.012.5136.5137.0137.5All delays in nanoseconds, referenced to input pin.∬DS1021DS1021DS1021∬DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 4DS1021TEST SETUP DESCRIPTIONFigure 4 illustrates the hardware configuration used for measuring the timing parameters of the DS1021. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected to the output. The DS1021 serial and parallel ports are controlled by interfaces to a central computer. All measurements are fully automated with each instrument controlled by the computer over an IEEE 488 bus.TEST CONDITIONSINPUT:Ambient Temperature:25°C ± 3°CSupply Voltage (V CC): 5.0V ± 0.1VInput Pulse:High = 3.0V ± 0.1VLow = 0.0V ± 0.1VSource Impedance:50 ohms max.Rise and Fall Time: 3.0 ns max.(measured between 0.6V and 2.4V)Pulse Width:500 ns (DS1021–25)2 µs (DS1021–50)Period: 1 µs (DS1021–25)4 µs (DS1021–50)NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions.OUTPUT:Output is loaded with a 74F04. Delay is measured between the 1.5V level of the rising edge of the input signal and the 1.5V level of the corresponding edge of the output.ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground-1.0V to +7.0VOperating Temperature0°C to 70°CStorage Temperature-55°C to +125°CSoldering Temperature260°C for 10 secondsShort Circuit Output Current50 mA for 1 second* This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.DC ELECTRICAL CHARACTERISTICS(0°C to 70°C; V CC = 5.0V ± 5%) PARAMETER SYM TESTCONDITIONMIN TYP MAX UNITS NOTES Supply Voltage V CC 4.75 5.00 5.25V1 High Level InputVoltageV IH 2.2V CC + 0.5V1Low Level InputVoltageV IL-0.50.8V1Input LeakageCurrentI10.0V ≤ V I≤ V CC-1.0 1.0µAActive Current I CC V CC=MAX;Period=1 µs30.0mA3High Level Output Current I OH V CC=MIN.V OH=2.7V-1.0mALow Level Output Current I OL V CC=MIN.V OL=0.5V8mA4AC ELECTRICAL CHARACTERISTICS(0°C to 70°C; V CC = 5V ± 5%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Clock Frequency f C10MHzEnable Width t EW50ns Fig. 7, 8 Clock Width t CW50ns Fig. 8 Data Setup to Clock t DSC30ns Fig. 8 Data Hold from Clock t DHC10ns Fig. 8 Data Setup to Enable t DSE30ns Fig. 7 Data Hold from Enable t DHE20ns Fig. 7 Enable to SerialOutput Validt EQV50ns Fig. 8Enable to SerialOutput High Zt EQZ050ns Fig. 8Clock to SerialOutput Validt CQV50ns Fig. 8Clock to SerialOutput Invalidt CQX10ns Fig. 8 Enable Setup to Clock t ES50ns Fig. 8 Enable Hold from Clock t EH50ns Fig. 8 Parallel Input Validto Delay Validt PDV50µs Fig. 6(cont’d)PARAMETER SYMBOL MIN TYP MAX UNITS NOTESt PDX0nsParallel Input Changeto Delay InvalidEnable to Delay Valid t EDV50µsEnable to Delay Invalid t EDX0nsV CC Valid to Devicet PU100msFunctionalV CC Rise Time t VR20msInput Pulse Width t WI100% of OutputnsDelayInput to Output Delay t PLH, t PHL Table 2ns2 Input Period Period 2 (t WI)ns CAPACITANCE(T A = 25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C IN10pFTIMING DIAGRAM: SILICON DELAY LINE Figure 5TERMINOLOGYPeriod: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse.t WI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge.t RISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse.t FALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse.t PLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of the corresponding output pulse.t PHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input pulse and the 1.5V point on the trailing edge of the output pulse.TIMING DIAGRAM: NON-LATCHED PARALLEL MODE (S = 1, E = 1) Figure 6TIMING DIAGRAM: LATCHED PARALLEL MODE (S=1) Figure 7TIMING DIAGRAM: SERIAL MODE (S = 0) Figure 8TIMING DIAGRAM: POWER-UP Figure 9NOTES:1.All voltages are referenced to ground.2.@ V CC = 5V and 25°C. Delay accurate on both rising and falling edges within tolerances given inTable 1.3.Measured with output open.4.The “Q” output will only source 4 mA. This pin is only intended to drive other DS1021s.。