Applying Slicing Technique to Software Architectures
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有难度的技巧英文Challenging Skill Techniques1. Advanced Data Analysis: This skill involves conducting complex statistical analyses, data mining, and using advanced software and programming languages like R or Python to extract meaningful insights from large datasets.2. Multivariable Calculus: Multivariable calculus deals with functions of more than one variable and techniques for studying them, such as partial derivatives, multiple integrals, and vector calculus. Mastering this skill enables a deeper understanding of complex mathematical models and their applications in fields like physics and economics.3. Ethical Hacking: Ethical hacking, also known as penetration testing or white-hat hacking, involves identifying vulnerabilities and weaknesses in computer systems and networks. This skill requires knowledge of various hacking techniques, network protocols, and programming languages like C++ or Python to exploit vulnerabilities safely and secure systems against cyber-attacks.4. Advanced Pilates: Pilates is a system of exercises designed to improvephysical strength, flexibility, and control. Advanced Pilates techniques include mastering complex movements like the flying squirrel, scorpion, or side crow, which require exceptional core strength, balance, and coordination.5. Fluent Public Speaking: Public speaking is a valuable skill, but becoming fluent in it takes practice and refinement. This includes techniques such as mastering persuasive language, effective body language, managing nerves, and engaging with different types of audiences.6. Advanced Chess Strategies: Chess is a game of strategy and tactics, and advanced techniques involve understanding various strategies such as positional play, sacrifices, endgame theory, and deep calculations. These skills enable players to anticipate and plan several moves ahead, making it challenging to master.7. High-Level Musical Instrument Proficiency: Mastering a musical instrument at a high level involves honing technique, sight-reading, improvisation skills, and understanding advanced musical theory and concepts. Achieving mastery often requires years of dedicated practice and study.8. Advanced Yoga Poses: Yoga comprises a range of postures, and advanced techniques involve achieving challenging poses like scorpion, handstand, or one-armed peacock. These advanced poses require exceptional balance, strength, and flexibility, making them difficult to master.9. Expert-level Programming: Becoming an expert programmer involves mastering multiple programming languages, algorithms, data structures, and software development methodologies. Advanced programming skills are essential for building complex software systems and solving intricate technical problems efficiently.10. Professional Level Cooking Techniques: Professional chefs employ advanced cooking techniques like molecular gastronomy, sous vide, or intricate knife skills to elevate their culinary creations. These skills require precise timing, attention to detail, and a deep understanding of ingredients and flavors.。
fdm打印工艺流程英文回答:FDM (Fused Deposition Modeling) is a popular 3Dprinting technology that uses a thermoplastic filament to create objects layer by layer. The process involves several steps, which I will explain in detail.1. Designing the Model:The first step in the FDM printing process is to create a 3D model using computer-aided design (CAD) software. This software allows me to design and customize the object according to my requirements. I can choose the dimensions, shape, and even add intricate details to the model.2. Slicing the Model:Once the design is complete, I need to slice the 3D model into thin layers. Slicing software is used to dividethe model into numerous horizontal layers, each with a specific thickness. This step is crucial as it determines the quality and accuracy of the final printed object.3. Preparing the Printer:Now that I have the sliced model, I need to prepare the 3D printer for the printing process. This involves several tasks such as leveling the build plate, ensuring proper filament loading, and calibrating the printer settings. These steps are essential to ensure the printer operates smoothly and produces high-quality prints.4. Printing the Object:Once the printer is ready, I can start the printing process. The 3D printer heats the thermoplastic filament to its melting point and extrudes it through a nozzle. The nozzle moves along the X, Y, and Z axes, depositing the melted filament layer by layer to create the object. The printer follows the instructions from the sliced model to determine the movement and deposition of each layer.5. Post-Processing:After the printing is complete, there are a few post-processing steps that may be required. This can include removing support structures, sanding the surface for a smoother finish, or applying additional coatings orfinishes to enhance the appearance of the printed object. These steps may vary depending on the specific requirements of the printed object.中文回答:FDM(熔融沉积建模)是一种常用的3D打印技术,它使用热塑性丝材料逐层构建物体。
密码学报 ISSN 2095-7025 CN 10-1195/TNJournal of Cryptologic Research, 2020, 7(6): 799-811 ©《密码学报》编辑部版权所有.E-mail: ***************.cn Tel/Fax: +86-10-82789618SM4算法快速软件实现**基金项目:北京市自然科学基金(4202037); CCF-腾讯科研基金(CCF-Tencent RAGR20200123);国家重点研发计划 (2017YFB1400700);科学研究与研究生培养共建项目(JD 100060630);国家级大学生创新创业训练计划(201910006159, 201910006107)Foundation: Natural Science Foundation of Beijing Municipality (4202037); CCF-Tencent Open Fund (CCF-Tencent RAGR 20200123); National Key Research and Development Program of China (2017YFB1400700); Co-Funding Project of Beijing Municipal Education Commission for Scientific Research and Graduates Training (JD 100060630); National Students 1 Innovation and Entrepreneurship Training Program (201910006159, 201910006107)收稿日期:2019-11-13 定稿日期:2020-01-13张觌气I 华气张习肚王肌刘建伟31. 北京航空航天大学软件开发环境国家重点实验室,北京1001912. 密码科学技术国家重点实验室,北京1008783. 北京航空航天大学空天网络安全工业与信息化部重点实验室,北京1001914. 北京卫星信息工程研究所,北京100086通信作者:郭华,E-mail: *************.cn;张习勇,E-mail: ************************摘要:SM4是对称分组密码国家标准•加解密计算效率是衡量算法实现性能的重要指标,而目前关于SM4软件实现方法方面的研究不多.利用比特切片技术,结合支持单指令多数据(SIMD)的AVX2指令 集,本文提出了一种SM4算法的快速软件优化实现方法,使用256位的YMM 奇存器实现了 SM4算法的256分组数据并行加解密.首先基于已有的选择函数构造了新的选择函数,之后改进了搜索算法,基于新的选择函数和改进的搜索算法化简了 S 盒的逻辑表达式,将实现逻辑表达式所需的逻辑门电路数量由 3000(最简与或式)降至497.在Intel Core I7-7700HQ (Kabylake) @2.80 GHz 处理器上,实现速度达到了 2580 Mbps,同公开文献中的最好结果 1795 Mbps (Intel Core i7-5500U (Broadwell-U) @2.40 GHz)相比,实现效率提高了 43%.基于比特切片技术的软件实现优化方法无需内存或高速缓存查表,因此该方法可抵抗缓存-计时侧信道攻击,从而安全性得到了提升.本文提出的优化方法具有可扩展性,不仅适用于 在X86平台上借助拓展指令集AVX2实现,还可利用RISC 指令集在资源受限,安全性要求高的ARM等嵌入式平台上实现.此外,新的选择函数和搜索算法具有通用性,可用于其它一般逻辑函数的化简.关键词:SM4算法;软件优化实现;比特切片;SIMD 技术中图分类号:TP309.7 文献标识码:A DOI: 10.13868力.cnki.jcr.000407中文引用格式:张笑从,郭华,张习勇,王闯,刘建伟.SM4算法快速软件实现[J].密码学报,2020, 7(6): 799-811.[D0I : 10.13868/ki.jcr.000407]英文引用格式:ZHANG X C, GUO H, ZHANG X Y, WANG C, LIU J W. Fast software implementation ofSM4[J]. Journal of Cryptologic Research, 2020, 7(6): 799-811. [DOI: 10.13868/ki.jcr.000407]Fast Software Implementation of SM4ZHANG Xiao-Cong b3, GUO Hua b2, ZHANG Xi-Yong 4, WANG Chuang 1, LIU Jian-Wei 31. State Key Laboratory of Software Development Environment, Beihang University, Beijing 100191, China2. State Key Laboratory of Cryptology, Beijing 100878, China800Journal of Cryptologic Research密码学报Vol.7,No.6,Dec.20203. Key Laboratory of Aerospace Network Security(Ministry of Industry and Information Technology), Beihang University,Beijing100191,China4. Beijing Institute of Satellite Information Engineering,Beijing100086,ChinaCorresponding author:GUO Hua,E-mail:*************.cn;ZHANG Xi-Yong,E-mail:xiyongzhang@Abstract:The SM4algoiithm is China's national standard of symmetric block cipher,and its efficiency is one of the most important features.So far,insufficient work has been done on fast software implementation of SM4algorithm.Exploiting bit-slicing technique and SIMD(single instruction multiple data)instruction set AVX2,this paper presents a fast implementation of SM4algorithm which can process256blocks in parallel via256bits YMM registers.Firstly,a new selection function is constructed based on existing ones.Then,the logic circuit generating algorithm corresponding to the selection function is improved.Furthermore,the number of gates of the S box is reduced from3000to ing an Intel Core i7-7700HQ(Kabylake)@2.80GHz processor,the software performance is2580 Mbps,43%ahead of SM4's benchmark on software implementation which is1795Mbps(Intel Core i7-5500U(Broadwell-U)@2.40GHz).Bit-sliced implementation does not require to store a table in memory or in cache,hence it is immune to side channel attacks such as cache attack and timing attack. The improved method presented in this paper can be implemented on various computing platforms, which means that it is suitable to X86architecture with extended instruction set AVX2,and is also suitable to embedded systems with RISC instructions and limited resource.Note that the improved selection function and the improved logic circuit generating algorithm are a generic approach,which can be used to the reduction of general logical functions.Key words:SM4;software implementation:bit slicing;SIMD1引言SM4分组密码算法⑴是我国自主设计的对称分组密码,为众多信息系统提供安全、完整的数据加密方案.SM4算法的高效软件实现为我国应用在安全产品(如IPSec、VPN、SSL、TLS等)上的密码算法由国际标准替换为国家标准提供了强有力的支撑,为SM4算法广泛用于政府办公、公安、银行、税务、电力等自主可控要求高的信息系统提供了可靠的保障.目前关于SM4算法的软件优化实现方面的相关工作不多,多使用查表的方法何,但由于代替表规模相对较大,CPU在做查表操作时,表中数据在内存和cache 之间频繁对换导致查表延时较大,且不利于高效并行加/解密多组消息.此外,查表法无法抵抗缓存-计时侧信道攻击,因此在一定程度上制约了SM4的软件实现性能和安全性.1996年Intel推出单指令多数据的SSE(Streaming SIMD Extensions)指令集后,Biham同于1997年提出一种新的对称分组密码快速软件实现方法,核心思想是将处理器视为以1比特为单位的单指令多数据处理器,随后被Matthew Kwan称为比特切片(bit slicing)⑷.比特切片方法在64位平台上实现了64组DES消息的并行加解密,将逻辑门个数从理论上需要的132个每比特输出优化到10()个每比特输岀.之后研究者们对门函数个数进一步进行了优化,使得标准逻辑门(与、或、非、异或)和非标准逻辑门均达到了平均50+个每比特输出.2011年Roman Rusakov同又将门函数的个数降至平均44个逻辑门每比特输岀.比特切片方法可大大提高实现效率,也可用于搜索密钥,对RISC和CISC的指令集平台均适用,且具有更好的安全性.为了提高软件实现速度,国内外许多学者尝试将采用SIMD(Single Instruction Multiple Dada,单指令多数据)技术用于密码算法的软件实现.A.Adomnicai和T.Peyrin何给出改进的比特切片方法“Fixslicing”,在ARM和RISC-V平台实现了AES.2012年Intel推出高级向量指令集(Advanced Vector Extensions,AVX)后,众多学者开始研究如何利用AVX指令集加速对称分组密码算法的实现速度,尤其是轻量级密码算法的实现速度.Seiichi Matsuda和Shiho Moriai卩】利用AVX指令集加速切片实现,给张笑从等:SM4算法快速软件实现801出了轻量级密码算法面向云端的实现,将SSE指令与比特切片方法结合并应用到PRESENT/Piccolo,使两者的实现吞吐量分别达到4.3cycle/byte和4.57cycle/byte.2013年,Neves和Aumasson同将AVX2指令应用到SHA-3候选算法BLAKE上并提高了其实现性能.最近,郎欢等何利用X86架构下的SIMD 指令给出了高效的SM4实现,他们釆用C语言调用AVX2指令接口方式实现,在并行查表的基础上,给出了两种不同的方法.2014年Kostas Papapagiannopoulos等人口°】将比特切片方法修改为nibble切片方法,并减少了访问内存,在AVR处理器上给出了高效实现.此外,研究者们将比特切片方法和其它方法结合,对SM4算法进行软件实现,也取得了较好的效果. SM4算法公布不久,Fen Liu等【切破解了SM4算法S盒的结构,公布了S盒的代数表达式及具体参数值.之后,Hao Liang等问基于已破解的SM4中S盒结构,提出了基于复合域的SM4实现方法,将S 盒的有限域求逆运算变换到复合域中实现,并在FPGA上进行验证.Jingbin Zhang等问提出了SM4在复合域中的软件实现,使用X86架构普通指令实现,速率达到20Mbps.最近,A.Eldosouky和W. Saad")针对物联网应用的效率、安全需求改进了轻量级密码算法LED的比特切片方法,并在嵌入式处理器ARM Cortex-A53进行了实现验证.O.Hajihassani等1151利用比特切片方法进一步提高了高级加密算法AES的加解密吞吐率.总的来说,在国密标准SM4算法的软件优化实现方法取得了一些进展,但和其他对称加密算法如AES相比,SM4的软件优化实现仍需进一步研究.本文利用比特切片方法,结合支持单指令多数据(SIMD)的AVX2指令集,提出了一种SM4算法的快速软件优化实现方法,使用256位的YMM寄存器实现了SM4算法的256分组数据并行加解密.该方法首先对待加密的明文消息通过SIMD版本的数据编排算法进行预处理;之后提出了一种改进的化简逻辑表达式的新方法,将实现逻辑表达式所需的逻辑门电路数量由3000降至497;最后使用反编排算法得到密文.在Intel Core i7-7700HQ(Kabylake)@2.80GHz处理器上,结合x86平台拓展指令集AVX2和上述方法对SM4算法进行软件实现,实现速度达到了2580Mbps.相比于传统的查表实现(Intel Core i7-5500U(Broadwell-U)@2.40GHz)、未优化的比特切片实现(Intel Core i7-5500U(Broadwell-U)@2.40 GHz)、SM4软件优化实现公开文献的最佳结果[9](Intel Core i7-550()U(Broadwell-U)@2.40GHz),新方法的实现效率分别提升了 1.8倍、2.6倍和43%.综上所述,本文主要贡献如下:(1)提出了一种通用的对称分组密码算法的软件优化实现方法,该方法通用于所有对称加密算法的快速软件实现.(2)提出的基于比特切片的软件优化实现方法无需内存或高速缓存查表,因此可抵抗缓存-计时侧信道攻击"1,从而安全性得到了提升.(3)提出的优化方法具有较强的通用性.该方法可用于所有对称加密算法的软件优化实现,并适用于不同的软件架构:在CISC架构平台如X86适合借助SSE、AVX2、AVX512等拓展指令集实现,在RISC架构(ARM,RISC-V)的平台可使用普通指令集实现.(4)新的选择函数和搜索算法具有通用性,可用于一般逻辑函数的化简.本文其余内容组织如下:第2节介绍SM4算法及AVX2指令;第3节介绍新的选择函数及基于选择函数的改进的搜索算法;第4节介绍SM4的基于比特切片和AVX指令的软件优化实现方法;第5节介绍实验结果;第6节总结全文.2预备知识2.1SM4简介SM4算法釆用非平衡Feistel结构"1,分组长度和密钥长度各为128比特,解密算法与加密算法结构相同,区别在于轮密钥使用顺序相反.下面首先介绍SM4的轮函数.设明文输入为(Xo,X“X2,X3)6(Z护)4,密文输出为(Yo,m,⑹€(Z跻丫,轮密钥为rk:6Zf2, 1=0,1,••-,31.SM4加密算法的轮函数F如图1所示.轮函数F每次迭代的输入为(Xi,X,+l,X;+2,X<+3),输出为(X,+l,X,+2,X;+3,尢+4),尢+4的计算方法如下:802Journal of Cryptologic Research 密码学报 Vol.7, No.6, Dec. 2020X :+4 = F(Xi, Xi+i, Xi+2, X :+3)= X : + T(Xi+i + Xi+2 + X+3 + rki)其中,rk.为当前迭代的轮密钥,T 为一个Z/2 t Zf 的可逆变换.T 为一个Zf t Z 舁的可逆变换,由非线性变换T 和线性变换L 复合而成,即T(・)= L(r(-)).非线性变换t 由4个并行的S 盒构成.设输入为A = (ao,ai,a2,a3)€ (Z®)4,输出为B = (feo,&i,&2, &3)€ (Z 寻)4,贝!I :(6(), bi, &3)= r(A) = (Sbox(ao), Sbox(ai), Sbox(a2), Sbox@3))对于每个S 盒的8位输入,前4位作为行,后4位作为列,输岀即为查找表中对应行列所对应的值.S 盒如图2所示.D C B A 95926857E 13F 18O 48O 96A A 389A E 65D B 84C 6C F F D 8851E B A 4692O A 3497C 1B 455B C 3B 6F F 56141C 3C O 5E BF 8C 8852C 68561E 6C 89D 56O 1O 95D D F 85724E 7E 7O A F F O 61B C D 263A 9B B 7E O B 2129EC 24F 143E C 3A 741O 3644F 9B 26739F 9 49EB 45D 5E 23F 92F D 7B E 6A 3O 385C 3D O 31D 591A 388F 24A A C O 1267 73A 5A B 2255O F F D E OB C 79B 8A.5B 5627B 72D 4887A 178A AE C B 7D 3O 9E 1D D 231C 8B 774 1EF 83483746D D D 6QE B E O 765D C 36F D C 9D C A 19 313F O B 2E B 5C AC 29C F 7 69 498D B A O 3E 64 9C 2E 724E 528A CF 7F A F B 55D A 24984E 9A O C 71E 6A D 27F 17DE 951A 8O 485E 3A 397 O 7237B 4OF E 6B B 19O964B O 62O B A F D 1C 6F 6B C 478E 4A O D 5D A 9 8D 29E 461D E E 1D 8O 814 cF C 2 2 29 3 o 7 o F 33A c o 1 F6 5 D F 5图2 SM4代替表Figure 2 Substitution table in SM4 algorithm图1 SM4轮函数Figure 1 Round function in SM4 algorithm L 是线性变换,非线性变换丁的输出是线性变换L 的输入.设输入为B t Z 沪,输出为C t Z 沪,则C = L(B) = B + (£«2) + (£ « 10) + (£ « 18) + (£ « 24)其中,《代表循环左移,如E «2代表循环左移2位.2.2 SIMD 技术及AVX2指令集SIMD (single instruction multiple data)技术可实现同一操作并行处理多组数据.目前支持SIMD技术的处理器厂商主要有Intel. AMD 、ARM 等.目前大多数PC 及服务器采用的是Intel 处理器,而Intel 处理器中的SSE/AVX 指令集采用的正是SIMD 技术.AVX (Advanced Vector Extensions)指令 集1181是256-bit 宽向量指令集,指令操作对象称为YMM 的256-bit SIMD 寄存器.该寄存器内容分为2个128-bit lane. AVX 指令操作对象为lanes,该指令不支持跨越lanes 的操作.AVX2指令集是AVX 指令集的扩展和改进,也称为Haswell New Instructions,支持跨越lanes 的操作.AVX2 支持 8 道 32-bit 整数异或(vpxor)、移位(vpslld),置换(vpermd)、查表(vpgatherdd)等. 2013年Inter 在22 nm Haswell 微架构处理器上正式推出AVX2指令集.表1给出了部分AVX2指令,这些指令可用于对称分组密码的切片实现.3构造新的选择函数及搜索算法“选择函数” 119>是Mattew 为比特切片方法中简化实现S 盒逻辑门电路数量而提出的一种逻辑函数 表达形式.选择函数的思想为二分法,每次分得两个子函数,直至最终分解到的子函数可以直接实现.经研究发现,对于上述特定问题选择函数形式比其他常用的标准形式优越许多.如上所述,对于SM4算法 的S 盒,使用最简与或形式、最简或与形式、最简与或非形式等需要逻辑门数约为3000,而使用己知的3张笑从等:SM4算法快速软件实现803表1相关AVX2指令总结Table1Summary of relevant AVX2instructionsAVX2指令C/C++接口功能描述vpshufhw_mm256_shufflehi_ep订64道64位数据重排vpshuflw_mm256_shufflelo_ep订64道64比特数据重排vpshufd_mm256_shu田e_epi328道32比特数据重排vpermq_mm256_permute4x64_epi644道64比特数据重排vpslld_mm256_slli_epi328道32比特逻辑左移vpsrld_mm256_srli_epi328道32比特逻辑右移vpxor_mm256_xor_si25625&比特逻辑异或vpor_mm256_or_si256256-比特逻辑或vpgatherdd_mm256_load_si256/_mm256_store_si2568道32比特查表vmovdqa_mm256_load_si256/_nim256_store__si256加载/存储256比特数据(要求内存对齐) vmovdqu_mm256_loadu_si256/_mm256_storeu_si256加载/存储256比特数据(不要求内存对齐)个选择函数形式时,可将逻辑门数限制在:N sm4=12+8x(2'+22+---+28-2)=1032.使用本文提出的新的选择函数及改进的搜索算法,可进一步将逻辑门数减至497门.一般来说,使用的选择函数越多,搜索越充分,越能减少逻辑门数量.本节首先基于已有的选择函数构造新的选择函数、之后基于新的选择函数给出改进的搜索算法,最后 介绍如何使用新的选择函数及改进的搜索算法化简S盒的逻辑表达式.3.1选择函数简介为化简比特切片方法中实现S盒所用的逻辑门电路数量,Mattew提出了化简逻辑门电路的算法及“选择函数”的概念.使用选择函数,DES中实现S盒的逻辑门电路数量从平均70门每比特输出被约简到平均45门每比特输岀.设凡为8比特逻辑函数,即F o(abcdefgh),从输入abcdefgh中任选一个比特,记为sei,给岀选择函数基本形式:F o=(Fi and sei)or(F2and not sei)不妨设sei为d,规定:Fi=Fi(abcefgh),F2=F2(abcefgh)由于Fi与F2均唯一存在,从而8比特逻辑函数被分解成7比特逻辑函数,这一过程称为利用“选择函数”的一次选择.Mattew给出了三种“选择函数”表达式:F。
课程基本信息东北大学课程编号课程名称学期学时原课程编号英文名学分理论学时B070110100方法论①24070100581Methodology 11.520B070110110方法论②32070100582Methodology 2232B070120100信号与系统*64070100060Signals & Commu45648070100160Digital Signal 332B070120200数字信号处理基础B070120210数字信号处理*64Digital Signal 452B070120300微机原理与应用*48070300010Computer Princi340B070120400单片机原理及应用56070100120SCM Theory & Ap3.540B070120500可编程逻辑器件E48070100390Programmable Lo332B070120600嵌入式系统技术*48070100680Embedded System340B070120610嵌入式系统技术*64070100680Embedded System448B070130100生物医学电子学48070100170Biomedical Elec33264Biomedical Elec448B070130110生物医学电子学及B070130200生物医学仪器64070100200Biomedical equi432B070140100生产实习64070100540Industrial Inte464B070140200毕业实习16070100550Graduation Prac116B070140300毕业设计(论文)240070100560Graduation Desi15240B070140400电工电子实训32Electronics Pra2056070100495Design Centered3.50B070140500以项目为中心的课56070100494Design Centered3.50B070140600以项目为中心的课B070200020计算机图形学64070100220Computer Graphi432B070200040医学成像技术及系64070100231Medical Image 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Applying Design Intent in SolidWorksSketchingSolidWorks is a powerful 3D CAD software that allows users to create and design complex models and assemblies. One of its fundamental features is the sketching tool, which enables users to create 2D profiles that can be used as a basis for creating 3D models. When sketching in SolidWorks, it is essential to apply design intent, which is a concept that ensures the sketch remains flexible and allows for easy modifications down the line. In this article, we will explore the importance of applying design intent in SolidWorks sketching and discuss various techniques to achieve it.Design intent refers to the idea that a design should capture the essential features and intentions of the final product. It involves creating sketches that are driven by dimensions, relations, and constraints to maintain their shape and behavior as they are modified. By applying design intent, designers can ensure that the sketches can be easily modified and adapted to incorporate design changes without losing their intended functionality.There are several key principles to keep in mind when applying design intent in SolidWorks sketching. First and foremost, it is crucial to define the sketch's purpose and understand how it fits into the overall design. By clearly defining the sketch's purpose, designers can make informed decisions about the dimensions, relations, and constraints needed to achieve the desired outcome.Secondly, it is essential to establish relationships and constraints within the sketch. SolidWorks provides various tools to apply relationships, such as coincident, parallel, tangent, and concentric, which help define the geometry's behavior. These relationships ensure that when modifications are made to the sketch, the desired proportions and connections are maintained.Another important aspect of applying design intent is the proper use of dimensions. Dimensions define the size and location of sketch entities and provide importantinformation for manufacturing and assembly. It is crucial to add relevant dimensions to control the sketch's overall size and proportions effectively.However, it is important not to over-constrain the sketch with excessive dimensions. Over-constrained sketches are difficult to modify and can lead to unintended consequences when making design changes. Instead, designers should focus on using fewer dimensions and leveraging relations and constraints to control the sketch's behavior.In addition to relationships and dimensions, using sketches that are parametrically driven is vital for maintaining design intent in SolidWorks. Parametric sketching allows users to define relationships and mathematical equations between sketch entities, ensuring that modifications made to one aspect of the design propagate through the entire model. This makes it easier to implement design changes throughout the development process.SolidWorks offers a range of advanced sketching tools that designers can use to maximize design intent. These tools include symmetry and pattern constraints, which ensure that changes made to a single entity propagate symmetrically or repeatedly throughout the sketch. By utilizing these advanced techniques, designers can save time and effort when modifying their sketches.Lastly, it is crucial to perform regular checks and validations throughout the sketching process to ensure that design intent has been maintained. SolidWorks provides tools such as the Fully Defined Sketch tool, which helps identify any under-defined or over-constrained sketches. By resolving these issues, designers can ensure that the sketches are flexible and easily modifiable.In conclusion, applying design intent in SolidWorks sketching is essential to create flexible and easily modifiable models. By understanding the purpose of the sketch, establishing relationships and constraints, using dimensions effectively, and leveraging parametric sketching techniques, designers can ensure that their sketches maintain their intended functionality throughout the design process. With the range of advanced sketching tools and validation options provided by SolidWorks, designers can createaccurate and efficient sketches that form the foundation for successful 3D models and assemblies.。
In the realm of international cuisine, pizza holds a special place in the hearts and palates of food enthusiasts worldwide. This versatile dish, with its crispy crust, savory sauce, gooey cheese, and myriad toppings, has become a universal symbol of culinary delight. As an avid home cook, I have embarked on a journey to master the art of crafting the perfect pizza from scratch. This essay delves into the intricate process of making pizza, examining each step in detail, while reflecting on the challenges faced, the skills honed, and the sheer joy derived from this gastronomic endeavor.**Ingredients: The Foundation of Flavor**The quality of a pizza is intrinsically linked to the freshness and authenticity of its ingredients. I begin my pizza-making odyssey by sourcing premium ingredients that meet my high standards. For the dough, I use a blend of high-protein bread flour and Italian '00' flour, which imparts a delicate texture and allows for optimal gluten development. The yeast, either active dry or instant, is carefully selected for its ability to leaven the dough effectively. Salt, sugar, and olive oil complete the dough's basic components, each contributing their unique properties –salt enhances flavor, sugar aids fermentation, and olive oil adds richness and tenderness.For the sauce, I opt for San Marzano tomatoes, renowned for their sweet, low-acidity profile and meaty texture. Fresh basil, garlic, and a pinch of sea salt create a simple yet flavorful base. Cheese selection is paramount; mozzarella, with its mild taste and excellent melting properties, serves as the foundation. I often complement it with grated Parmigiano-Reggiano for a nutty, umami boost and a sprinkle of Pecorino Romano for a sharp, salty edge.Toppings are where creativity reigns supreme. I choose a mix of fresh vegetables (such as bell peppers, mushrooms, and onions), meats (like pepperoni, sausage, or prosciutto), and herbs (basil, oregano, or rosemary) based on personal preferences and seasonal availability. The key is to strike a balance between flavors, textures, and cooking times to ensure each component reaches its optimal state during baking.**Dough Preparation: Artistry Meets Science**Making pizza dough is a delicate dance between art and science. It begins with activating the yeast in a mixture of warm water and sugar, ensuring the environment is neither too hot nor too cold to hinder or accelerate fermentation. Once frothy, the yeast is incorporated into the flour, salt, and olive oil, forming a shaggy mass. Kneading ensues – a rhythmic, meditative process that transforms the rough dough into a smooth, elastic ball.I then allow the dough to rest in a warm, draft-free area for at least an hour, or until it doubles in size. This stage, known as proofing, is crucial for developing the gluten network and infusing the dough with air pockets, which ultimately contribute to the crust's characteristic chewiness and airy texture. After proofing, the dough is gently punched down, divided, and shaped into individual balls, ready for further resting or immediate use.**Shaping and Topping: Translating Vision to Reality**Shaping the pizza dough requires both skill and patience. I prefer the Neapolitan-style, characterized by its thin, slightly puffed edges and soft center. To achieve this, I stretch the dough by hand, rotating it gently while applying outward pressure, until it forms a thin, even circle. Alternatively, I may use a rolling pin for a more uniform thickness, especially when working with a sturdier dough.Once shaped, the pizza is laid on a lightly floured peel or parchment paper, ready for its topping transformation. First comes the sauce, spread evenly but sparingly, leaving a small border for the crust. Next, a generous layer of mozzarella is scattered across the sauce, followed by the chosen toppings. Here, restraint is key – too many toppings can weigh down the crust and hinder even cooking. Finally, a sprinkle of herbs, a drizzle of olive oil, and a dusting of grated cheese complete the picture-perfect pizza.**Baking: The Crucible of Transformation**Baking pizza is where the magic truly happens. I use a preheated oven, preferably with a pizza stone or steel, to achieve a crispy, evenly cooked crust.The high heat (around 450-500°F or 230-260°C) mimics the intense heat of a traditional wood-fired oven, allowing the pizza to cook rapidly, sealing in moisture and creating those sought-after leopard spots on the crust.The pizza is slid onto the heated surface and baked for 8-12 minutes, depending on the oven and desired level of doneness. Monitoring the pizza closely during this stage is essential, as the difference between perfectly cooked and overcooked can be mere seconds. Once the crust is golden brown, the cheese melted and bubbly, and the toppings caramelized to perfection, the pizza is removed from the oven and allowed to rest for a minute or two. This resting period allows the cheese to set slightly, making slicing and serving easier.**Reflections and Learnings**My journey towards mastering pizza-making has been a gratifying blend of trial, error, and triumph. Each time I roll out the dough, I am reminded of the importance of patience, precision, and adaptability in the kitchen. I have learned to appreciate the nuances of different flours, the transformative power of fermentation, and the delicate balance between toppings. Moreover, I have discovered that the best pizzas are not just about technique or ingredients, but also about the joy of sharing a homemade meal with loved ones.Pizza-making has also taught me the value of sustainability and seasonality. By using locally sourced, organic produce and minimizing food waste, I contribute to a more eco-friendly culinary practice. Additionally, experimenting with seasonal toppings encourages creativity and fosters a deeper connection to the rhythms of nature.In conclusion, crafting the perfect pizza is a multifaceted endeavor that combines culinary expertise, artistic vision, and a deep appreciation for the transformative power of heat. From selecting high-quality ingredients to skillfully shaping the dough, thoughtfully layering toppings, and expertly baking the pie, each step is a testament to the artistry and science behind this beloved dish. As I continue to refine my pizza-making skills, I am constantly reminded that the true essence of this culinary journey lies not only in thefinal product but also in the joy of creation, the satisfaction of self-reliance, and the warmth of sharing delicious food with others.。
外文文献资料(外文文件名:JSP Splitting for Improving ExecutionPerformance)AbstractSplitting a JSP (Java Server Pages) page into fragments can improve the execution performance of JSP pages when the Web application server can separately cache the Web page fragments obtained by executing the JSP fragments. If a JSP page is split into fragments according to the update frequency of each portion of the Web page obtained by executing the JSP page, all of the split JSP fragments do not need to be executed again when only a single cached part of a Web page expires. In addition, the fragments of a JSP page can be reused by other JSP pages. In both cases, the execution results of all of the JSP fragments split from the JSP page must be the same as from the JSP page before it was split. In this paper, we propose JSP splitting, which is a method of splitting a JSP page into fragments maintaining the data and control dependences existing in the original JSP page. JSP splitting automatically detects the portions needed to maintain the data and control dependences of a JSP page for the portions that developers want to split from the JSP page. We implemented JSP splitting with a GUI tool, and confirmed that the split JSP fragments were executed in the same as the way as the JSP page before the split. Experimental results show that the response time to access a Web page can be reduced by splitting a JSP page into fragments and setting different caching periods for the Web page fragments obtained by executing the JSP fragments.1. IntroductionSplitting a JSP (Java Server Pages) page into fragments can improve the execution performance of some JSP pages when the Web application server can separately cache the Web page fragments obtained by executing the fragments of the JSP page. The period of caching dynamic Web pages generated by a JSP engineis limited due to the dynamic nature of the content. When the cached content of a Web page generated by a JSP engine is updated, the entire JSP page must be executed again on the application server, even though the change of the Web page might be small. Since frequent updates of cached Web pages increase the load on an application server, it is reasonable to split a JSP page into fragments and set different caching periods for the Web page fragments obtained by executing the JSP fragments. Of course, the Web page fragments must be merged into a final Web page correctly. The Dynacache technology of IBM WebSphere Application Server allows Web page fragments to have different caching periods. Cache tag libraries provided by the Apache Jakarta Project also support different caching periods for the JSP fragments. In addition, ESI (Edge Side Includes) technology provides a mechanism to cache Web page fragments with different caching periods, and to merge them into a final Web page on an edge server.The application offload technology of IBM WebSphere Edge Server is another approach to improve the execution performance of JSP pages. This technology allows one or more JSP fragments to be cached and executed on edge servers. The remaining JSP fragments are deployed on the application server and are called by the JSP fragments executed on the edge server. Thus, some of the execution of a JSP page is offloaded to the edge server.Splitting a JSP page facilitates the reuse of JSP fragments. When a Web application consists of many JSP pages, the same portions tend to exist in many JSP pages. Examples are the frames, the banners, the headers, and etc.When a JSP page is split into fragments, the total execution result of all of the fragments must be the same as the JSP page before it was split. In addition, when the fragments of a JSP page are executed in different servers, each fragment needs to be executed without the other fragments. In order to satisfy these conditions, we propose JSP splitting, which is the method of splitting a JSP page into fragments described in this paper. Since it is very difficult to automatically find the best way to split a JSP page into fragments for some particular purpose, we assume that the developers will select the portions that they want to split into fragments. In order to execute all of the divided JSP pages correctly, JSP splitting automatically detects any portions that must be moved or copied into a fragment with the selected portions. The detection is done based on the analysis of the data and controldependences existing in a JSP page. JSP splitting is similar to the program slicing technique that slices a program based on the data and the control dependences. However, the program slicing technique does not take into account that the sliced programs are executed independently and that the total execution result of the sliced programs must be the same as the program before the division. In addition, since data is passed to the JSP engine during the execution of JSP pages, the source program of the JSP engine, such as Apache Tomcat, is required in order to analyze the data dependences correctly. This is impractical, because the source program of the JSP engine is very large and complex. JSP splitting avoids the analysis of the JSP engine by utilizing the characteristics of JSP.The rest of the paper is organized as follows. Section 2 explains the difficulty of splitting a JSP page into fragments. Section 3 gives details of the algorithmto split a JSP page. Section 4 describes the JSP splitting tool that is an implementation of JSP splitting and demonstrates how a sample JSP page is split by the tool. Section 5 shows the experimental results obtained by executing the split JSP fragments with different caching periods on the IBM WebSphere Application Server. Section 6 discusses previous work in relation to our contributions. Our conclusions form the final section.2. Difficulty of Splitting a JSP PageIn this paper, splitting a JSP page means that some portions of the JSP page are cut from the JSP page and saved as new JSP pages. Such newly created JSP pages are included in the original JSP page by using some mechanism such as the jsp: include tag. We call the included JSP page the JSP fragment, and call the JSP page that invokes the JSP fragments the master JSP page. A master JSP page invokes JSP fragments and receives Web page fragments obtained by executing them. Then the master JSP page merges its own Web page fragment with the Web page fragments received from the JSP fragments, and creates a final Web page.JSP fragments are not always executed in the same server or at the same time. The application offload technology allows a master JSP page and JSP fragments to be executed in different servers. When the ESI mechanism is used, esi: include tags are put into a Web page fragment obtained by executing a master JSP page andinterpreted in an edge server that supports the ESI mechanism. In this case, the edge server checks whether or not the Web page fragments specified by esi:include tags exist in its cache. If the contents of Web page fragments are not cached or have expired, the JSP fragments are invoked from the edge server, and executed in one or more application servers. If different caching periods can be given to the Web page fragments obtained by executing the JSP fragments, each JSP fragment is executed only when the cached content has expired. The Dynacache technology, the ESI mechanism, and the cache tag libraries can support different caching periods for Web page fragments.When a JSP page is split into fragments, the following two conditions must be satisfied even if the master JSP page and the JSP fragments are not executed in the same server or at the same time.Cond. 1 - 1The total execution result of a master JSP page and the JSP fragments is the same as the JSP page before it was split.Cond. 1 - 2Each JSP page, which is either a master JSP page or a JSP fragment, may be executed without other JSP pages.These conditions are satisfied by maintaining the data and control dependences existing in a JSP page after the JSP page has been split into fragments. However, it is hard work for developers to detect data and control dependent portions in a JSP page, because the data and control flow of a JSP page can be divided among the JSP page, the JSP engine that executes the JSP page, any Java beans used in the JSP page, and etc.. Thus, a natural solution calls for automatically detecting data-dependent and control-dependent portions linked to the portions that developers want to split.The program slicing technique detects a set of program statements that affect a program statement S by analyzing the data and control dependences existing in the program. One program slice consists of the detected set of program statements and the statement S. This technique is useful when debugging or maintaining large programs. Since JSP pages are compiled into servlet programs by using a JSP compiler such as the Apache Jasper compiler [4], JSP slices can be obtained by applying program slicing technique to a servlet program compiled from a JSP page. However, the program slicing technique is not sufficient to split a JSP page into fragments, because the technique does not take into account that program slices areexecuted independently.Figure 1 shows a part of a sample JSP page and a sample servlet program compiled from the JSP page. Figure 2 (a) shows the data dependence graph obtained from the servlet program. In a program, when a statement S1 assigns a value to a variable and a statement S2 following S1 uses that value, a true data dependence exists between S1 and S2. Such a data dependence is denoted as S1 →S2. In Figure 2 (a), due to the data dependences, the program slice for the statement S10 consists of S1, S9, and S10. If the program slice is cut from the servlet program, the remaining program statements have errors because the data dependences S1 →S2, S11, and S12 and S9 → S11 and S12 are not honored. Thus, the program slicing technique does not work well for splitting JSP pages.3. JSP SplittingIn this paper, we propose JSP splitting, a method of splitting a JSP page into fragments. The proposed method analyzes data and control dependences in the servlet program compiled from a JSP page. At the time of analysis, JSP splitting takes into account that split JSP pages will be executed independently, and may not be executed in the same server or at the same time. First, the portions that developers want to split into a JSP fragment are selected. For the selected portions, the portions needed to satisfy the conditions 1 - 1 and 1 - 2 are detected. The detected portions are categorized into moved and copied portions, and are minimized in order to match the intentions of the developers.3.1. Ignorable Data DependencesBasically, JSP splitting does not allow the dependent statements to be split apart. However, if this rule is applied too strictly, none of the statements shown in Figure 1 (b) can be split, because there are interlocking dependences starting from S1 and S9.Here, we consider how the variable out shown in Figure 1 (b) is used. The variable out is used to write the text data of any Web page. Note that the value of out can be retrieved from any JSP engine. When a master JSP page JM includes a JSP fragment JF by using a jsp:include tag and a JSP engine executes both of them, JM first retrieves the value of out from the JSP engine and writes its own text data to the value. Next, J M invokes J F. After being invoked, J F also retrieves the value of out and writes its own text data to the value. The text data written by J M is returned to out through the JSP engine and merged with the text data written by J M. This means that the value of out can be utilized by any JSP page and the text data written to the value is maintained by the JSP engines. In other words, when a JSP page is split into fragments, a statement that retrieves the value of out can exist both in a servlet program compiled from a master JSP page and in servlet programs compiled from JSP fragments. Therefore, the data dependences for the variable out can be ignored at the time of splitting a JSP page.As shown in Figure 2 (a), none of the statements can be split while maintaining the data dependences existing in the servlet program shown in Figure 1 (b). However, if the data dependences for the variable out are ignored, the datadependence graph is changed as shown in Figure 2 (b). Using the data dependence graph shown in Figure 2 (b) makes it possible to split S2 from the set of S9, S10, S11, and S12 which cannot be split due to the data dependences for the variable book.In servlet programs compiled by the Apache Jasper compiler, the data dependences for the variables shown in Table1 can be ignored for the same reason as for the variable out.Since the values of these variables are defined at the top of each servlet program and are frequently referred to, most statements cannot be split if the data dependences are to be maintained.In general, the out-of-order execution is allowed for the statements without data and control dependences. Ignoring the data dependences for the variables shown in Table 1 may introduce an incorrect execution order of statements. For example,if S10 and S12 shown in Figure 1 are split into a JSP fragment and the JSP fragment is included before S11, an incorrect Web page is generated. In order to avoid such incorrect execution, our algorithm does not allow changes in the order of the statements that have ignored data dependences.3.2. Analysis of Data Dependences for Java beansIn a JSP page, Java beans are frequently used to store and retrieve data as property values. Each Java bean is a Java object and developers can use Java beans by using three kinds of tags in a JSP page.● jsp:useBean: Declares a named Java bean with its scope. When an object forthe Java bean does not exist within the declared scope, the bean is instantiated. Java beans can be declared with the scope of page, request,session or application.● jsp:getPrope rty: Calls the get method of a Java bean object and retrieves the property value.● jsp:setProperty: Calls the set method of a Java bean object and sets the property value.Java beans must be declared with the jsp:useBean tag before the other two operations. This means that a declaration of a Java bean and all of the other operations for the Java bean must be included in the same JSP page. This strongly limits the extent of a JSP fragment. In order to relax the limitation, JSP splitting allows declarations of Java beans to be copied to JSP fragments. The reason why declarations of Java beans can be copied is that the declarations do not have side effects. Each declaration merely instantiates a Java bean object when the Java bean object has not yet been instantiated within its scope. In other words, a Java bean object is not instantiated more than one time within its scope even if the declaration is copied to JSP fragments. Therefore, some of the operations for a Java bean can be split into fragments.When a property value is set for a Java bean by using a jsp:setProperty tag and retrieved from the JSP bean by using a jsp:getProperty tag, a true data dependence exists between the two operations.When the rule that data dependent statements cannot be split is applied, data dependent operations for a Java bean must be included in the same fragment. However, a data dependence between an operation that sets a property value for a JSP bean and another operation that retrieves the property value is maintained after the two operations are split if the following two conditions are satisfied.Cond. 2 - 1The scope of the Java bean is ”request”, ”session”, or ”application”. Cond. 2 - 2 The split JSP pages are executed in the same JSP engine.If these conditions are satisfied, JSP splitting allows the operations among which the data dependences exist to be split into different JSP pages, because the Java bean lives in the JSP engine during the execution of the split JSP pages. As a result, the portions split along with the portions selected by a developer can be reduced. However, the Web page fragments obtained by executing the split JSP pages satisfying these conditions must have the same caching period. This is because thedata dependence is not maintained if a JSP page was executed and a value is defined in the JSP page while another JSP page, in which the defined value is used, was not executed due to the valid cached content of the Web page.When a Java bean has the page scope, the dependent operations for the Java bean cannot be split. However, each operation that sets a property value for a Java bean with the page scope can be copied along with one or more operations that retrieve the same property value, because the operations that set property values for Java beans with the page scope do not have side effects.Figures 3 to 6 show the algorithms to split the operations for Java beans. These algorithms try to minimize the number of the operations that are moved or copied to a JSP fragment.4. JSP Splitting ToolWe implemented JSP splitting as a plug-in for Eclipse。
Rectilinear Block Placement Using B*-TreesGUANG-MING WUNan-Hua UniversityYUN-CHIH CHANGRealtek Semiconductor Corp.andY AO-WEN CHANGNational T aiwan UniversityDue to the layout complexity in modern VLSI designs,integrated circuit blocks may not be rect-angular.However,literature on general rectilinear block placement is still quite limited.In this article,we present approaches for handling the placement for arbitrarily shaped rectilinear blocks using B*-trees[Chang et al.2000].We derive the feasibility conditions of B*-trees to guide the placement of rectilinear blocks.Experimental results show that our algorithm achieves optimal or near-optimal block placement for benchmarks with various shaped blocks.Categories and Subject Descriptors:B7.2[Integrated Circuits]:Design Aids—placement and routing;J.6[Computer Applications]:Computer-Aided EngineeringGeneral Terms:Algorithms,Design,Experimentation,Measurement,PerformanceAdditional Key Words and Phrases:Computer-aided design of VLSI,floorplanning,layout, placement1.INTRODUCTIONDue to the growth in design complexity,circuit size is getting larger.To cope with the increasing design complexity,hierarchical design and IP modules are widely used.This trend makes blockfloorplanning/placement much more critical to the quality of a design.Floorplanning is often studied based on twofloorplan structures,the slicing structure[Otten1982;Wong and Liu1986]and the nonslicing structure[Chang The work of G.-M.Wu was partially supported by the National Science Council of Taiwan ROC under Grant No.NSC-91-2215-E-343-001.The work of Y.-W.Chang was partially supported by the National Science Council of Taiwan ROC under Grant No.NSC-91-2215-E-002-038.Authors’addresses:G.-M.Wu,Department of Information Management,Nan-Hua University, Chiayi,Taiwan;email:*************.edu.tw;Y.-C.Chang,Realtek Semiconductor Corp.,No.2, Industry E.Rd.IX,Science-Based Industrial Park,Hsinchu,Taiwan;Y.-W.Chang,Graduate In-stitute of Electronics Engineering and Department of Electrical Engineering,National Taiwan University,Rm.548,Electrical Engineering Building#1,Taipei106,Taiwan;email:ywchang@ .tw.Permission to make digital/hard copy of part or all of this work for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage,the copyright notice,the title of the publication,and its date appear,and notice is given that copying is by permission of the ACM,Inc.To copy otherwise,to republish,to post on servers, or to redistribute to lists,requires prior specific permission and/or a fee.C 2003ACM1084-4309/03/0400-0188$5.00ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April2003,Pages188–202.Rectilinear Block Placement Using B*-T rees•189 et al.2000;Guo et al.1999;Murata et al.1997;Nakatake et al.1996;Wang and Wong1990].A slicing structure can be represented by a binary tree whose leaves denote modules,and internal nodes specify horizontal or vertical cut lines.Wong and Liu[1986]proposed an algorithm for slicingfloorplan design. They presented a normalized Polish expression to represent a slicing structure, enabling the speedup of the search procedure.However,this representation can-not handle nonslicingfloorplans.Recently,researchers have proposed several representations for nonslicingfloorplans,such as the sequence pair[Murata et al.1997],bounded slicing grid(BSG)[Nakatake et al.1996],O-tree[Guo et al.1999],and B*-tree[Chang et al.2000].In modern VLSI design,the blocks may not be rectangular.Most existing floorplanning/placement algorithms,however,only deal with rectangles and cannot apply to arbitrarily shaped rectilinear block placement directly.New approaches that can handle arbitrarily shaped blocks are essential to optimize resource(e.g.,area)utilization.Preas and van Cleemput[1979]proposed a graph model for the topological re-lationships among rectangular and arbitrarily shaped rectilinear blocks.Wong and Liu[1987]extended the Polish expression to represent slicingfloorplans with rectangular and L-shaped blocks.Lee[1993]extended the zone refinement technique to rectilinear blocks.A bounded2-D contour searching algorithm was proposed tofind the best position for a block.Kang and Dai[1997]proposed a BSG-based method to solve the packing of rectangular,L-shaped,T-shaped,and soft blocks.The algorithm combined simulated annealing and a genetic algorithm for general nonslicingfloorplans.Xu et al.[1998]presented an approach extending the sequence-pair approach for rectangular block placement to arbitrarily sized and shaped rectilinear blocks.The properties of L-shaped blocks were examinedfirst,and then arbi-trarily shaped rectilinear blocks were decomposed into a set of L-shaped blocks.Kang and Dai[1998]proposed a method based on the sequence-pair structure for rectilinear block placement.Three necessary and sufficient conditions for a sequence pair to be feasible were derived.A stochastic search was applied on the optimization of convex blockfloorplanning.Chang et al.[2000]recently proposed the B*-tree representation for nonslic-ingfloorplans,which is based on block compaction and ordered binary trees. Inheriting from the nice properties of ordered binary trees,B*-trees are very easy to implement and require only constant time for tree search and insertion, and linear time for deletion.Unlike the O-tree representations,in particular, no extra encoding of the tree itself is needed for a B*-tree,and cost evalua-tion can be performed directly on a B*-tree.Besides,the ordered property of a B*-tree makes the incremental cost evaluation of its corresponding placement possible.Furthermore,given a B*-tree,it takes only linear time to construct the placement,and vice versa.All these nice properties make the B*-trees an efficient andflexible representation for nonslicingfloorplans.In this article,we apply the B*-tree to handle the placement of arbitrarily shaped rectilinear blocks.First,we explore the properties of L-shaped blocks and then extend the properties to general rectilinear blocks.The feasibility con-ditions are then used to guide the placement of rectilinear blocks.We construct a ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April2003.190•G.M.Wu et al.Top profile sequence = (4, [5, 7], [7, 4], [6, 1], [8, 4])Fig.1.The top profile sequence consists of the length of the base,followed by a sequence of two-tuples that is composed of the lengths of the succeeding horizontal segments and their relative heights to the base.set of benchmarks with rectangular and L-shaped(and T-shaped)blocks and ap-ply simulated annealing as a vehicle to test the effectiveness of our approaches. Experiment results show that our approaches lead to placements with optimal or near-optimal area utilization.The remainder of this article is organized as follows.Section2formulates the rectilinear block placement problem.Section3introduces the B*-tree repre-sentation.Section4describes the method for the L-shaped blocks in a B*-tree. Section5describes our algorithm.Section6extends the algorithm to arbitrar-ily rectilinear blocks.Experimental results are reported in Section7.Finally, we give conclusions in Section8.2.FORMULATIONLet B={b1,b2,...,b n}denote a set of rectilinear blocks.A block is notflex-ible in its shape but free to rotate andflip.A packing of a set of blocks is a nonoverlapping placement of the blocks.A rectilinear block can be represented by four profile sequences,namely,the top profile sequence,the bottom profile sequence,the left profile sequence,and the right profile sequence,specifying the profiles viewed from the top side,the bottom side,the left side,and the right side of the block,respectively.The top (bottom)profile sequence of a rectilinear block uses the leftmost horizontal segment on the top(bottom)boundary of the block as a base and records the length of the succeeding horizontal segments on the top(bottom)boundary and the relative height.Specifically,the top profile sequence consists of the length of the base,followed by a sequence of two-tuples composed of the lengths of the succeeding horizontal segments and their relative heights to the base(could be negative).For example,Figure1shows a rectilinear block with the top profile sequence(4,[5,7],[7,4],[6,−1],[8,4]).The base of the sequence is segment a which has a length of4units.The second horizontal segment is c which has a length of5units and is7units higher than the base a.Similarly,the third horizontal segment is e which has a length of7units and is4units higher ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April2003.Rectilinear Block Placement Using B*-T rees•191(a)01b b b b b b b b (0, 0)x y 23456b 780123678(b)n 4n n 5n n n n n n Fig.2.An admissible placement and its corresponding B*-tree.than the base a ,and so on.The other three profile sequences are similarly defined.Definition 1.A rectilinear block placement is feasible if and only if no two blocks overlap each other,and all profile sequences remain unchanged after placement (i.e.,all blocks keep their original shapes).The goal of the rectilinear placement problem is to optimize a given cost metric (such as area,wirelength,etc.)induced by the assignment of b i s.(By area here,we mean the final enclosing rectangle of B .)3.OVERVIEW OF THE B*-TREE REPRESENTATIONGiven an admissible placement P ,we can represent it by a unique (horizontal)B*-tree T [Chang et al.2000].(See Figure 2(b)for the B*-tree representing the placement shown in Figure 2(a).)A B*-tree is an ordered binary tree whose root corresponds to the module in the bottom-left corner.Similar to the depth-first search (DFS)procedure,we construct the B*-tree T for an admissible placement P in a recursive fashion.Starting from the root,we first recursively construct the left subtree and then the right subtree.Let R i denote the set of modules located on the right-hand side and adjacent to b i .The left child of the node n i corresponds to the lowest module in R i that is unvisited.The right child of n i represents the first module located above and visible from b i ,with its x -coordinate equal to that of b i (and its y -coordinate less than or equal to that of the top boundary of the module on the left-hand side and adjacent to b i ,if any ,to consider the special placement).As shown in Figure 2,we make n 0the root of T since b 0is in the bottom-left corner.Constructing the left subtree of n 0recursively ,we make n 4the left child of n 0.Since the left child of n 4does not exist,we then construct the right subtree of n 4(which is rooted by n 5).The construction is recursively performed in the DFS order.After completing the left subtree of n 0,the same procedure applies to the right subtree of n 0.Figure 2(b)illustrates the resulting B*-tree for the placement shown in Figure 2(a).The construction takes only linear time.ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April 2003.192•G.M.Wu et al.old contournew contourFig.3.A contour and its update:when adding a new block to the placement,we search the contour from left to right and update it with the top boundary of the new block.The B*-tree keeps the geometric relationship between two modules as fol-lows.If node n j is the left child of node n i,module b j must be located on theright-hand side and adjacent to module b i in the admissible placement;thatis,x j=x i+w i.Besides,if node n j is the right child of n i,module b j must be located above and visible from module b i,with the x-coordinate of b j equalto that of b i;that is,x j=x i.Also,since the root of T represents the bottom-left module,the x-and y-coordinates of the module associated with the root (x root,y root)=(0,0).A contour structure(see Figure3),which was originally proposed in Guo et al.[1999],can be used to reduce the run-time offinding the y-coordinate of a newlyinserted block.The contour structure is a doubly linked list of blocks,whichdescribes the contour line in the current compaction direction.Without thecontour structure,the run-time for placing a new block is linear to the numberof blocks.By maintaining the contour structure,however,the y-coordinate ofa block can be computed in O(1)time.Figure3illustrates how to update thecontour when we add a new block to the placement.4.L-SHAPED BLOCKSIn this section,we apply the B*-tree approach tofind a feasible placement withL-shaped blocks.Let b L denote an L-shaped block.b L can be partitioned intotwo rectangular subblocks by slicing b L along its middle vertical boundary.Asshown in Figure4(a),b1and b2are the subblocks of b L,and we say b1,b2∈b L.After partitioning and placement,the rectilinear block b L might not conformto its top profile sequence,as illustrated in Figure5.Figure5(a)shows a B*-tree and its corresponding placement.We can pull subblock b2up to align withthe subblock b1,so that the block b L can maintain its top profile sequence with-out changing the overall topology of the blocks.Conversely,there might not beenough space to do so;see Figure5(b)for such an example.It is obvious thata feasible placement can be generated from the B*-tree shown in Figure5(a)with a local adjustment,but it is impossible for the case shown in Figure5(b).Therefore,if we represent an L-shaped block by two subblocks,we must guar-antee that the two subblocks abut.To ensure that the left subblock b1and the ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April2003.Rectilinear Block Placement Using B*-T rees •193(a)(b)(c)(d)(e)(f)(g)(h)b1b2b2b2b2b2b1b1b1b1b1b1b1b2b2b2Fig.4.Eight situationsof an L-shaped block.Each is partitionedinto two parts by slicing it along the middle vertical boundary .(b)Fig.5.Placing the L-shaped block shown in Figure 4(a)by two subblocks:(a)a feasible placement;(b)an infeasible placement.right subblock b 2of an L-shaped block b L abut,we impose the following location constraint (LC for short)for b 1and b 2.LC :Keep b 2as b 1’s left child in the B*-tree.The LC relation ensures that the x -coordinate of the left boundary of b 2is equal to that of the right boundary of b 1.For example,the two sets of subblocks b 1,b 2and b 3,b 4shown in Figure 6(a)do not abut whereas those shown in Figure 6(b)ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April 2003.194•G.M.Wu et al.Fig.6.Suppose that b1,b2and b3,b4are two sets of subblocks corresponding to two L-shaped blocks(a)a placement in which b1,b2and b3,b4do not abut.Their corresponding nodes in the B*-tree may not be related;(b)another placement in which b1,b2and b3,b4abut.Their corresponding nodes in the B*-tree keep the LC relation between b1and b2(as well as b3and b4).do.In Figure6(b),the subblocks b3and b4are placed at the right locations and the subblocks b1and b2are not since the y-coordinates of b1and b2are not equal.We say b1and b2are misaligned.In the following,we adopt the contour data structure to solve the misalign-ment problem.When transforming a B*-tree to its corresponding placement, we update the contour to maintain its top profile sequence as follows.Assume that b1and b2are the respective left and right subblocks of an L-shaped block b L,and they are misaligned.When processing b2,b1must have been placed.We can classify the misalignment into categories and adjust them as follows. (1)Basin:The contour is lower than the top profile sequence at the positionof the current subblock b2.(See Figure7(a).)In this case,we pull b2up to conform to the top profile sequence of the L-shaped block b L.It should be noted that this operation will not pull other blocks up due to the DFS packing order induced by the B*-tree.(2)Plateau:The contour is higher than the top profile sequence at the positionof the current subblock b2.(See Figure7(b).)In this case,we pull b1up to conform to the top profile sequence of b L.(Note that b2cannot be moved down because the compaction operation makes b2be placed right above another block.)It is clear that each of the adjustments can be performed in constant time with the contour data structure.In the following,we discuss the rotation andflip operations of an L-shaped block.For each L-shaped block b i,there are eight orientations by rotation and ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April2003.Rectilinear Block Placement Using B*-T rees•195(a)(b)Fig.7.Placing two subblocks b1and b2of an L-shaped block:(a)if the contour is lower than the top profile sequence at b2,then we pull b2up to meet the top profile sequence;(b)if the contour is higher than the top profile sequence at b2,then we pull b1up to meet the top profile sequence.flip,as shown in Figure4.To preserve the LC relation and keep it in the B*-tree, we repartition b i into two subblocks after it is rotated orflipped and keep the LC relation between them.Figure4shows the subblocks after repartitioning. As shown in thefigure,an L-shaped block is always partitioned by slicing it along the middle vertical boundary.After repartitioning,we should update the top profile sequence for the block.5.FLOORPLAN ALGORITHMOur rectilinearfloorplan design algorithm is based on the simulated annealing method[Kirkpatrick et al.1983;Sechen and Sangiovanni1985]and the B*-tree described in Section3.We perturb a B*-tree(a feasible solution)to another B*-tree by using the following four operations.Op1:Rotate a block.Op2:Flip a block.Op3:Move a block to another place.Op4:Swap two blocks.The Op1and Op2operations have been described in Section4.The Op3opera-tion deletes and inserts a block into a B*-tree.If the deleted node is associated with a rectangular block,we simply delete the node from the B*-tree.Other-wise,there will be two nodes associated with an L-shaped block,and we must delete the two nodes from the B*-tree and insert them in other places.Note that the LC relations must hold.Both of the Op3and Op4operations need to apply the Insert(n i)and Delete(n i)operations,where Insert(n i)(Delete(n i))is the operation for inserting(deleting)a node n i to(from)a B*-tree.The B*-tree must remain a binary tree after deletion or insertion.We detail the deletion and insertion operations in the following.5.1DeletionThe deletion can be categorized into these cases:—Case1:A leaf node;—Case2:A node with one child;—Case3:A node with two children.ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April2003.196•G.M.Wu et al.Fig.8.Deletion:(a)deleting a leaf node;(b)deleting a node with only one child;(c)deleting a node with two children.In Case1,we can just delete the target leaf node directly,and the tree will still be a B*-tree.As shown in Figure8(a),to delete the node n7from the B*-tree of Figure2,we set the left childfield of its parent n6to be NULL and free the node n7.In Case2,we remove the target node and then place the single child at the position of the removed node.For example,after deleting the node n4from the B*-tree of Figure2,we move n5to the original position of n4and obtain the tree shown in Figure8(b).This tree update can be performed in O(1)time. Note that the relative positions of the blocks might be changed after the op-eration,and thus we might need to reconstruct a corresponding placement for further processing.In Case3,when deleting a target node n t with two children,we replace n t by either its right child or left child n c.Then we move a child of n c to the original position of n c.The process proceeds until the corresponding leaf node is handled.For instance,suppose that we delete the node n0from the B*-tree of Figure2.We can use the right child n1to replace it,and then use n3to replace n1.(The resulting tree is shown in Figure8(c).)It is obvious that such a deletion operation requires O(h)time,where h is the height of the B*-tree.Again the ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April2003.Rectilinear Block Placement Using B*-T rees•197Fig.9.The inseparable,internal,and external positions of a B*-tree.(Assume that n1and n2 are associated with the same L-shaped block.)A node can be inserted at either an internal or an external position.relative positions of the blocks might be changed after the operation,and thus we might need to reconstruct a corresponding placement for further processing.Note that if the deleted node n i is a subblock of an L-shaped b L,we should also delete the other subblock of b L.5.2InsertionWhen adding a block to a placement,we may place the block around a certain block,but not between two subblocks that belong to an L-shaped block.For a B*-tree,we define three types of positions as follows.(See Figure9for an illustration.)—Inseparable position:A position between two nodes associated with the two subblocks of an L-shaped block.—Internal position:A position between two nodes in a B*-tree,but not an inseparable one.—External position:A position pointed to by a NULL pointer.Only internal and external positions can be used for inserting a new node.For a rectangular block,we can insert it into an internal or an external position directly.For any L-shaped block b L consisting of two subblocks b1and b2,with b1on the left-hand side of b2,the two subblocks must be inserted into a B*-tree simultaneously,and b2must be the left child of b1(according to the LC relation).In the following,we discuss three cases of inserting an L-shaped block into an internal position.As shown in Figure10,if we insert two nodes b1and b2of an L-shaped block into an internal position between nodes b i and b j,with b j being a child of b i,b j can be placed at the position that is the left child of b2, the right child of b2,or the right child of b1.ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April2003.198•G.M.Wu et al.(a)(d)Fig.10.Three cases of inserting an L-shaped block to an internal position.b1b2b3b4b5b6b7(a)b1b2b3b4b5b6(b)Fig.11.(a)Partition a convex block along every vertical boundary from left to right;(b)repartition the block of (a)after it rotates.6.EXTENSION TO GENERAL RECTILINEAR BLOCKSIn this section,we extend the techniques described in previous sections to han-dle general rectilinear blocks.In general,a rectilinear block can be partitioned into a set of rectangular subblocks.Let b i denote an arbitrarily shaped rectilin-ear block.b i can be partitioned into a set of rectangular subblocks by slicing b i from left to right along every vertical boundary of b i ,as shown in Figure 11(a).After perturbing the Op1and Op2operations,we repartition a recti-linear block when it is rotated or flipped.Figure 11(b)shows the block of ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April 2003.Rectilinear Block Placement Using B*-T rees•199Fig.12.Filling approximation for a rectilinear block.Figure11(a)after rotating90◦clockwise;there are six subblocks in it after the repartition.There are two types of rectilinear blocks:convex and concave.A rectilinear block is convex if any two points within the block can be connected by a shortest Manhattan path that also lies within the block;the block is concave,otherwise. Figures11and12show two convex and a concave block,respectively.A convex block b C can be partitioned into a set of subblocks b1,b2,...,b n ordered from left to right.Considering the LC relation,we keep the subblock b i+1as b i’s left child in the B*-tree to ensure that they are placed side by side along the x-direction, where1≤i≤n−1.To ensure that b1,b2,...,b n are not misaligned,we modify the processing for Basin and Plateau as follows.—Basin:The contour is lower than the top profile sequence at the position of a subblock.We pull the subblock up to conform to the top profile sequence.—Plateau:The top boundary of a subblock b i(1≤i≤n)in the contour is higher than the top profile sequence at the position of b i.Assume that b i has the largest top boundary.We pull all subblocks,except b i,up to conform to the top profile sequence.Moreover,all subblocks must be deleted(or inserted)together for the OP3and OP4operations.For a concave block,there might be empty space between two subblocks.As shown in Figure12,the subblock b1is placed above the subblock b2,which cannot be characterized by an LC relation in the B*-tree.Nevertheless,we can fill the concave holes of a concave block and make it a convex block.We call this operation afilling approximation for the rectilinear block.For any concave block,we treat it as a convex block after applying appropriatefilling.7.EXPERIMENTAL RESULTSWe implemented our algorithm in the C++programming language on a 450MHz SUN Ultra Sparc-I workstation with1Gb memory.Since the bench-marks in previous work are artificial cases and unavailable to us,we generate some general benchmarks for experiments in this article.Our test cases were generated by cutting a rectangle into a set of blocks.Therefore,the optimum area is given by the original block.As shown in Table I,Columns2through4list the numbers of rectangular, L-shaped,and T-shaped blocks.RL10,RL20,and RL30consist of only ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April2003.200•G.M.Wu et al.Table I.Experimental Results #Rectangular #L-Shaped #T-Shaped OptimumResulting Dead Run-time Circuits Blocks Blocks Blocks AreaArea Space (%)(sec)RL105501001000.008(10×10)(10×10)RL2010100400408 2.00307(20×20)(15×27)RL3015150900936 4.001636(30×30)(29×32)RLT10433100102 2.0041(10×10)(6×17)RLT20776400414 3.501096(20×20)(18×23)RLT30101010900945 5.003007(30×30)(27×35)(a)12345678910(b)11098546372Fig.13.Placement for RL10:5rectangular and 5L-shaped blocks:(a)the optimum placement (10×10);(b)the resulting placement (10×10).rectangular and L-shaped blocks.There are 5rectangular and 5L-shaped blocks in RL10,10rectangular and 10L-shaped blocks in RL20,and 15rectan-gular and 15L-shaped blocks in RL30,respectively .RLT10,RLT20,and RLT30consist of not only rectangular and L-shaped blocks,but also T-shaped ones.RLT10is composed of 4rectangular,3L-shaped,and 3T-shaped blocks;RLT20is composed of 7rectangular,7L-shaped,and 6T-shaped blocks;and RLT30is composed of 10rectangular,10L-shaped,and 10T-shaped blocks.The original area of each test case is shown in Column 5.Columns 6and 7list the result-ing area and the dead space (%).The results show that our algorithm obtains the optimum area for RL10and near optimum areas for RL20,RL30,RLT10,RLT20,and RLT30with areas only 2.00,4.00,2.00,3.50,and 5.00%away from the optima,respectively .The run-times for achieving the results ranged from about 8seconds to 50minutes (see Column 8).Figures 13and 14show the optimum and the resulting placement for RL10and RLT30,respectively .ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April 2003.Rectilinear Block Placement Using B*-T rees •201(a)123456789101112131415161718192021222324252627282930123456789101113121920142115161718263029252824232722(b)Fig.14.Placement for RLT30:10rectangular,10L-shaped,and 10T-shaped blocks:(a)the opti-mum placement (30×30);(b)the resulting placement (27×35).8.CONCLUSIONSIn this article,we have extended the B*-tree approach introduced in Chang et al.[2000]to handle the placement of arbitrarily shaped rectilinear blocks.We partitioned a rectilinear block into a set of rectangular subblocks,each indi-vidually represented by a node in the B*-tree.The LC relations and the basin and plateau operations were used to ensure that each block kept its original shape.The experiment results have shown that our approach is very effective in area utilization.REFERENCESC HANG ,Y.-C.,C HANG ,Y.-W .,W U ,G.-M.,AND W U ,S.-W .2000.B*-Trees:A new representation for non-slicing floorplans.In Proceedings of the ACM/IEEE Design Automation Conference ,(Los Angeles,June),458–463.G UO ,P .-N.,C HENG ,C.-K.,AND Y OSHIMURA ,T .1999.An O-tree representation of non-slicing floor-plan and its applications.In Proceedings of the ACM/IEEE Design Automation Conference (California,June),268–273.P APADIMITRIOU ,C.AND S TEIGLITZ ,binatorial Optimization:Algorithms and Complex-ity .Prentice-Hall Inc.,Englewood Cliffs,NJ.K ANG ,M.Z.AND D AI ,W .1997.General floorplanning with L-shaped,T-shaped and soft blocks based on bounded slicing grid structure.In Proceedings of the ACM/IEEE Asia and South Pacific Design Automation Conference (Chiba,Japan,January 28–31),265–270.K ANG ,M.Z.AND D AI ,W .1998.Arbitrary rectilinear block packing based on sequence pair.In Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (San Jose,CA,November 8–12),259–266.K IRKPATRICK ,S.,G ELATT ,C.D.,AND V ECCHI ,M.P .1983.Optimization by simulated annealing.Science 220,4598,671–680.L EE ,T .C.1993.A bounded 2D contour searching algorithm for floorplan design with arbitrar-ily shaped rectilinear and soft modules.In Proceedings of the ACM/IEEE Design Automation Conference (California,June),525–530.ACM Transactions on Design Automation of Electronic Systems,Vol.8,No.2,April 2003.。
一种基于程序切片技术的软件测试方法李必信;方祥圣;袁海;郑国梁【期刊名称】《计算机科学》【年(卷),期】2001(028)012【摘要】It is well acknowledged that quality of software has a higher priority than the performance and functions of software. One of the ways to get high-quality software is to get more efficient software-testing techniques. Theory and technology of software quality assurance are an important part of software developing methodology and software engineering. Software testing plays a key role in software quality assurance. The purpose of the essay is to search for new software testing method and to solve some problems in testing of object-oriented program. We also try to amend some deficiency in the traditional test method for structured programs. By the idea of program slicing, we can disassemble the source code of a program into several slices following certain rules. Instead of testing the whole program, we can test these slices. We can also guarantee the equivalence of the two ways. Testing on the base of program slicing has several advantages than the one simply using data flow analysis and control flow analysis. The first, because a program equals to the union of its slices, to test all of the slices makes a complete test of the program, and to test each slice which is related to the interested variables is actually a complete test of the requirement test. Then we solve the problem ofsufficiency in traditional structured program testing and object-oriented program testing as well. The second, program slicing technique can be applied to the testing of both structured programs and object-oriented ones.【总页数】6页(P97-101,112)【作者】李必信;方祥圣;袁海;郑国梁【作者单位】南京大学;安徽经济管理学院,;南京大学;南京大学【正文语种】中文【中图分类】TP31【相关文献】1.基于程序切片的软件测试技术初探 [J], 韩永生;章雪梅2.基于程序切片技术的回归测试方法研究 [J], 陈永郑;李龙澍3.基于粗粒度程序切片技术的遗产软件系统理解方法研究 [J], 杜林;胡秀琴;江海燕4.基于程序切片技术的云计算软件安全模型研究 [J], 崔艳鹏;冯璐铭;闫峥;蔺华庆5.一种基于程序切片算法的软件故障诊断策略 [J], 周婕;慕晓冬;王杰因版权原因,仅展示原文概要,查看原文内容请购买。
a r X i v :c s /0105008v 1 [c s .S E ] 5 M a y 2001Applying Slicing Technique to Software ArchitecturesJianjun ZhaoDepartment of Computer Science and EngineeringFukuoka Institute of Technology3-10-1Wajiro-Higashi,Higashi-ku,Fukuoka 811-0214,JapanEmail:zhao@cs.fit.ac.jpAbstractSoftware architecture is receiving increasingly atten-tion as a critical design level for software systems.As software architecture design resources (in the form of ar-chitectural specifications)are going to be accumulated,the development of techniques and tools to support ar-chitectural understanding,testing,reengineering,main-tenance,and reuse will become an important issue.This paper introduces a new form of slicing,named archi-tectural slicing,to aid architectural understanding and reuse.In contrast to traditional slicing,architectural slicing is designed to operate on the architectural spec-ification of a software system,rather than the source code of a program.Architectural slicing provides knowl-edge about the high-level structure of a software system,rather than the low-level implementation details of a program.In order to compute an architectural slice,we present the architecture information flow graph which can be used to represent information flows in a software architecture.Based on the graph,we give a two-phase algorithm to compute an architectural slice.1IntroductionSoftware architecture is receiving increasingly atten-tion as a critical design level for software systems [18].The software architecture of a system defines its high-level structure,exposing its gross organization as a col-lection of interacting components.A well-defined ar-chitecture allows an engineer to reason about system properties at a high level of abstraction.Architectural description languages (ADLs)are formal languages that can be used to represent the architecture of a software system.They focus on the high-level structure of the overall application rather than the implementation de-tails of any specific source module.Recently,a number of architectural description languages have been pro-posed such as W right [2],Rapide [13],UniCon [17],and ACME [9]to support formal representation and reason-ing of software architectures.As software architecture design resources (in the form of architectural specifica-tions)are going to be accumulated,the development of techniques to support software architectural under-standing,testing,reengineering,maintenance and reuse will become an important issue.One way to support software architecture develop-ment is to use slicing technique.Program slicing,origi-nally introduced by Weiser [23],is a decomposition tech-nique which extracts program elements related to a par-ticular computation.A program slice consists of those parts of a program that may directly or indirectly affect the values computed at some program point of interest,referred to as a slicing criterion .The task to compute program slices is called program slicing .To understand the basic idea of program slicing,consider a simple ex-ample in Figure 1which shows:(a)a program frag-ment and (b)its slice with respect to the slice criterion (Total ,14).The slice consists of only those statements in the program that might affect the value of variable Total at line 14.The lines represented by small rectan-gles are statements that have been sliced away.We refer to this kind of slicing as traditional slicing to distinguish it from a new form of slicing introduced later.Traditional slicing has been studied primarily in the context of conventional programming languages [21].In such languages,slicing is typically performed by using a control flow graph or a dependence graph [5,12,7,16,24,25].Traditional slicing has many ap-plications in software engineering activities including program understanding [6],debugging [1],testing [3],maintenance [8],reuse [15],reverse engineering [4],and complexity measurement [16].Applying slicing technique to software architectures promises benefit for software architecture development at least in two aspects.First,architectural understand-ing and maintenance should benefit from slicing.When a maintainer wants to modify a component in a software architecture in order to satisfy new design requirements,the maintainer must first investigate which components will affect the modified component and which compo-nents will be affected by the modified component.This process is usually called impact analysis .By slicing a software architecture,the maintainer can extract the parts of a software architecture containing those compo-nents that might affect,or be affected by,the modified component.The slicing tool which provides such infor-mation can assist the maintainer greatly.Second,archi-tectural reuse should benefit from slicing.While reuse of code is important,in order to make truly large gains in productivity and quality,reuse of software designs and patterns may offer the greater potential for return on investment.By slicing a software architecture,a sys-1 begin2 read(X,Y);3 Total := 0.0;4 Sum := 0.0;5 if X <= 1 then6 Sum := Y;7 else8 begin9 read(Z);10 Total := X * Y;11 end;12 end if13 Write(Total, sum);14 end1 begin2 read(X,Y);3 Total := 0.0; 45 if X <= 1 then 67 else8 begin 910 Total := X * Y;11 end;12 end if 1314 end(a) A program fragment.(b) a slice of (a) on the criterion (Total,14).Figure 1:A program fragment and its slice on criterion (Total ,14).tem designer can extract reusable architectures from it,and reuse them into new system designs for which they are appropriate.While slicing is useful in software architecture devel-opment,existing slicing techniques for conventional pro-gramming languages can not be applied to architectural specifications straightforwardly due to the following rea-sons.Generally,the traditional definition of slicing is concerned with slicing programs written in conventional programming languages which primarily consist of vari-ables and statements,and the slicing notions are usually defined as (1)a slicing criterion is a pair (s,V)where s is a statement and V is a set of variables defined or used at s ,and (2)a slice consists of only statements.However,in a software architecture,the basic elements are components and their interconnections,but neither variables nor statements as in conventional program-ming languages.Therefore,to perform slicing at the architectural level,new slicing notions for software ar-chitectures must be defined.In this paper,we introduce a new form of slicing,named architectural slicing .In contrast to traditionalslicing,architectural slicing is designed to operate on a formal architectural specification of a software sys-tem,rather than the source code of a conventional pro-gram.Architectural slicing provides knowledge about the high-level structure of a software system,rather than the low-level implementation details of a conven-tional program.Our purpose for development of archi-tectural slicing is different from that for development of traditional slicing.While traditional slicing was de-signed originally for supporting source code level un-derstanding and debugging of conventional programs,architectural slicing was primarily designed for support-ing architectural level understanding and reuse of large-scale software systems.However,just as traditional slic-ing has many other applications in software engineering activities,we believe that architectural slicing is also useful in other software architecture development activ-ities including architectural testing,reverse engineering,reengineering,and complexity measurement.Abstractly,our slicing algorithm takes as input a for-mal architectural specification (written in its associated architectural description language)of a software system,then it removes from the specification those components and interconnections between components which are not necessary for ensuring that the semantics of the specifi-cation of the software architecture is maintained.This benefit allows unnecessary components and interconnec-tions between components to be removed at the archi-tectural level of the system which may lead to consid-erable space savings,especially for large-scale software systems whose architectures consist of numerous com-ponents.In order to compute an architectural slice,we present the architecture information flow graph which can be used to represent information flows in a software architecture.Based on the graph,we give a two-phase algorithm to compute an architectural slice.The rest of the paper is organized as follows.Section 2briefly introduces how to represent a software archi-tecture using W right :an architectural description lan-guage.Section 3shows a motivation example.Section 4defines some notions about slicing software architec-tures.Section 5presents the architecture information flow graph for software architectures .Section 6gives a two-phase algorithm for computing an architectural slice.Section 7discusses the related work.Concluding remarks are given in Section 8.2Software Architectural Specification in W rightWe assume that readers are familiar with the basic concepts of software architecture and architectural de-scription language,and in this paper,we use W right architectural description language [2]as our target lan-guage for formally representing software architectures.The selection of W right is based on that it supports to represent not only the architectural structure but also the architectural behavior of a software architecture.Below,we use a simple W right architectural speci-Configuration GasStationComponent CustomerPort Pay=pay!x→pump?x→GasComputation=Pay.pay!x→Gas.pump?x→Computation Component CashierPort Customer1=pay?x→Customer1Port Customer2=pay?x→Customer2Port Topump=pump!x→Computation []Customer2.pay?x→Topump.pump!x→Oil1Port Oil2=take→pump!x→Computation)[](Oil2.take→Oil2.pump!xCashierRole Givemoney=pay!x→GlueConnector Customer→pump?x→GetoilRole Giveoil=take→pump!x→Giveoil.pump?x→Getoil.pump!xPumpRole Tell=pump!x→GlueInstancesCustomer1:CustomerCustomer2:Customercashier:Cashierpump:PumpCustomer1CashierCustomer2CashierCustomer1PumpCustomer2Pumpcashier PumpAttachmentsCustomer1.Pay as Customer1pump.GetoilCustomer2.Pay as Customer2pump.Getoilcasier.Customer1as Customer1cashier.Getmoneycashier.Topump as cashierpump.Knowpump.Oil1as Customer1pump.GiveoilEnd GasStation.Figure2:An architectural specification in W right.fication taken from[14]as a sample to briefly introduce how to use W right to represent a software architecture. The specification is showed in Figure2which models the system architecture of a Gas Station system[11].2.1Representing Architectural StructureW right uses a configuration to describe architec-tural structure as graph of components and connectors.Components are computation units in the system.In W right,each component has an interface defined by a set of ports.Each port identifies a point of interaction between the component and its environment.Connectors are patterns of interaction between com-ponents.In W right,each connector has an interface defined by a set of roles.Each role defines a participant of the interaction represented by the connector.A W right architectural specification of a system is defined by a set of component and connector type defini-tions,a set of instantiations of specific objects of these types,and a set of attachments.Attachments specify which components are linked to which connectors.For example,in Figure2there are three compo-nent type definitions,Customer,Cashier and Pump,and three connector type definitions,Customer_Cashier, Customer_Pump and Cashier_Pump.The configuration is composed of a set of instances and a set of attach-ments to specify the architectural structure of the sys-tem.2.2Representing Architectural BehaviorW right models architectural behavior according to the significant events that take place in the computa-Customer1Customer2pumpFigure 3:The architecture of the Gas Station system.tion of components,and the interactions between com-ponents as described by the connectors.The nota-tion for specifying event-based behavior is adapted from CSP [10].Each CSP process defines an alphabet of events and the permitted patterns of events that the process may exhibit.These processes synchronize on common events (i.e.,interact)when composed in paral-lel.W right uses such process descriptions to describe the behavior of ports,roles,computations and glues.A computation specification specifies a component’s behavior:the way in which it accepts certain events on certain ports and produces new events on those or other ports.Moreover,W right uses an overbar to distin-guish initiated events from observed events ∗.For ex-ample,the Customer initiates Pay action (i.e.,pay!x).As a result,based on formal W right architectural specifications,we can infer which ports of a component are input ports and which are output ports.Also,we can infer which roles are input roles and which are out-specification of the original one which includes those components and connectors that might affect the com-ponent cashier through the ports in the criterion,and a forward architectural slice is a partial specification of the original one which includes those components and connectors that might be affected by the component cashier through the ports in the criterion.The other parts of the specification that might not affect or be af-fected by the component cashier will be removed,i.e., sliced away from the original specification.The main-tainer can thus examine only the contents included in a slice to investigate the impact of modifi-ing the algorithm we will present in Section6,the slice shown in Figure6can be computed.4Architectural SlicingIntuitively,an architectural slice may be viewed as a subset of the behavior of a software architecture,simi-lar to the original notion of the traditional static slice. However,while a traditional slice intends to isolate the behavior of a specified set of program variables,an ar-chitectural slice intends to isolate the behavior of a spec-ified set of a component or connector’s elements.Given an architectural specification P=(C m,C n,c g),our goal is to compute an architectural slice S p=(C′m,C′n,c′g) which should be a“sub-architecture”of P and preserve partially the semantics of P.To define the meanings of the word“sub-architecture,”we introduce the concepts of a reduced component,connector and configuration. Definition4.1Let P=(C m,C n,c g)be an architec-tural specification and c m∈C m,c n∈C n,and c g be a component,connector,and configuration of P respec-tively:•A reduced component of c m is a component c′m that is derived from c m by removing zero,or more ele-ments from c m.•A reduced connector of c n is a connector c′n that is derived from c n by removing zero,or more elements from c n.•A reduced configuration of c g is a configuration c′g that is derived from c g by removing zero,or more elements from c g.The above definition showed that a reduced compo-nent,connector,or configuration of a component,con-nector,or configuration may equal itself in the case that none of its elements has been removed,or an empty com-ponent,connector,or configuration in the case that all its elements have been removed.For example,the followings show a component Customer,a connector Customer_Cashier,and a con-figuration as well as their corresponding reduced com-ponent,connector,and configuration.The small rect-angles represent those ports,roles,or instances and at-tachments that have been removed from the original component,connector,or configuration.(1)The component Customer and its reduced compo-nent(with*mark)in which the port Gas and elements Gas.take→PayPort Gas=take→Gas.take→Pay22222222222222222222Computation=Pay.pay!xCashierRole Givemoney=pay!x→Glue*Connector Customer→Glue(3)The configuration and its reduced configuration (with*mark)in which some instances and attachments have been removed.InstancesCustomer1:CustomerCustomer2:Customercashier:Cashierpump:PumpCustomer1CashierCustomer2CashierCustomer1PumpCustomer2Pumpcashier PumpAttachmentsCustomer1.Pay as Customer1pump.GetoilCustomer2.Pay as Customer2pump.Getoilcasier.Customer1as Customer1cashier.Getmoney cashier.Topump as cashierpump.Knowpump.Oil1as Customer1pump.Giveoil*InstancesCustomer1:CustomerCustomer2:Customercashier:Cashier22222222Customer1CashierCustomer2Cashier222222222222222222222222222222222222222222222222222222222222*AttachmentsCustomer1.Pay as Customer1cashier.Givemoney 222222222222222222222222222casier.Customer1as Customer1cashier.Getmoney 222222222222222222222222222222222222222222222222222222222222222222222222222222222222222222222222222Having the definitions of a reduced component,con-nector and configuration,we can define the meaning of the word“sub-architecture”.Definition4.2Let P=(C m,C n,c g)and P′= (C′m,C′n,c′g)be two architectural specifications.Then P′is a reduced architectural specification of P if:•C′m={c′m1,c′m2,...,c′mk}is a“subset”of C m={c m1,c m2,...,c mk}such that for i=1,2,...,k,c′miis a reduced component of c m i,•C′n={c′n1,c′n2,...,c′nk}is a“subset”of C n={c n1,c n2,...,c nk}such that for i=1,2,...,k,c′niis a reduced connector of c n i,•c′g is a reduced configuration of c g,Having the definition of a reduced architectural spec-ification,we can define some notions about slicing soft-ware architectures.In a W right architectural specification,for exam-ple,a component’s interface is defined to be a set of ports which identify the form of the component inter-acting with its environment,and a connector’s interface is defined to be a set of roles which identify the form of the connector interacting with its environment.To un-derstand how a component interacts with other compo-nents and connectors for making changes,a maintainer must examine each port of the component of interest. Moreover,it has been frequently emphasized that con-nectors are as important as components for architec-tural design,and a maintainer may also want to modify a connector during the maintenance.To satisfy these requirements,for example,we can define a slicing cri-terion for a W right architectural specification as a set of ports of a component or a set of roles of a connector of interest.Definition4.3Let P=(C m,C n,c g)be an architec-tural specification.A slicing criterion for P is a pair (c,E)such that:1.c∈C m and E is a set of elements of c,or2.c∈C n and E is a set of elements of c.Note that the selection of a slicing criterion depends on users’interests on what they want to examine.If they are interested in examining a component in an ar-chitectural specification,they may use slicing criterion 1.If they are interested in examining a connector,they may use slicing criterion2.Moreover,the determina-tion of the set E also depends on users’interests on what they want to examine.If they want to examine a component,then E may be the set of ports or just a subset of ports of the component.If they want to ex-amine a connector,then E may be the set of roles or just a subset of roles of the connector.Definition4.4Let P=(C m,C n,c g)be an architec-tural specification.•A backward architectural slice S bp=(C′m,C′n,C′g) of P on a given slicing criterion(c,E)is a reduced architectural specification of P which contains only those reduced components,connectors,and config-uration that might directly or indirectly affect the behavior of c through elements in E.•Backward-slicing an architectural specification P on a given slicing criterion is tofind the backward architectural slice of P with respect to the criterion. Definition4.5Let P=(C m,C n,c g)be an architec-tural specification.•A forward architectural slice S fp=(C′m,C′n,C′g) of P on a given slicing criterion(c,E)is a reduced architectural specification of P which contains only those reduced components,connectors,and config-uration that might be directly or indirectly affected by the behavior of c through elements in E.•Forward-slicing an architectural specification P ona given slicing criterion is tofind the forward ar-chitectural slice of P with respect to the criterion.From Definitions4.4and4.5,it is obviously that there is at least one backward slice and at least one forward slice of an architectural specification that is the specification itself.Moreover,the architecture repre-sented by S bp or S fp should be a“sub-architecture”of the architecture represented by P.Defining an architectural slice as a reduced architec-tural specification of the original one is particularly use-ful for supporting architectural reuse.By using an ar-chitectural slicer,a system designer can automatically decompose an existing architecture(in the case that its architectural specification is available)into some small architectures each having its own functionality which may be reused in new system designs.Moreover,the view of an architectural slice as a reduced architecturalpv1: Customer1.Paypv2: Customer1.Gaspv3: Customer2.Paypv4: Customer2.Gaspv5: cashier.Customer1pv6: cashier.Customer2pv7: cashier.Topumppv8: pump.Fromcashierpv9: pump.Oil1pv10: pump.Oil2rv1: Customer1_cashier.Givemoneyrv2: Customer1_cashier.Getmoneyrv3: Customer2_cashier.Givemoneyrv4: Customer2_cashier.Getmoneyrv5: cashier_pump.Tellrv6: cashier_pump.Knowrv7: Customer1_pump.Getoilrv8: Customer1_pump.Giveoilrv9: Customer2_pump.Getoilrv10: Customer2_pump.GiveoilFigure4:The informationflow graph of the architectural specification in Figure2.specification dose not reduce its usefulness when applied it to architectural understanding because it also con-tains enough information for a maintainer to facilitate the modification.5The Information Flow Graph for Soft-ware ArchitecturesIn this section,we present the architecture informa-tionflow graph for software architectures on which ar-chitectural slices can be computed efficiently.The architecture informationflow graph is an arc-classified digraph whose vertices represent the ports of components and the roles of the connectors in an archi-tectural specification,and arcs represent possible infor-mationflows between components and/or connectors in the specification.Definition5.1The Architecture Information Flow Graph(AIFG)of an architectural specification P is an arc-classified digraph(V com,V con,Com,Con,Int), where:•V com is the set of port vertices of P;•V con is the set of role vertices of P;•Com is the set of component-connectorflow arcs;•Con is the set of connector-componentflow arcs;•Int is the set of internalflow arcs.There are three types of informationflow arcs in the AIFG,namely,component-connectorflow arcs, connector-componentflow arcs,and internalflow arcs.Component-connectorflow arcs are used to represent informationflows between a port of a component and a role of a connector in an architectural specification. Informally,if there is an informationflow from a port of a component to a role of a connector in the specifi-cation,then there is a component-connectorflow arc in the AIFG which connects the corresponding port vertex to the corresponding role vertex.For example,from the W right specification shown in Figure2,we can know that there is an informationflow from the port Topump of the component cashier to the role Tell of the con-nector cashier_pump.Therefore there is a component-connectorflow arc in the AIFG in Figure4which con-nects the port vertex of port Topump to the role vertex of role Tell.Connector-componentflow arcs are used to represent informationflows between a role of a connector and a port of a component in an architectural specification. Informally,if there is an informationflow from a role of a connector to a port of a component in the speci-fication,then there is a connector-componentflow arc in the AIFG which connects the corresponding role ver-tex to the corresponding port vertex.For example,from the W right specification in Figure2,we can know that there is an informationflow from the role Know of the connector cashier_pump to the port Fromcashier of the component pump.Therefore,there is a connector-componentflow arc in the AIFG in Figure4which con-nects the role vertex for role Know to the port vertex for port Fromcashier.Internalflow arcs are used to represent internal in-formationflows within a component or connector in an architectural specifirmally,for a component in the specification,there is an internalflow from an input port to an output port,and for a connector in the specification,there is an internalflow from an in-put role to an output role.For example,in Figure2, there is an internalflow from the role Givemoney to the role Getmoney of the connector Customer1_cashier and also an internalflow arc from the port Fromcashier to the port Oil1of component pump.As we introduced in Section2,W right uses CSP-based model to specify the behavior of a component and a connector of a software architecture.W right allows user to infer which ports of a component are input and which are output,and which roles of a connector are input and which are output based on a W right archi-tectural specification.Moreover,it also allows user to infer the direction in which the information transfers be-tween ports and/or roles.As a result,by using a static analysis tool which takes an architectural specification as its input,we can construct the AIFG of a W right architectural specification automatically.Figure4shows the AIFG of the architectural specifi-cation in Figure2.In thefigure,large squares represent components in the specification,and small squares rep-resent the ports of each component.Each port vertex has a name described by component name. For example,pv5(cashier.Customer1)is a port ver-tex that represents the port Customer1of the compo-nent rge circles represent connectors in the specification,and small circles represent the roles of each connector.Each role vertex has a name de-scribed by connector name.For example,rv5 (cashier_pump.Tell)is a role vertex that represents the role Tell of the connector cashier_pump.The com-plete specification of each vertex is shown on the right side of thefigure.Solid arcs represent component-connectorflow arcs that connect a port of a component to a role of a connec-tor.Dashed arcs represent connector-componentflow arcs that connect a role of a connector to a port of a component.Dotted arcs represent internalflow arcs that connect two ports within a component(from an input port to an output port),or two roles within a con-nector(from an input role to an output role).For exam-ple,(rv2,pv5)and(rv6,pv8)are connector-component flow arcs.(pv7,rv5)and(pv9,rv8)are component-connectorflow arcs.(rv1,rv2)and(pv8,pv10)are in-ternalflow arcs.6Computing Architectural Slices The slicing notions defined in Section4give us only a general view of an architectural slice,and do not tell us how to compute it.In this section we present a two-phase algorithm to compute a slice of an architectural specification based on its informationflow graph.Our algorithm contains two phases:(1)Computing a slice S g over the informationflow graph of an architectural specification,and(2)Constructing an architectural slice S p from S g.6.1Computing a Slice over the AIFGLet P=(C m,C n,c g)be an architectural specifica-tion and G=(V com,V con,Com,Con,Int)be the AIFG of P.To compute a slice over the G,we refine the slicing notions defined in Section4as follows:•A slicing criterion for G is a pair(c,V c)such that:(1)c∈C m and V c is a set of port vertices corre-sponding to the ports of c,or(2)c∈C n and V c isa set of role vertices corresponding to roles of c.•The backward slice S bg(c,V c)of G on a given slic-ing criterion(c,V c)is a subset of vertices of G such that for any vertex v of G,v∈S bg(c,V c)iffthere exists a path from v to v′∈V c in the AIFG.•The forward slice S fg(c,V c)of G on a given slicing criterion(c,V c)is a subset of vertices of G such that for any vertex v of G,v∈S fg(c,V c)iffthere exists a path from v′∈V c to v in the AIFG.According to the above descriptions,the computa-tion of a backward slice or forward slice over the AIFG can be solved by using an usual depth-first or breath-first graph traversal algorithm to traverse the graph by taking some port or role vertices of interest as the start point of interest.Figure5shows a backward slice over the AIFG with respect to the slicing criterion(cashier,V c)such that V c={pv5,pv6,pv7}.6.2Computing an Architectural SliceThe slice S g computed above is only a slice over the AIFG of an architectural specification,which is a set of vertices of the AIFG.Therefore we should map each element in S g to the source code of the specification.Let P=(C m,C n,c g)be an architectural specification and G=(V com,V con,Com,Con,Int)be the AIFG of P.By using the concepts of a reduced component,connector, and configuration introduced in Section4,a slice S p= (C′m,C′n,c′g)of an architectural specification P can be constructed in the following steps:1.Constructing a reduced component c′m from a com-ponent c m by removing all ports such that their corresponding port vertices in G have not been in-cluded in S g and unnecessary elements in the com-putation from c m.The reduced components C′m in S p have the same relative order as the componentsC m in P.2.Constructing a reduced connector c′n from a con-nector c n by removing all roles such that their cor-responding role vertices in G have not been in-cluded in S g and unnecessary elements in the glue from c n.The reduced connectors C′n in S p have the。