高速pcb设计与电路板分析课程讲义3

目录高速PCB设计入门概念问答高速PCB设计指南（一）高速PCB设计指南（二）高速PCB设计指南（三）高速PCB设计指南（四）高速PCB设计指南（五）高速PCB设计指南（六）高速PCB设计指南（七）高速PCB设计指南（八）高速PCB布线问题高速PCB板的电源布线设计高速PCB设计心得设计高速电路板的注意事项高速板4层以上布线总结接地技术总结高速印制电路板的设计及布线要点5GHz的高频电路设计技巧高速PCB设计入门概念问答要做高速的PCB设计，首先必须明白下面的一些基本概念，这是基础。

1、什么是电磁干扰（EMI）和电磁兼容性(EMC)?(Electromagnetic Interference)，有传导干扰和辐射干扰两种。

传导干扰是指通过导电介质把一个电网络上的信号耦合（干扰）到另一个电网络。

辐射干扰是指干扰源通过空间把其信号耦合（干扰）到另一个电网络。

在高速PCB及系统设计中，高频信号线、集成电路的引脚、各类接插件等都可能成为具有天线特性的辐射干扰源，能发射电磁波并影响其他系统或本系统内其他子系统的正常工作。

自从电子系统降噪技术在70年代中期出现以来，主要由于美国联邦通讯委员会在1990年和欧盟在1992提出了对商业数码产品的有关规章，这些规章要求各个公司确保它们的产品符合严格的磁化系数和发射准则。

符合这些规章的产品称为具有电磁兼容性EMC（Electromagnetic Compatibility）。

2、什么是信号完整性(signal integrity)?信号完整性是指信号在信号线上的质量。

信号具有良好的信号完整性是指当在需要的时候，具有所必需达到的电压电平数值。

差的信号完整性不是由某一单一因素导致的，而是板级设计中多种因素共同引起的。

主要的信号完整性问题包括反射、振荡、地弹、串扰等。

常见信号完整性问题及解决方法问题可能原因解决方法其他解决方法过大的上冲终端阻抗不匹配终端端接使用上升时间缓慢的驱动源直流电压电平不好线上负载过大以交流负载替换直流负载在接收端端接，重新布线或检查地平面过大的串扰线间耦合过大使用上升时间缓慢的发送驱动器使用能提供更大驱动电流的驱动源时延太大传输线距离太长替换或从新部线，检查串行端接使用阻抗匹配的驱动源，变更布线策略振荡阻抗不匹配在发送断串接阻尼电阻3、什么是反射(reflection)?反射就是在传输线上的回波。

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高速设计分析技术1Agenda 课程安排High Speed Trends 高速设计趋势 y g 同步系统设计Synchronous Design Source Synchronous Design 源同步系统设计 - DDR2 - DDR3 Serial Link Design 高速串行设计 - I t Interconnect consideration 互连考虑 t id ti - Technologies 设计技术 -8b/10b Encoding 8b/10b编码2高速电路设计趋势Trend towards serial connectivity 向串行连接发展3Parallel I/O Common Clock 并行IO –共同时钟系统Pre-layout simulation for design exploration andpost-layout simulation for verification 可以通过SI前后仿真进行设计 Signal timing 信号时序 Signal noise 信号噪声Undershoot and overshoot 过冲4Parallel I/O Common Clock (继续) 并行IO –共同时钟How to increase data rate? 如何提高数据速率Increase data pin counts 增加管脚 Increase bus clock frequency 增加时钟频率But……但是……Increase data pin counts it's more hard for PCB design (need more space for trace breakout, routing…..) 增加管脚造成PCB设计困难 Increase clock frequency it will reduce timing margin, destroy signal integrity (due to multi-drop top.), restrict data trace length, increase EMI… 增加时钟频率使得时序紧张, 信号完整性问题突出, 走线线长约束严格, 电磁辐射增加…5Parallel I/O Source Synchronous 并行 I/O –源同步系统Provide guidelines for physical layout by sweeping the solution space 可以通过参数扫描分析确定电气约束Measurements for voltage and time specifications and worst case report 得到最坏情况下的信号质量和时序要求 Bus timing analysis 总线时序分析 Slew rate prorating/derating for Setup/Hold Time compensations (DDR2) 考虑边沿速率造成的的建立保持时间的补偿 (DDR2)6Parallel I/O Source Synchronous (继续) 并行 I/O –源同步系统How to increase data rate? 如何提高数据速率Increase bus clock frequency 增加时钟频率 From single strobe to dual strobe 采用读写数据采样时钟 From single end strobe to differential strobe signaling 采用差分时钟But……但是……Increasebusclockfrequencythereisnotheoreticallimitonbuscloc k frequency,buthigherclockfrequencywillcausesignalintegrity p ( p p) depredation(duetomulti‐droptop.) 增加时钟频率使得信号完整性问题突出… Fromsinglestrobetodifferentialstrobeforlesstimingmarginwhiledesignmigratestohighspeed,differentialstrobewillincreaseval idtiming window 采用差分时钟提高速率但是因为速率提高, 时序参数更为紧张7Parallel I/O - Integrating SI with Timing 并行接口分析–综合考虑SI和时序Multiple TopologiesTimingEquationWaveform and Solution SpaceSignal Integrity and Timing Analysis integrated to one solution 信号完整性和时序分析组成一个完整的解决方案8Parallel I/O - Integrating SI with Timing 并行接口分析–综合考虑SI和时序 (继续)Component SpecsA rising edge (when using tDSb and tDHb) must: – Start below VIL_DC – Switch through VIH_AC – Settle above VIH_DC Vin_Meas_R_Low = Vin_Low_DC Vin_Meas_R_High = Vin_High_AC MIN Delay Measured at first crossing of Vin_meas_R_Low MAX Delay Measured at last crossing of Vin_meas_R_HighMin Delay Vin_Meas_R_Low Vin_DC_Low Vin_AC_Low Vref Max Delay Vin_Meas_R_High Vin_AC_High Vin_DC_HighComponent timing is specified under specific loading and measurement conditions 器件时序由特定负载和测量条件构成Timing and signal integrity analysis must be compatible 时序和信号完整性必须兼顾 SI measurements are therefore "normalized" to component timing specs SI相关的测量最终转化为器件的时序规范 Timing Closure occurs when integrated analysis yields acceptable setup/hold margins 可接受的建立/保持时间裕量使时序收敛Vin_AC_High Vin_DC_High Vref Vin_DC_Low Vin_AC_Low"Sim Start time" normalized using reference load specs Switching times based on datasheet setup/hold specs9Serial I/O 串行 I/OInterconnect loss of the channel (entire signal path) 考虑互连损耗Jitter controlled is required due to CDR 控制抖动 Modeling complex drivers and receivers 需要更复杂的器件模型 Stress test the design with LARGE bit streams 要分析大量数据位传输S-parameter simulation (Time domain & Frequency Domain) S-参数分析, 时域和频域分析10Agenda 课程安排High Speed Trends 高速设计趋势 y g 同步系统设计Synchronous Design Source Synchronous Design 源同步系统设计 - DDR2 - DDR3 Serial Link Design 高速串行设计 - I t Interconnect consideration 互连考虑 t id ti - Technologies 设计技术 -8b/10b Encoding 8b/10b编码11Synchronous Design 同步设计系统Sometimes called "Common Clock" 又叫共同时钟系统 Clocks are distributed from a central point to all of the loads. 时钟信号由同一时钟源发送 Max M operating f ti frequency is a f i function of T ti f Tco, T d S t Tpd, Setup, H ld and Hold, d Clock Skew 最大工作频率由缓冲延时,传输延时,建立,保持时间和时钟偏移决定12Synchronous Data Transfer 数据传输方式1 4Hold32Tco Flight TimeD0 D1 D2D0 D1 D2DrivingReceiving13Setu pClock DriverSynchronous Timing Terminology 时序参数Cycle Time (Tcycle)时钟周期Clock Skew 时钟偏移 Cycle 1 Cycle 2Clock to Output (Tco) 时钟输出延时Clock Jitter14Synchronous Timing Terminology (继续) 时序参数Interconnect Delay (Tpd) 互连传输延时Positive Interconnect Delay (Tpd)Negative Interconnect Delay (Tpd)15Defining TcoTco定义Tco = time from clock rise to Vmeas into test load 从时钟边沿进入器件到数据从器件输出有效的时间(数据输出接测试负载)Clock Clock rises t=0 DinInternal LogicOutput BufferVmeasTco TRL = 50 Ω Load for Tco measurement (from databook)16Components of TcoClock Clock rises t=0 DinTco的组成Internal I t l LogicOutput BufferVmeasTcoRL = 50 Ω Internal delay = from clock External (buffer) delay = how rise to the point where the long the buffer takes to drive the output begins to switch reference load to Vmeas 缓冲器时延内部逻辑时延17Clock JitterClock Driver Cycle 1 Cycle 2时钟抖动Clock Jitter occurs when the clock period varies from one period to the next 考虑周期差抖动Usually caused by PLL instability in the clock driver 通常由锁相环引起 Jitter increases / decreases the clock period period, decreasing the effective clock cycle 抖动减小有效时钟周期18Clock Skew 时钟偏斜Clock t = 0 DriverOccurs when different devices see the clock transition atdifferent times 时钟到达不同器件的时延Increases / decreases the apparent clock cycle. Depending on which devices are driving / receiving 根据 g gt=1D0 D1 D2t=2D0 D1 D2驱动接收不同变化Reduces the effective clock cycle 减小有效时钟周期19内部偏斜和外部偏斜时钟驱动器造成内部偏斜而PCB布线和设计以及外部环境引起的偏斜被称为外而 C 布线和设计以及外部环境引起的偏斜被称为外部偏斜 tSKEW_INTRINSIC = 器件引起的偏斜 tSKEW_EXTRINSIC = PCB + 布线 + 工作环境引起的偏斜 tSKEW = tSKEW_INTRINSIC + tSKEW_EXTRINSIC20内部偏斜 - 输出偏斜 (tSK)单一器件的指定输出之间的偏斜 (JEDEC) 输出偏斜也称为引脚到引脚的偏斜.输出偏斜是同一输出偏斜也称为引脚到引脚的偏斜输出偏斜是同器件上同一跃迁的任何两个输出延时之间的差值21内部偏斜 - 封装偏斜 (tDSK)在相同环境下工作的两个独立器件的任何指定输出之间的传送延时之差也称为器件到器件的偏斜.类似于输出偏斜,只是它用于两个或多个相同的器件22外部偏斜 - 传送延时(tpd)当输出从一个指定的电平改变到另一个电平时,输入和输出电压波形上的指定基准点之间的时间23PCB走线影响时钟偏斜(传送延迟)因素Clock skew is caused by: 原因 variation in the loading between different agents on the bus (CL).负载不一致variation in interconnect characteristics (Z0, τ d ) 互连结构特性 ). Crosstalk 串扰 variation in electrical lengths. What is electrical length?互连电气长度差Clock Driver Z0 , τ dTdrvCL a CL b24TdrvZ0 , τ d建立和保持时间 (Tsetup和Thold)建立时间和保持时间:建立时间(setup time):是指在时钟信号上升沿到来以前,数据稳定不变的时间,如果建立时间不够,数据将不能在这个时钟上升沿被打入; 保持时间(hold time):是指在时钟信号上升沿到来以后,数据稳定不变的时间, 如果保持时间不够,数据同样不能被打入.25同步电路时序分析clk: 时钟驱动器 a: 数据发送器件 b: 数据接收器件 CLOCK(a) @ clk output CLOCK @ clk inputclkCLOCK(b) @ clk outputFROM CORECLK D QCLK D QaCLOCK(a) @ aDATA @ aDATA @ bTO COREbCLOCK(b) @ b26Setup Timing Diagram & Loop Analysis同步电路建立时间分析CLOCK @ clk input CLOCK(a) ( ) @ clk output CLOCK(a) @ a DATA @ a DATA @ b CLOCK(b) @ clk output CLOCK(b) @ b Tcycle Tdrv_clk Tprop_clk Tco Tprop Tmargin Tdrv_clk Tsetup(b)Tprop_clk(b) TjitterTcycle + Tdrv _ clk (b ) + T prop _ clk (b ) T jitter Tsetup Tm arg in T prop Tco T prop _ clk Tdrv _ clk = 027Hold Timing Equation 保持时间分析Uses same clock edge Hold equation 公式同一时钟沿Tdrv _ clk + T prop _ clk + Tco + T prop Tm arg in _ hold Thold T prop _ clk (b ) Tdrv _ clk (b ) = 0Define定义时钟偏斜Clock Delay 传送延迟Tclk ≡ Tdrv _ clk + T prop _ clk Clock Skew 时钟偏斜Tskew ≡ Tclk (b ) Tclk (a )28Simplify Timing Equations 公式简化Setup margin = Tcycle - Tco_max - Tpd_max - Tsetup + Tsetup_skew SETUP @ Maximum Data, Minimum Clock Hold margin = Tco_min + Tpd_min - Thold - Thold_skew HOLD @ Minimum Data,Maximum Clock29仿真波形分析时序30仿真波形分析时序 (继续)31Common Clock Bus Example 案例Intel Pentium-Pro reference design Pentium-Pro 参考设计Processor/Chipset Bus (GTL+, 66 MHz) GTL + 66MHz总线 Intel GTL+ Design Guidelines 参考英特尔GTL + 设计指导32Defining Device Timing 定义器件时序参数Pentium Pro Timings taken from "AC (dynamic) p Specifications" sections of Intel datasheets 时序参数参考器件手册 "AC Specifications" 部分 Important parameters 重要参数Clock → Data Valid for GTL+ Bus Tco时间 Setup / Hold requirements for GTL+ signals440FX (timings from 440LX)需要的建立保持时间PLL Jitter (if spec'd)锁相环抖动33Determining Flight Times 计算走线需要的飞行时间Device Timing InformationTcom in Tcom ax Setup Hold Pentium Pro 0.55 ns 4.40 ns 2.20 ns 0.45 ns 440FX 1.25 ns 7.25 ns 5.00 ns 0.00 nsBudgeted Parameters Clock Skew Clock Jitter Crosstalk Clock Freq. Clock Period 0.2 ns 0.4 ns 0.4 ns 66 MHz 15.15 ns Pentium Pro to 440FXTflightmax = ClockPeriod Tco max - Skew - Jitter - Crosstalk - Receiver(Setup) 15.15 ns 4.40 ns 0.20 ns 0.40 ns 0.40 ns 5.00ns 4.75 Tflightmin = Receiver(Hold) - Tco min + Skew + Jitter + Crosstalk 0.00 ns 0.55 ns 0.20 ns 0.40 ns 0.40 ns 0.45 ns 440FX to Pentium ProTflightmax = ClockPeriod Tco max - Skew - Jitter - Crosstalk - Receiver(Setup) 15.15 ns 7.25 ns 0.20 ns 0.40 ns 0.40 ns 2.20 ns 4.70 ns Tflightmin = Receiver(Hold) - Tco min + Skew + Jitter Crosstalk 0.45 ns 1.25 ns 0.20 ns 0.40 ns 0.40 ns 0.20 nsTflightmax = 4.70 ns Tflightmin = 0.45 ns34Agenda 课程安排High Speed Trends 高速设计趋势 y g 同步系统设计Synchronous Design Source Synchronous Design 源同步系统设计 - DDR2 - DDR3 Serial Link Design 高速串行设计 - I t Interconnect consideration 互连考虑 t id ti - Technologies 设计技术 -8b/10b Encoding 8b/10b编码35Source Synchronous Design 源同步设计Clock and Data originate at the same source 时钟和数据发自同一源 Originally called Clock forwarding Clock and Data are Correlated 时钟和数据信号相关 They are at the same process corner 相同条件 Temperature, voltage variations effect both the same way 相同影响 Major issue is Delay Variations between DATA and CLOCK 主要因素 Package 封装 PCB etch 电路板蚀刻Loading 负载 On-die Variations 片上参数 Crosstalk 串扰 ISI 码间干扰36Source Synchronous Data Transfer 数据传输方式STB D0 D1 D2 STB D0 D1 D2 Data / STB are synchronized at the driver 数据时钟在发送端保持同步 Device speed (fast, slow) is irrelevant since Data & STB are supplied by the same device 器件本身速率变化不重要 The significant issue is the gaccumulated skew between Data & STB as the signals travel between devices 数据时钟之间的偏斜是主要问题Driving Di iReceiving R i i37Limiting Factors for Source Synchronous Bus Speeds 影响速度的因素Design Factor Bus Length Device delay (Tco) Receiver setup / hold Jitter Differences in device p (fast, slow) ) speed ( Timing Requirement No longer applies No longer applies Still applies Dependes No longer appliesCritical factor is minimizing skew 关键是减小偏斜38Source Synchronous Terminology 时序参数Cycle time vs. Data RateStrobe vs. ClockDelay skew 延时偏移Correlated vs. Uncorrelated Etch39DLL Concept锁延时环D0MUX QD L LD1DQ0CDelay Line(Delay=C)Delay=ACLKDD0MUX QD1DQ1CPhase DetectorDelay Control. . .DQiD0A + BDelayD1MUX QCModelDelay=B40Data Valid Window (数据有效窗口)Conventional flight-time measurements cannot be used 传统的飞行时间测量不再适用 Valid time window concept 应用有效窗口 Calculate all the consumed timing and the timing margin 计算所有的消耗时间和需要的时序裕量Ske wtD Q S QD a ta V a lidt D VSke wtD Q S QA ll D Q a n d D Q S (a t D D R o u tp u ts ) A ll D Q a n d D Q S(a t C P U in p u ts )Skew'tD Q S Q + B o a rd S ke wD a ta V a lid ' tD V -B o a rd S ke wS kew'tD Q S Q + B o a rd S ke w41Derive Source Synchronous Timing Equations 时序计算公式 Setup margin = Tclk_min - Tdata_max -Tdelay_skew_max - Tsetup SETUP @ Maximum Data, Minimum Clock Hold margin = Tdata_rate + Tdata_min + Tdelay_skew_min - Tclk_max - Tcycle_to_cycle_jitter – Thold HOLD @ Minimum Data, Maximum Clock42Specialties for DDR2 - SSTL DDR2一些特性– SSTL电平SSTLVDDQVIH(ac)VIH(dc)VREFVIL(dc) VIL(ac)VSS43SSTL _1844Threshold 电平门限45过冲和时序测量Max Delay (Setup)1V/ns Min Delay (Hold)1.5V/ns 1 5V/nsMin, Max Delay{ΔT46DDR2 Slew Rate Derating 边沿斜率补偿Baseline setup/hold requirements are based on specific voltage and slew rate conditions 基准的建立/保持时间要求基于特定的翻转条件 System slew rates rarely conform to measurement conditions 系统工作的翻转条件很少与定义的基准的建立/保持时间的测试条件一致Loading can vary widely wit47hin the same system 负载变化DDR2 slew-rate derating defines adjustments to setup/hold specs based on actual slew rates of input signals 边沿斜率补偿可以按实际设计调整建立/保持时间DiePackageChip CorePinPad Core47Slew rate 边沿斜率计算48Applying Slew Rate Data 根据斜率查表得到建立保持时间补偿DQ DDR2 derating tables list adjustments to setup / hold timing 建立保持时间补偿表1.5V/nsDQS1.8V/nsSlew rates are measured for each signal independently 边沿斜率对每个信号都要计算 The timing adjustment is read from the table 查表得到时间量调整 Slew rates must be measured Sl t tb d for each edge of each signal 边沿斜率对每个信号每个边沿都要测量49A DDR2 Example DDR2例子AddressCLK ADDR/CMDControlClock/StrobeCTRL DATA DQSRead DataWrite DataMultiple timing relationships 多种时序关系 Each timing relationship involves multiple net classes 每一种时序关系包含多种网络类型 Each net class must be analyzed under multiple operating conditions 每一种网络必须在多种条件下分析Successful design ensures all timing requirements are met under all operating conditions 成功的设计确保所有的时序在所有条件下得到满足ControllerMemory50Real Waveform Processing 实际波形测量处理Let's consider a case where the controller writes data to memory 数据写入内存数据写内存DQ DQS is operated differentially 差分DQS信号Differential rising edge 差分边沿Rising DQS Falling DQS# DQS正端 DQS# 负端DQSRising edge on DQInterconnect delays are to be I t td l t b measured for DQ and DQS signals 互连延迟测量51DQ Signals 数据信号Quality 质量 A rising edge must: 上升沿Start below VIL_DC 从VIL_DC开始 Switch through VIH_AC 跳变到 VIH_AC上 VIH AC上 Settle above VIH_DC 在VIH_DC上保持稳定Timing 时序 MIN delay measured at first crossing of VIL_DC 最小延时测量点在波形第一次穿过VIL_DC的点 Used to compute hold margin 用来计算保持时间 JESD79-2C, page 96, note 21SI ViewMAX delay measured at first crossing of VIH_AC 最大延时测量点在波形第一次穿过VIH_AC的点 Used to compute setup margin 用来计算建立时间 JESD79-2C, page 96, note 20Timing Spec View52Differential DQS Signals 差分时钟信号Quality 质量 The differential voltage swing must be at least VID(ac) 差分信号必须达到正负VID(ac)电平 Must account for duty cycle distortion and Jitter 必须考虑时钟的失真和抖动 Timing MIN, MIN MAX d l delays are measured at d t crossing of DQS and DQS# 延时测量点在差分正负波形的交接点JESD79-2C, page 96, notes 20 & 21SI ViewTiming Spec View53DDR3 - Time Beyond VAC (TVAC) DDR3设计 - TVACSignals must remain above / below VIH/IL(ac) for aspecified time to ensure a valid transition 信号必须在VIH/IL(ac)之上保持一段时间 This time period, TVAC, is slew rate dependent TVAC也是随信号边沿斜率而不同 Signals must satisfy the TVAC requirement even if setup time is negative (signal has not reached VIH/IL(ac) before clock transition) 即使需要的建立时间为负信号也要满足TVAC时间Ref: JESD79-3A, Page 161, Table 71Ref: JESD79-3A, Page 162, Figure 10154"Fly By" ADDCMD / CLK 串行链路的地址/时钟ControllerCLK, CLK_N ADDRCMD / CTRLEnd-terminated daisy-chain topology for ADDCMD/CTRL and CK/CK# signals 菊花链结构的地址时钟走线 Address valid windows at memory inputs are larger, but staggered in time 地址总线的有效窗口台阶状的时延分布. . .55DDR3 Signal Integrity / Timing Analysis SI/时序分析READ WRITEL3DQ DQSL2DQ DQSL1DQ DQSL0DQ DQSADDRCLKCLK ADDR DQS DQCLK ADDR DQS DQCLK ADDR DQS DQCLK ADDR DQS DQ56CK / DQS Relationship 系统时钟和数据采样时钟关系Rising edge of CK has required relationship to both edges of DQS 系统时钟和数据采样时钟的上升沿必须保持一定的时间关系 Relationship must be maintained at each SDRAM 每一个内存芯片都要保证Ref: JESD79-3A, Page 63, Figure 38Ref: JESD79-3A, Page 151, Table 6757CK/CK# to DQS (and therefore DQ) 系统时钟和数据总线ControllerCLK, CLK# ADDR DQS, DQS# DQ<0:N> DQS, DQS# DQ<0:N>Matched length routingMust maintain CK/DQS relationship at each SDRAM 每个内存芯片的系统时钟和数据采样时钟的时序关系都要保证CLK ADDR DQS DQ CLK ADDR DQS DQ 58CK/CK# to DQS (and therefore DQ) 系统时钟和数据总线 (继续)ControllerCLK, CLK# ADDR DQS, DQS# DQ<0:N> DQS, DQS# DQ<0:N>Matched length routingMust adjust DQS timing for each lane to j Q g maintain CK/DQS relationship at SDRAM 必须调整DQS时序 (Write leveling) DQ shifts must follow DQS shifts DQ随着QDS移动 Controllers can adjust DQ/DQS output timing to simplify PCB routing 控制器可以调节DQ/DQS输出时序CLK ADDR DQS DQ CLK ADDR DQS DQ59DQS/CLK AnalysisL3DQ DQSL2DQ DQSL1DQ DQSL0DQ DQSADDRCLKCLK ADDR DQS DQCLK ADDR DQS DQCLK ADDR DQS DQCLK ADDR DQS DQ60Adjusting DQ/DQS Timing 调节DQ/DQS输出时序DQ/DQS aligned with CK/CK# on a per-byte lane basis 对每一路数据信号都要保持DQ/DQS与系统时钟的关系对每路数据信号都要保持DQ/DQS与系统时钟的关系 Write LevelingDDR3 memory devices can report on alignment of received CK/DQS signals DDR3内存报告CK/DQS对齐信息给控制器Controllers can utilize this information to optimizeCLK/DQS/DQ output timing for each byte lane 控制器可以根据这个信息调整DQ/DQS输出时序 Controllers compensate for skew in signals returned from memory on a per-byte line basis 控制器可以补偿部分时序偏差Read Leveling61Agenda 课程安排High Speed Trends 高速设计趋势 y g 同步系统设计Synchronous Design Source Synchronous Design 源同步系统设计 - DDR2 - DDR3 Serial Link Design 高速串行设计 - I t Interconnect consideration 互连考虑 t id ti - Technologies 设计技术 -8b/10b Encoding 8b/10b编码62Serial Link Design 高速串行设计63Serial I/O 高速串行接口Jitter controlled is required due to CDR 抖动控制 Point to point topology 点对点拓扑 Pre/De-emphasis for driver end and equalization at receiver end due to l t loss in l i long i t interconnect 预加重和均衡电路设计改善损耗影响 tHigh-Performance serial signaling implemented with differential signaling technology 差分走线Figure 7.11 Generalized SERDES serial connectionparallel to serial conversion parallel data bus8serial linkserial to parallel conversion SERDES8SERDES PLLrecovered parallel dataPLLbit clock64Differential Impedance 差分阻抗Odd O ModeZ oo =Ls Lm C s + CmLs + Lm Cs CmEven ModeZ oe =Z diff = 2 Z ooZ comm =1 Z oe 265Loosely & Tightly Coupled Diff Pair 松耦合和紧耦合Loosely Coupled DP 松耦合Differential Impedance depends only on single TL. Easy to do the layout, distance changes don't affect the differential impedance. y , g p 易于控制阻抗和布线Tightly Coupled DP 紧耦合High layout density, lower the cost. 布线密度大Differential noise is smaller than Loosely Coupled DP. 差分噪声小 Common noise can be easily controlled by using common mode choke. 可以用共模扼流圈抑制共模噪声 Can minimize the influences of discontinuity in the ground plane current return pass. 可以减小不完整参考平面影响66PCB structures that introduce Skew 差分走线偏差An escape from a BGA or connector pins introduces skew BGA 出线造成偏差This is an p example of skew compensation 一个控制偏差的例子67Broadside&Edge Coupled Diff Pair 上下面耦合和边沿耦合Broadside stripline offers better routing density but the impedance variation is larger due to manufacturing variations and the tight coupling of traces on different layers 上下面耦合提高布线密度但是阻抗难于控制 Edge-coupled stripline has the largest attenuation constant 边沿耦合带状线具有最大的衰减常数 Edge-coupled microstrip line has smallest propagationconstants 边沿耦合微带线具有最小的传播常数68Via Effect 过孔Microstripline viaStripline via69Via Effect signal via couple with power/ground via 换层孔旁加地孔Power / ground vias closed to signal via which will play a role for return current path 信号孔旁的地孔可以提供回流路径Layer 2 and layer3 have same voltage attribute70Right Angle Corner 直角走线Capacitive effect 电容效果 Un continuous impedance 阻抗不连续 Attenuate high frequency signals 高频信号衰减Zo Zo Ccorner45o bends, round and chamfered bends exhibit reduced effects 45o或圆角减小反射71Bends introduce skew 拐角造成偏差Back to back bends compensate for skew 返回拐角控制偏差 72线宽影响73Connector 连接器Connector – to be or not to be? 是否需要 Can you afford 2 connectors (in BP topology)? 添加俩个连接器互连质量是否能够满足要求 Sh ld you fi d a b Should find better connector? 是否有更好的连接器 ?74Measurements of Gbps Signals -Connector Via Discontinuity 连接器造成的阻抗不连续75Cross talk2MM connector列列列列列列列列 1 2 3 4 5 6 7 8连接器串扰分析2MM连接器屏蔽行 A 行 B 行 C 行 D 行 E 行 F 行 G 行 H 屏蔽地地地 + - 地 + - 地 + - 地地 + - 地 + - 地 + - 地地 + - 地 + - 地 + - 地地 + - 地 + - 地 + - 地地 + - 地 + - 地 + - 地地+ - 地 + - 地 + - 地地 + - 地 + - 地 + - 地地 + - 地 + - 地+ - 地仿真上升沿为150PS,摆幅为400MV的LVDS信号激励,远端最大串扰85MV76Cross talk连接器串扰分析 (继续)HS3连接器HS3 connector仿真上升沿为150PS,摆幅为400MV的LVDS信号激励,远端最大串扰12MV77Pre-Emphasis 预加重 (I)Time and Frequency Domain of Square wave (50% duty cycle) 观察50%占空比方波的时域频域 A finite-edge-rate square wavewith 50% duty cycle contains harmonic f h i frequency components at (frequency), 3*(frequency), t t (f ) 3*(f ) 5*(frequency), etc. 50%占空比方波的频域只包含奇次谐波Time DomainFrequency Domain78Pre-Emphasis 预加重(II)A wave with 25%/75% Duty Cycle 观察占空比25%/75%的波形This now changes the distribution of energy in the frequency "bins" 频谱分布变化了Time DomainFrequency Domain79Pre-Emphasis 预加重 (III)Combine the above two waveforms 上面两个波形叠加观察Time DomainFrequency DomainBy boosting the spectral distribution at the harmonics, you can reduce loss effects through pre-emphasis 增强了奇次谐波的能量分布, 改善损耗影响 Key Concept of Pre-emphasis: redistributing the energy of the driven waveform in the frequency domain to combat losses at certain frequencies, by selectively increasing the time domain drive strength 增强了某些频率点的能量, 可以有选择的提高时域驱动能力80Pre-Emphasis预加重(IV)High-frequencyLoss profile of lengthy backplane PCB trace 损耗曲线观察Total loss (dB) ( losses edge degradationFrequency (Hz)Xfer Function of pre-emphasis signal C = Sum of trace loss and pre-emphasis signalTotal loss (dB)Frequency (Hz)Diagrams courtesy Mindspeed,/io_shoot_mindspeed.pdfTotal loss (dB)Frequency (Hz)81Pre-Emphasis预加重 (V)Pre-emphasis not limited to "one boost"不仅限于" one boost" Multi tap Multi-tap enables strengthening of several frequencies to different levels 多抽头增强了更多频率点的能量 Time DomainFrequency Domain82Complex-IO Devices IO接口Pre-emphasis预加重/De-emphasis去加重Emphasis (t) = Input (t 1) (t-1) Main (+ & -) Input stimulus pattern 1000 1000 0111 0111 TX+ Pad 1000 1000 TX- Pad 0111 0111 Emphasis X011 1011 stimulus ti l X100 0100 patternin concert in oppositionBoost (+ & -)83测试案例A Pre-emphasis example. 预加重测试例子84Inter-Symbol Interference (ISI) 码间干扰1Data bit is sent 数据位传输 Before the previous bit is received, the next bit is sent 在前一位接收前, 下一位已发出When each bit reaches the end of the net, some portion will be reflected if not perfectly terminated 阻抗不匹配会产生反射Reflections propagate back towards (and reflect off of) the driver and can interfere with subsequent bits, especially if many receivers are on the line 反射会影响下面正在传输的数据位 Signal Reflection23485Interconnect Storage Potential 互连能量存储Unique for each interconnect 每个互连结构都存在Measures how long a bit's energy stays in link 测试一个bit 的能量可以持续多久 Can be measured from pulse response 可以通过脉冲响应得到 Directly related to how many bits you need to simulate 指导需要多少位传输能够看到全部情况ISP86Process1.步骤Determine the Interconnect's Storage Potential (ISP) 确定ISP the time for a pulse to decay 脉冲响应的衰减时间 2. Calculate the relevant preamble size (bit times) within the ISP 计算ISP时间内信号可以传输多少位 preamble = ISP / bit_time bit variations prior to the preamble are not likely to affect eye height 在之外的数据位不会影响现在传输的数据 3. Determine how many bits may need to be run to address preamblevariations 估算需要分析多少位 #bits = (preamble) * 2 (preamble)= (ISP *Gbps)*2 (ISP*Gbps) encoding schemes may reduce thi value 特定的编码可以大大减小需要的位 di h d this l 数 4. Simulate or measure this # bits in your channel 分析或测试足够的数据位87Stress Test the Design with LARGE Bit Streams 设计需要分析足够多位数Examine channel's Interconnect Storage Potential (ISP) for insight on length of required bit stream 分析ISP 造成的ISI 影响 q 分析造成的影响 Run high-capacity channel simulations, inspect eye diagrams 观察眼图 Examine the jitter 得到抖动 Examine the bit error rate 得到误码率88CA Mathematical Method 通道分析技术BIT PATTERN FFT iFFT FFTNOT typical circuit simulation 不是常规电路分析方法Requires characterization of interconnect (its "fingerprint") 需要先分析互连的脉冲响应 Techniques have been used in other disciplines for years 这个技术已经应用于其他方面 But new to digital PCB signal integrity 但是对板级分析来说是新引进的分析技术 89Time domain incorporates with frequency domain analysis Frequency domain 频域分析S21 = insertion loss Signal energy dissipated during the transmission, lower value imply higher loss S21 传输损耗 S11 = return loss Reflected i R fl t d signal d t i l due to impedance d Mismatch, lower value imply smaller reflection better SI S11 反射损耗90BER (Bit error rate) 误码率91Bath Tub浴盆曲线928b/10b Encoding 8b/10b编码8b/10b 8b/10b编码 Input: A standard 8 bit long word 输入: 8位数据 Output: 10 bit long data block 输出: 10位数据Originated with IBM 起源于IBM Patent: Widmer & Franaszek, September 1983 Standard means of encoding data in SerDes 串行传输编码标准 GbE, PCIe, S-ATA, etc10 bit 8 bit control938b/10b EncoderData SerializerSerial InterfacePurpose目的限制码型8b/10b limits data pattern permutationsInput: 256 possible data or 256 possible control 输入: 256种可能 Output: 1024 possible data or 1024 possible control 输出:1024种可能 512 permitted data (256 positive, 256 negative) 实际允许512种 24 permitted control (12 positive, 12 negative) 24种允许控制码型Limitation based on DC balance好的直流偏置Consecutive, identical bits tightly bounded, only three variations in any 10 bit block are allowed. 任一10位数据, 只允许下面三种连续传输码码型里有5个1和5个0 Five "1" and five "0" Four "1" and six "0" 码型里有4个1和6个0 码型里有6个1和4个0 Six "1" and four "0"For example,举例1 0 1 0 1 0 1 0 1 0: VALID – Five "1" and five "0" 1 0 1 0 0 0 1 0 1 0 0 0: INVALID – Seven "0" and three "1"94Purpose Cont'd目的(继续)Assures DC balance of interface 直流偏置Examples – imagine 1000 cycles of the following: 1000位码型 1 0 1 0 1 0 1 0 1 0: common mode is 0.5*Swing 是数据波动电压的一半是数据波动电压的半 0 1 1 1 1 1 1 1 1 0: common mode "drifts up" 会偏上 1 0 0 0 0 0 0 1 0 0: common mode "drifts down" 会偏下 Many SerDes buses limit the common mode. 高速串行传输对共模电压有要求DC Balance vs. Input Thresholds No Balance vs. Thresholds 95Key Concepts关键点Disparity 不均等性 What is the "trend" of the data bits so far? 描述数据趋势More "1" than "0"? Disparity is positive 1比0多, 不均等性为正 More "0" than "1"? Disparity is negative 0比1多, 不均等性为负 Otherwise, neutral disparity 否则为0All input patterns have "twin" outputs 每种输入对应正负两种输出 Example: 0 0 0 0 0 0 0 0 Positive: 1001110100 Negative: 0110001011 Disparity changes to preserve DC balance 根据不均等性结果控制输出码型保证直流均衡 If incoming disparity is positive, negative output used 不均等性为正, 输出负码型 If incoming disparity is negative, positive output used 不均等性为负, 输出正码型96Implementation应用8b/10b actually 3b/4b + 5b/6b 实际是3b/4b + 5b/6b 编码Previous data stream's disparity need be taken into account 前面数据位的不均等性要考虑进去 5b/6b output disparity affects 3b/4b disparity 5b/6b编码输出的不均等性影响3b/4b编码的不均等性 This ensures no more than 5 consecutive identical bits 保证不超过5位相同位传输6 bit Error and Disp. Check Serial Interface5b/6b Encoder 8 bit 3b/4b Encoder control4 bitData D t Serializer97Input Pattern Name输入码型名称Input pattern name is used to describe the input 8 bit data 描述8位输入码 Zx.y, where Z is control or data (D for Data, K for control), x.y is input bit stream Zx.y形式, Z位D或K, 表示数据或控制码, x.y表述输入码流 Bits [4:0] (E:A) are converted to decimal 低五位用十进制表示 Example: 00111 for (E:A) -> 7 Therefore, 00111 as data would be D7.x Bits [7:5] (H:F) are converted to decimal and added after "." 高三位用十进制表示, 放在码型名称的"."后面 Example: 001 for (H:F) -> 1 Therefore, 00100111 -> D7.1 Favorite patterns for simulation 仿真分析常用码型 K28.5: 10111100, high ISI D10.5: 10101010, highest frequency D11.4 + D3.0: 1000101100000011, "lone-bit" worst-case ISI possible98Example举例99。

高速PCB设计指南之一第一篇PCB布线在PCB设计中，布线是完成产品设计的重要步骤，可以说前面的准备工作都是为它而做的，在整个PCB中，以布线的设计过程限定最高，技巧最细、工作量最大。

PCB布线有单面布线、双面布线及多层布线。

布线的方式也有两种：自动布线及交互式布线，在自动布线之前，可以用交互式预先对要求比较严格的线进行布线，输入端与输出端的边线应避免相邻平行，以免产生反射干扰。

必要时应加地线隔离，两相邻层的布线要互相垂直，平行容易产生寄生耦合。

自动布线的布通率，依赖于良好的布局，布线规则可以预先设定，包括走线的弯曲次数、导通孔的数目、步进的数目等。

一般先进行探索式布经线，快速地把短线连通，然后进行迷宫式布线，先把要布的连线进行全局的布线路径优化，它可以根据需要断开已布的线。

并试着重新再布线，以改进总体效果。

对目前高密度的PCB设计已感觉到贯通孔不太适应了，它浪费了许多宝贵的布线通道，为解决这一矛盾，出现了盲孔和埋孔技术，它不仅完成了导通孔的作用，还省出许多布线通道使布线过程完成得更加方便，更加流畅，更为完善，PCB 板的设计过程是一个复杂而又简单的过程，要想很好地掌握它，还需广大电子工程设计人员去自已体会，才能得到其中的真谛。

1 电源、地线的处理既使在整个PCB板中的布线完成得都很好，但由于电源、地线的考虑不周到而引起的干扰，会使产品的性能下降，有时甚至影响到产品的成功率。

所以对电、地线的布线要认真对待，把电、地线所产生的噪音干扰降到最低限度，以保证产品的质量。

对每个从事电子产品设计的工程人员来说都明白地线与电源线之间噪音所产生的原因，现只对降低式抑制噪音作以表述：（1）、众所周知的是在电源、地线之间加上去耦电容。

（2）、尽量加宽电源、地线宽度，最好是地线比电源线宽，它们的关系是：地线＞电源线＞信号线，通常信号线宽为：0.2～0.3mm,最经细宽度可达0.05～0.07mm,电源线为1.2～2.5 mm对数字电路的PCB可用宽的地导线组成一个回路, 即构成一个地网来使用(模拟电路的地不能这样使用)（3）、用大面积铜层作地线用,在印制板上把没被用上的地方都与地相连接作为地线用。

图1 近年来IC封装的发展为什么如此多的失败呢？自己设计时有把握一次成功吗？信号完整性是指信号在信号线上的质量。

反射就是信号在传输线上的回波。

两管脚短路时的发端、收端信号仿真波形在高速电路中，信号以电磁波的速度在信号线上传容、分布电感的复杂网络，其模型如下图。

实际的传输线模型特性阻抗是传输线理论中最常用也是最重要微带传输线结构图微带传输线的特性阻抗：带状传输线结构图图3 带状传输线结构图带状传输线特性阻抗：带状差分线-1≤ρ并行端接主要是在尽量靠近负载端的位置加上拉和/或下拉阻抗以阻抗匹配与端接技术方案随着互联长度和电路中逻辑器件的家族不同也会有所不同，只有针对具体情况，串扰是指当信号在传输线上传播时，因电磁耦合对相邻的传输线产生的不期望的信号噪声干扰。

过大的串扰可能引性耦合引发耦合电压。

其等效电路如下：两条耦合线的等效模型PCB板层的参数、信号线间距、驱动端和接收端的电气特性及线端接方式对串扰都有一定的影响。

由于芯片封装与电源平面间的寄生电感和电阻建立时间（setup time）是指在触发器的时钟信号上升沿到来以前，数1 Clock Driver输出的时对于控制线要求满足下列条件才能保证正确读写建立时间应满足：t对于数据线要求满足下列条件才能保证正确读读t ClockRouteDelay电磁兼容性（电磁兼容性的要素去耦电容去耦电容的布置回流路径根据克希霍夫定律得出根据法拉第感应定律得出采取有效措施将信号的反射、串扰、单调性、上冲、下冲、振铃和地弹抑制在允许的范围之内，以保证信采取这些措施的效果怎样？于是出现了许多这方面的工具软件。

CADENCE的PSD软件包就是一套业界领先的进行高速PCB设计的EDA工具。

高速数字电路设计与实现•高速数字电路简介•信号完整性•电路的调试与测试•电路板级设计1、电路板级设计流程•创造一个电路板或系统级的电子产品设计的主要步骤有：–概念（concept）：定义技术需求、描述系统行为和决定设计的整体结构–原理图设计（schematic capture）：通过描述产品功能来获得设计原理图–板图设计（layout）阶段包含确定电路板上器件的最优布局和布线，还需要考虑用于多个电路板之间连接的电缆或者连接器的数量–制造（manufacture）和发布2、设计流程中的仿真验证•电路板传统的设计方式是设计然后建立一个物理（硬件）原型，把它放在测试工作台上进行调试直至可以工作•现在对系统工程师和布局布线工程师来说有许多可用的计算机辅助（computer-aided）仿真验证和分析工具。

2、设计流程中的仿真验证2、设计流程中的仿真验证•*模拟信号仿真，*混合信号仿真•*可制造性设计(DFM)•*射频(RF)•*设计规则检查(DRC)•*数字信号仿真•*信号完整性(SI)•*电气规则检查(ERC)•*焊接/热剖析(profile)•*电磁兼容性(EMC)*电磁干扰(EMI)•*热•*时序•*机械特性（振动、冲击、受压），*可靠性2、设计流程中的仿真验证•仿真模型包括–数字器件的VHDL，Verilog，C模型；–器件驱动和负载的IBIS模型；电源开关–放大器，稳压器，二极管和三极管，混合信号模／数转化器和比较器的SPICE模型–VHDL-AMS（混合信号，IEEE1076.1）–Verilog-A（模拟）和Verilog AMS（混合信号）3、通用信号处理机设计•指导思想–标准化–模块化–可重构–可配置–可编程–易开发3.1 系统设计的目标•基于标准总线的通用信息处理机•多处理器并行系统•“异构处理器的通用结构”•高速数据传输能力•标准化、模块化、可扩展•具有二次开发能力软硬件系统3.2 系统总线设计•以C-PCI标准总线技术为基础，配以高速数据传输总线、精确定时总线、以太网的4套总线相结合的并行处理机方案。