SUBSTRATE STRUCTURE FOR GROWTH OF HIGHLY ORIENTED AND EPITAXIAL LAYERSTHEREON

碳化硅衬底核心要素英文回答：The core elements of a silicon carbide substrate can be summarized as follows:1. Material Properties: Silicon carbide (SiC) is a compound semiconductor material known for its excellent thermal conductivity, high breakdown electric field strength, and wide bandgap. These properties make SiC a suitable choice for high-power and high-temperature applications.For example, SiC substrates are widely used in power electronic devices such as MOSFETs and Schottky diodes. The high thermal conductivity of SiC allows for efficient heat dissipation, while the wide bandgap enables the devices to operate at higher voltages and temperatures.2. Crystal Structure: SiC can exist in differentpolytypes, with the most common ones being 4H-SiC and 6H-SiC. The crystal structure of SiC influences its electrical and optical properties. For instance, the 4H-SiC polytype is often preferred for high-power applications due to its higher electron mobility.3. Substrate Quality: The quality of the SiC substrate is crucial for device performance. It includes factors such as crystal defects, surface roughness, and doping levels. High-quality SiC substrates are essential to ensure the reliability and efficiency of the devices fabricated on them.For example, a low defect density in the SiC substrate can lead to higher breakdown voltage and lower leakage current in power devices. Smooth surface morphology is also important for the growth of epitaxial layers and the integration of other materials.4. Epitaxial Growth: Epitaxy refers to the deposition of a crystalline layer on a substrate with a similarcrystal structure. In SiC technology, epitaxial growth iscommonly used to create a thin layer with specific doping and thickness requirements.For example, SiC epitaxial layers can be grown on SiC substrates to create a p-n junction for diode applications. The epitaxial layer can be doped with impurities to achieve the desired electrical characteristics.中文回答：碳化硅衬底的核心要素可以总结如下：1. 材料特性，碳化硅（SiC）是一种复合半导体材料，以其优异的热导率、高击穿电场强度和宽禁带宽度而闻名。

Semiconductor Manufacturing Technology半导体制造技术Instructor’s ManualMichael QuirkJulian SerdaCopyright Prentice HallTable of Contents目录OverviewI. Chapter1. Semiconductor industry overview2. Semiconductor materials3. Device technologies—IC families4. Silicon and wafer preparation5. Chemicals in the industry6. Contamination control7. Process metrology8. Process gas controls9. IC fabrication overview10. Oxidation11. Deposition12. Metallization13. Photoresist14. Exposure15. Develop16. Etch17. Ion implant18. Polish19. Test20. Assembly and packagingII. Answers to End-of-Chapter Review QuestionsIII. Test Bank (supplied on diskette)IV. Chapter illustrations, tables, bulleted lists and major topics (supplied on CD-ROM)Notes to Instructors:1)The chapter overview provides a concise summary of the main topics in each chapter.2)The correct answer for each test bank question is highlighted in bold. Test bankquestions are based on the end-of-chapter questions. If a student studies the end-of-chapter questions (which are linked to the italicized words in each chapter), then they will be successful on the test bank questions.2Chapter 1Introduction to the Semiconductor Industry Die:管芯 defective:有缺陷的Development of an Industry•The roots of the electronic industry are based on the vacuum tube and early use of silicon for signal transmission prior to World War II. The first electronic computer, the ENIAC, wasdeveloped at the University of Pennsylvania during World War II.•William Shockley, John Bardeen and Walter Brattain invented the solid-state transistor at Bell Telephone Laboratories on December 16, 1947. The semiconductor industry grew rapidly in the 1950s to commercialize the new transistor technology, with many early pioneers working inSilicon Valley in Northern California.Circuit Integration•The first integrated circuit, or IC, was independently co-invented by Jack Kilby at Texas Instruments and Robert Noyce at Fairchild Semiconductor in 1959. An IC integrates multiple electronic components on one substrate of silicon.•Circuit integration eras are: small scale integration (SSI) with 2 - 50 components, medium scale integration (MSI) with 50 – 5k components, large scale integration (LSI) with 5k to 100kcomponents, very large scale integration (VLSI) with 100k to 1M components, and ultra large scale integration (ULSI) with > 1M components.1IC Fabrication•Chips (or die) are fabricated on a thin slice of silicon, known as a wafer (or substrate). Wafers are fabricated in a facility known as a wafer fab, or simply fab.•The five stages of IC fabrication are:Wafer preparation: silicon is purified and prepared into wafers.Wafer fabrication: microchips are fabricated in a wafer fab by either a merchant chip supplier, captive chip producer, fabless company or foundry.Wafer test: Each individual die is probed and electrically tested to sort for good or bad chips.Assembly and packaging: Each individual die is assembled into its electronic package.Final test: Each packaged IC undergoes final electrical test.•Key semiconductor trends are:Increase in chip performance through reduced critical dimensions (CD), more components per chip (Moore’s law, which predicts the doubling of components every 18-24 months) andreduced power consumption.Increase in chip reliability during usage.Reduction in chip price, with an estimated price reduction of 100 million times for the 50 years prior to 1996.The Electronic Era•The 1950s saw the development of many different types of transistor technology, and lead to the development of the silicon age.•The 1960s were an era of process development to begin the integration of ICs, with many new chip-manufacturing companies.•The 1970s were the era of medium-scale integration and saw increased competition in the industry, the development of the microprocessor and the development of equipment technology. •The 1980s introduced automation into the wafer fab and improvements in manufacturing efficiency and product quality.•The 1990s were the ULSI integration era with the volume production of a wide range of ICs with sub-micron geometries.Career paths•There are a wide range of career paths in semiconductor manufacturing, including technician, engineer and management.2Chapter 2 Characteristics of Semiconductor MaterialsAtomic Structure•The atomic model has three types of particles: neutral neutrons（不带电的中子）, positively charged protons（带正电的质子）in the nucleus and negatively charged electrons（带负电的核外电子） that orbit the nucleus. Outermost electrons are in the valence shell, and influence the chemical and physical properties of the atom. Ions form when an atom gains or loses one or more electrons.The Periodic Table•The periodic table lists all known elements. The group number of the periodic table represents the number of valence shell electrons of the element. We are primarily concerned with group numbers IA through VIIIA.•Ionic bonds are formed when valence shell electrons are transferred from the atoms of one element to another. Unstable atoms (e.g., group VIIIA atoms because they lack one electron) easily form ionic bonds.•Covalent bonds have atoms of different elements that share valence shell electrons.3Classifying Materials•There are three difference classes of materials:ConductorsInsulatorsSemiconductors•Conductor materials have low resistance to current flow, such as copper. Insulators have high resistance to current flow. Capacitance is the storage of electrical charge on two conductive plates separated by a dielectric material. The quality of the insulation material between the plates is the dielectric constant. Semiconductor materials can function as either a conductor or insulator.Silicon•Silicon is an elemental semiconductor material because of four valence shell electrons. It occurs in nature as silica and is refined and purified to make wafers.•Pure silicon is intrinsic silicon. The silicon atoms bond together in covalent bonds, which defines many of silicon’s properties. Silicon atoms bond together in set, repeatable patterns, referred to asa crystal.•Germanium was the first semiconductor material used to make chips, but it was soon replaced by silicon. The reasons for this change are:Abundance of siliconHigher melting temperature for wider processing rangeWide temperature range during semiconductor usageNatural growth of silicon dioxide•Silicon dioxide (SiO2) is a high quality, stable electrical insulator material that also serves as a good chemical barrier to protect silicon from external contaminants. The ability to grow stable, thin SiO2 is fundamental to the fabrication of Metal-Oxide-Semiconductor (MOS) devices. •Doping increases silicon conductivity by adding small amounts of other elements. Common dopant elements are from trivalent, p-type Group IIIA (boron) and pentavalent, n-type Group VA (phosphorus, arsenic and antimony).•It is the junction between the n-type and p-type doped regions (referred to as a pn junction) that permit silicon to function as a semiconductor.4Alternative Semiconductor Materials•The alternative semiconductor materials are primarily the compound semiconductors. They are formed from Group IIIA and Group VA (referred to as III-V compounds). An example is gallium arsenide (GaAs).•Some alternative semiconductors come from Group IIA and VIA, referred to as II-VI compounds. •GaAs is the most common III-V compound semiconductor material. GaAs ICs have greater electron mobility, and therefore are faster than ICs made with silicon. GaAs ICs also have higher radiation hardness than silicon, which is better for space and military applications. The primary disadvantage of GaAs is the lack of a natural oxide.5Chapter 3Device TechnologiesCircuit Types•There are two basic types of circuits: analog and digital. Analog circuits have electrical data that varies continuously over a range of voltage, current and power values. Digital circuits have operating signals that vary about two distinct voltage levels – a high and a low.Passive Component Structures•Passive components such as resistors and capacitors conduct electrical current regardless of how the component is connected. IC resistors are a passive component. They can have unwanted resistance known as parasitic resistance. IC capacitor structures can also have unintentional capacitanceActive Component Structures•Active components, such as diodes and transistors can be used to control the direction of current flow. PN junction diodes are formed when there is a region of n-type semiconductor adjacent to a region of p-type semiconductor. A difference in charge at the pn junction creates a depletion region that results in a barrier voltage that must be overcome before a diode can be operated. A bias voltage can be configured to have a reverse bias, with little or no conduction through the diode, or with a forward bias, which permits current flow.•The bipolar junction transistor (BJT) has three electrodes and two pn junctions. A BJT is configured as an npn or pnp transistor and biased for conduction mode. It is a current-amplifying device.6• A schottky diode is formed when metal is brought in contact with a lightly doped n-type semiconductor material. This diode is used in faster and more power efficient BJT circuits.•The field-effect transistor (FET), a voltage-amplifying device, is more compact and power efficient than BJT devices. A thin gate oxide located between the other two electrodes of the transistor insulates the gate on the MOSFET. There are two categories of MOSFETs, nMOS (n-channel) and pMOS (p-channel), each which is defined by its majority current carriers. There is a biasing scheme for operating each type of MOSFET in conduction mode.•For many years, nMOS transistors have been the choice of most IC manufacturers. CMOS, with both nMOS and pMOS transistors in the same IC, has been the most popular device technology since the early 1980s.•BiCMOS technology makes use of the best features of both CMOS and bipolar technology in the same IC device.•Another way to categorize FETs is in terms of enhancement mode and depletion mode. The major different is in the way the channels are doped: enhancement-mode channels are doped opposite in polarity to the source and drain regions, whereas depletion mode channels are doped the same as their respective source and drain regions.Latchup in CMOS Devices•Parasitic transistors can create a latchup condition(???????) in CMOS ICs that causes transistors to unintentionally（无心的） turn on. To control latchup, an epitaxial layer is grown on the wafer surface and an isolation barrier（隔离阻障）is placed between the transistors. An isolation layer can also be buried deep below the transistors.Integrated Circuit Productsz There are a wide range of semiconductor ICs found in electrical and electronic products. This includes the linear IC family, which operates primarily with anal3og circuit applications, and the digital IC family, which includes devices that operate with binary bits of data signals.7Chapter 4Silicon and Wafer Preparation8z Semiconductor-Grade Silicon•The highly refined silicon used for wafer fabrication is termed semiconductor-grade silicon (SGS), and sometimes referred to as electronic-grade silicon. The ultra-high purity of semiconductor-grade silicon is obtained from a multi-step process referred to as the Siemens process.Crystal Structure• A crystal is a solid material with an ordered, 3-dimensional pattern over a long range. This is different from an amorphous material that lacks a repetitive structure.•The unit cell is the most fundamental entity for the long-range order found in crystals. The silicon unit cell is a face-centered cubic diamond structure. Unit cells can be organized in a non-regular arrangement, known as a polycrystal. A monocrystal are neatly arranged unit cells.Crystal Orientation•The orientation of unit cells in a crystal is described by a set of numbers known as Miller indices.The most common crystal planes on a wafer are (100), (110), and (111). Wafers with a (100) crystal plane orientation are most common for MOS devices, whereas (111) is most common for bipolar devices.Monocrystal Silicon Growth•Silicon monocrystal ingots are grown with the Czochralski (CZ) method to achieve the correct crystal orientation and doping. A CZ crystal puller is used to grow the silicon ingots. Chunks of silicon are heated in a crucible in the furnace of the puller, while a perfect silicon crystal seed is used to start the new crystal structure.• A pull process serves to precisely replicate the seed structure. The main parameters during the ingot growth are pull rate and crystal rotation. More homogeneous crystals are achieved with a magnetic field around the silicon melt, known as magnetic CZ.•Dopant material is added to the melt to dope the silicon ingot to the desired electrical resistivity.Impurities are controlled during ingot growth. A float-zone crystal growth method is used toachieve high-purity silicon with lower oxygen content.•Large-diameter ingots are grown today, with a transition underway to produce 300-mm ingot diameters. There are cost benefits for larger diameter wafers, including more die produced on a single wafer.Crystal Defects in Silicon•Crystal defects are interruptions in the repetitive nature of the unit cell. Defect density is the number of defects per square centimeter of wafer surface.•Three general types of crystal defects are: 1) point defects, 2) dislocations, and 3) gross defects.Point defects are vacancies (or voids), interstitial (an atom located in a void) and Frenkel defects, where an atom leaves its lattice site and positions itself in a void. A form of dislocation is astacking fault, which is due to layer stacking errors. Oxygen-induced stacking faults are induced following thermal oxidation. Gross defects are related to the crystal structure (often occurring during crystal growth).Wafer Preparation•The cylindrical, single-crystal ingot undergoes a series of process steps to create wafers, including machining operations, chemical operations, surface polishing and quality checks.•The first wafer preparation steps are the shaping operations: end removal, diameter grinding, and wafer flat or notch. Once these are complete, the ingot undergoes wafer slicing, followed by wafer lapping to remove mechanical damage and an edge contour. Wafer etching is done to chemically remove damage and contamination, followed by polishing. The final steps are cleaning, wafer evaluation and packaging.Quality Measures•Wafer suppliers must produce wafers to stringent quality requirements, including: Physical dimensions: actual dimensions of the wafer (e.g., thickness, etc.).Flatness: linear thickness variation across the wafer.Microroughness: peaks and valleys found on the wafer surface.Oxygen content: excessive oxygen can affect mechanical and electrical properties.Crystal defects: must be minimized for optimum wafer quality.Particles: controlled to minimize yield loss during wafer fabrication.Bulk resistivity(电阻系数): uniform resistivity from doping during crystal growth is critical. Epitaxial Layer•An epitaxial layer (or epi layer) is grown on the wafer surface to achieve the same single crystal structure of the wafer with control over doping type of the epi layer. Epitaxy minimizes latch-up problems as device geometries continue to shrink.Chapter 5Chemicals in Semiconductor FabricationEquipment Service Chase Production BayChemical Supply Room Chemical Distribution Center Holding tank Chemical drumsProcess equipmentControl unit Pump Filter Raised and perforated floorElectronic control cablesSupply air ductDual-wall piping for leak confinement PumpFilterChemical control and leak detection Valve boxes for leak containment Exhaust air ductStates of Matter• Matter in the universe exists in 3 basic states (宇宙万物存在着三种基本形态): solid, liquid andgas. A fourth state is plasma.Properties of Materials• Material properties are the physical and chemical characteristics that describe its unique identity.• Different properties for chemicals in semiconductor manufacturing are: temperature, pressure andvacuum, condensation, vapor pressure, sublimation and deposition, density, surface tension, thermal expansion and stress.Temperature is a measure of how hot or cold a substance is relative to another substance. Pressure is the force exerted per unit area. Vacuum is the removal of gas molecules.Condensation is the process of changing a gas into a liquid. Vaporization is changing a liquidinto a gas.Vapor pressure is the pressure exerted by a vapor in a closed container at equilibrium.Sublimation is the process of changing a solid directly into a gas. Deposition is changing a gas into a solid.Density is the mass of a substance divided by its volume.Surface tension of a liquid is the energy required to increase the surface area of contact.Thermal expansion is the increase in an object’s dimension due to heating.Stress occurs when an object is exposed to a force.Process Chemicals•Semiconductor manufacturing requires extensive chemicals.• A chemical solution is a chemical mixture. The solvent is the component of the solution present in larger amount. The dissolved substances are the solutes.•Acids are solutions that contain hydrogen and dissociate in water to yield hydronium ions. A base is a substance that contains the OH chemical group and dissociates in water to yield the hydroxide ion, OH-.•The pH scale is used to assess the strength of a solution as an acid or base. The pH scale varies from 0 to 14, with 7 being the neutral point. Acids have pH below 7 and bases have pH values above 7.• A solvent is a substance capable of dissolving another substance to form a solution.• A bulk chemical distribution (BCD) system is often used to deliver liquid chemicals to the process tools. Some chemicals are not suitable for BCD and instead use point-of-use (POU) delivery, which means they are stored and used at the process station.•Gases are generally categorized as bulk gases or specialty gases. Bulk gases are the relatively simple gases to manufacture and are traditionally oxygen, nitrogen, hydrogen, helium and argon.The specialty gases, or process gases, are other important gases used in a wafer fab, and usually supplied in low volume.•Specialty gases are usually transported to the fab in metal cylinders.•The local gas distribution system requires a gas purge to flush out undesirable residual gas. Gas delivery systems have special piping and connections systems. A gas stick controls the incoming gas at the process tool.•Specialty gases may be classified as hydrides, fluorinated compounds or acid gases.Chapter 6Contamination Control in Wafer FabsIntroduction•Modern semiconductor manufacturing is performed in a cleanroom, isolated from the outside environment and contaminants.Types of contamination•Cleanroom contamination has five categories: particles, metallic impurities, organic contamination, native oxides and electrostatic discharge. Killer defects are those causes of failure where the chip fails during electrical test.Particles: objects that adhere to a wafer surface and cause yield loss. A particle is a killer defect if it is greater than one-half the minimum device feature size.Metallic impurities: the alkali metals found in common chemicals. Metallic ions are highly mobile and referred to as mobile ionic contaminants (MICs).Organic contamination: contains carbon, such as lubricants and bacteria.Native oxides: thin layer of oxide growth on the wafer surface due to exposure to air.Electrostatic discharge (ESD): uncontrolled transfer of static charge that can damage the microchip.Sources and Control of Contamination•The sources of contamination in a wafer fab are: air, humans, facility, water, process chemicals, process gases and production equipment.Air: class number designates the air quality inside a cleanroom by defining the particle size and density.Humans: a human is a particle generator. Humans wear a cleanroom garment and follow cleanroom protocol to minimize contamination.Facility: the layout is generally done as a ballroom (open space) or bay and chase design.Laminar airflow with air filtering is used to minimize particles. Electrostatic discharge iscontrolled by static-dissipative materials, grounding and air ionization.Ultrapure deiniozed (DI) water: Unacceptable contaminants are removed from DI water through filtration to maintain a resistivity of 18 megohm-cm. The zeta potential represents a charge on fine particles in water, which are trapped by a special filter. UV lamps are used for bacterial sterilization.Process chemicals: filtered to be free of contamination, either by particle filtration, microfiltration (membrane filter), ultrafiltration and reverse osmosis (or hyperfiltration).Process gases: filtered to achieve ultraclean gas.Production equipment: a significant source of particles in a fab.Workstation design: a common layout is bulkhead equipment, where the major equipment is located behind the production bay in the service chase. Wafer handling is done with robotic wafer handlers. A minienvironment is a localized environment where wafers are transferred on a pod and isolated from contamination.Wafer Wet Cleaning•The predominant wafer surface cleaning process is with wet chemistry. The industry standard wet-clean process is the RCA clean, consisting of standard clean 1 (SC-1) and standard clean 2 (SC-2).•SC-1 is a mixture of ammonium hydroxide, hydrogen peroxide and DI water and capable of removing particles and organic materials. For particles, removal is primarily through oxidation of the particle or electric repulsion.•SC-2 is a mixture of hydrochloric acid, hydrogen peroxide and DI water and used to remove metals from the wafer surface.•RCA clean has been modified with diluted cleaning chemistries. The piranha cleaning mixture combines sulfuric acid and hydrogen peroxide to remove organic and metallic impurities. Many cleaning steps include an HF last step to remove native oxide.•Megasonics(兆声清洗) is widely used for wet cleaning. It has ultrasonic energy with frequencies near 1 MHz. Spray cleaning will spray wet-cleaning chemicals onto the wafer. Scrubbing is an effective method for removing particles from the wafer surface.•Wafer rinse is done with overflow rinse, dump rinse and spray rinse. Wafer drying is done with spin dryer or IPA(异丙醇) vapor dry (isopropyl alcohol).•Some alternatives to RCA clean are dry cleaning, such as with plasma-based cleaning, ozone and cryogenic aerosol cleaning.Chapter 7Metrology and Defect InspectionIC Metrology•In a wafer fab, metrology refers to the techniques and procedures for determining physical and electrical properties of the wafer.•In-process data has traditionally been collected on monitor wafers. Measurement equipment is either stand-alone or integrated.•Yield is the percent of good parts produced out of the total group of parts started. It is an indicator of the health of the fabrication process.Quality Measures•Semiconductor quality measures define the requirements for specific aspects of wafer fabrication to ensure acceptable device performance.•Film thickness is generally divided into the measurement of opaque film or transparent film. Sheet resistance measured with a four-point probe is a common method of measuring opaque films (e.g., metal film). A contour map shows sheet resistance deviations across the wafer surface.•Ellipsometry is a nondestructive, noncontact measurement technique for transparent films. It works based on linearly polarized light that reflects off the sample and is elliptically polarized.•Reflectometry is used to measure a film thickness based on how light reflects off the top and bottom surface of the film layer. X-ray and photoacoustic technology are also used to measure film thickness.•Film stress is measured by analyzing changes in the radius of curvature of the wafer. Variations in the refractive index are used to highlight contamination in the film.•Dopant concentration is traditionally measured with a four-point probe. The latest technology is the thermal-wave system, which measures the lattice damage in the implanted wafer after ion implantation. Another method for measuring dopant concentration is spreading resistance probe. •Brightfield detection is the traditional light source for microscope equipment. An optical microscope uses light reflection to detect surface defects. Darkfield detection examines light scattered off defects on the wafer surface. Light scattering uses darkfield detection to detectsurface particles by illuminating the surface with laser light and then using optical imaging.•Critical dimensions (CDs) are measured to achieve precise control over feature size dimensions.The scanning electron microscope is often used to measure CDs.•Conformal step coverage is measured with a surface profiler that has a stylus tip.•Overlay registration measures the ability to accurately print photoresist patterns over a previously etched pattern.•Capacitance-voltage (C-V) test is used to verify acceptable charge conditions and cleanliness at the gate structure in a MOS device.Analytical Equipment•The secondary-ion mass spectrometry (SIMS) is a method of eroding a wafer surface with accelerated ions in a magnetic field to analyze the surface material composition.•The atomic force microscope (AFM) is a surface profiler that scans a small, counterbalanced tip probe over the wafer to create a 3-D surface map.•Auger electron spectroscopy (AES) measures composition on the wafer surface by measuring the energy of the auger electrons. It identifies elements to a depth of about 2 nm. Another instrument used to identify surface chemical species is X-ray photoelectron spectroscopy (XPS).•Transmission electron microscopy (TEM) uses a beam of electrons that is transmitted through a thin slice of the wafer. It is capable of quantifying very small features on a wafer, such as silicon crystal point defects.•Energy-dispersive spectrometer (EDX) is a widely used X-ray detection method for identifying elements. It is often used in conjunction with the SEM.• A focused ion beam (FIB) system is a destructive technique that focuses a beam of ions on the wafer to carve a thin cross section from any wafer area. This permits analysis of the wafermaterial.Chapter 8Gas Control in Process ChambersEtch process chambers••The process chamber is a controlled vacuum environment where intended chemical reactions take place under controlled conditions. Process chambers are often configured as a cluster tool. Vacuum•Vacuum ranges are low (rough) vacuum, medium vacuum, high vacuum and ultrahigh vacuum (UHV). When pressure is lowered in a vacuum, the mean free path(平均自由行程) increases, which is important for how gases flow through the system and for creating a plasma.Vacuum Pumps•Roughing pumps are used to achieve a low to medium vacuum and to exhaust a high vacuum pump. High vacuum pumps achieve a high to ultrahigh vacuum.•Roughing pumps are dry mechanical pumps or a blower pump (also referred to as a booster). Two common high vacuum pumps are a turbomolecular (turbo) pump and cryopump. The turbo pump is a reliable, clean pump that works on the principle of mechanical compression. The cryopump isa capture pump that removes gases from the process chamber by freezing them.。

表面技术第53卷第5期高温对含氢DLC涂层的微观结构及力学性能的影响贾伟飞1，梁灿棉2，胡锋1,2*（1.武汉科技大学 高性能钢铁材料及其应用省部共建协同创新中心，武汉 430081；2.广东星联精密机械有限公司，广东 佛山 528251）摘要：目的针对含氢DLC涂层热稳定性很差的问题，探究高温下含氢DLC涂层的微观组织变化特征，以及高温对其力学性能的影响。

方法采用等离子体强化化学气相沉积（Plasma Enhanced Chemical Vapor Deposition, PECVD）在S136模具不锈钢表面沉积以Si为过渡层的含氢DLC复合涂层，利用光学显微镜、扫描电镜、拉曼光谱、X射线电子衍射仪、三维轮廓仪研究DLC涂层的微观结构，采用划痕测试仪、往复式摩擦磨损试验机、纳米压痕仪研究DLC涂层的力学性能，并通过LAMMPS软件，利用液相淬火法建立含氢DLC模型，模拟分析经高温处理后涂层的组织变化特征和纳米压痕行为。

结果在400 ℃、2 h的退火条件下，拉曼谱峰强度I D/I G由未退火的0.7增至1.5，涂层发生了石墨化转变，同时基线斜率下降，H元素析出；XPS结果表明，在此条件下涂层中sp2杂化组织相对增加，氧元素增多，涂层粗糙度增大；在600 ℃、2 h退火条件下，DLC发生了严重氧化，LAMMPS模拟结果表明，在400 ℃高温下涂层的分子键长变短，表明sp3杂化组织在高温下吸收能量，并向sp2杂化转变。

纳米压痕模拟结果显示，在400 ℃下退火后，涂层的硬度下降。

结论在400 ℃下退火处理后，涂层中的H元素释放，涂层内应力减小，保证了涂层的强度；在600 ℃退火条件下，过渡层的Si和DLC在高温下形成了C—Si键，使得DLC薄膜部分被保留；LAMMPS 模拟结果表明，在高温下涂层发生了石墨化转变，涂层的硬度减小。

关键词：含氢DLC涂层；退火处理；微观组织；力学性能；LAMMPS模拟中图分类号：TB332 文献标志码：A 文章编号：1001-3660(2024)05-0174-10DOI：10.16490/ki.issn.1001-3660.2024.05.018Effect of High-temperature on Microstructure and MechanicalProperties of Hydrogen-containing DLC CoatingJIA Weifei1, LIANG Canmian2, HU Feng1,2*(1. Collaborative Innovation Center for Advanced Steels, Wuhan University of Science and Technology, Wuhan 430081,China; 2. Guangdong Xinglian Precision Machinery Co., Ltd., Guangdong Foshan 528251, China)ABSTRACT: The thermal stability of hydrogen-containing DLC coating is poor, and the work aims to explore the microstructure changes of hydrogen-containing DLC coating at high temperature and their impact on mechanical properties. The收稿日期：2023-01-09；修订日期：2023-05-18Received：2023-01-09；Revised：2023-05-18基金项目：中国博士后科学基金（2021M700875）Fund：China Postdoctoral Science Foundation (2021M700875)引文格式：贾伟飞, 梁灿棉, 胡锋. 高温对含氢DLC涂层的微观结构及力学性能的影响[J]. 表面技术, 2024, 53(5): 174-183.JIA Weifei, LIANG Canmian, HU Feng. Effect of High-temperature on Microstructure and Mechanical Properties of Hydrogen-containing DLC Coating[J]. Surface Technology, 2024, 53(5): 174-183.*通信作者（Corresponding author）第53卷第5期贾伟飞，等：高温对含氢DLC涂层的微观结构及力学性能的影响·175·hydrogen-containing DLC composite coating with Si as the transitional layer was deposited on the surface of S136 stainless steel by plasma enhanced chemical vapor deposition (PECVD). The microstructure of DLC coating was investigated by optical/scanning electron microscopy, Raman spectroscopy, XPS (X-ray photoelectron spectroscopy) and three-dimensional profiler, the mechanical properties of DLC coating were studied by scratch, reciprocating friction wear and nano-indentation experiment, and the nano-indentation experiment behavior of DLC coating was simulated by LAMMPS to analyze the microstructure characteristics in annealing. The coating was subject to annealing conditions of 400 ℃for 2 hours and 600 ℃for 2 hours. Under the former condition, Raman spectroscopy showed an increase in the intensity ratio of the I D/I G peaks from0.7 to 1.5, indicating graphitization transition, accompanied by a decrease in baseline slope and H element segregation. XPSanalysis revealed an increase in sp2 hybridization and oxygen content in the coating under this condition, as well as an increase in surface roughness. At 600 ℃, severe oxidation of the DLC coating was observed. Under that condition, the matrix stainless steel was also oxidized. Molecular dynamics simulations using LAMMPS suggested a decrease in molecular bond length at 400 ℃high temperature. The three-dimensional profile test showed that the roughness under the unannealed condition was mainly from the large particles produced during deposition. At 400 for 2℃h, the coating had the minimum surface roughness. At this time, some large particles in the coating structure fell off, and the coating was basically completely damaged at 600 for℃ 2 h. The roughness was mainly from the original stainless steel roughness. The scratch test showed that under the condition of 400 for℃2 h, due to the release of the internal stress of the coating and the tighter bonding of the transition layer, the coating had the bestbonding effect with the substrate and was the least likely to fall off. The statistical results of LAMMPS simulation showed that the chemical bonds of the original DLC model tended to become shorter after annealing at high temperature. Relative to the unannealed DLC coating, the mechanical properties of DLC coating were best under 400 for℃ 2 h. Under this condition, the precipitation of mixed H elements in the coating led to the transformation of the original C—H sp3 structure, which occupied a large space to the smaller C—C sp3 and C—C sp2 structure, releasing internal stress in the coating, while ensuring the strength.The nano-indentation experiments showed that the elastic recovery and hardness of the coating were the highest at 400 for℃ 2 h, compared with that at other annealing temperature. The structure of the DLC coating containing hydrogen changed due to the precipitation of H element at 400 ℃. On the one hand, the coating structure changed from sp3 to sp2 due to high temperature, and on the other hand, the precipitation of H element changed the original C—H sp3 to C—C sp3, reducing the internal stress of the coating and improving the mechanical properties. The coating is basically damaged at 600 for 2 h, but the substrate still℃retains part of the coating. This is because the transition layer Si reacts with the coating to improve the heat resistance of the remaining coating. Molecular dynamics simulations using LAMMPS showed that the coating undergoes a graphitization transition at high temperature, leading to a reduction in its hardness.KEY WORDS: hydrogen-containing DLC coating; annealing treatment; microstructure; mechanical properties; LAMMPS simulationDLC（Diamond-Like Carbon，类金刚石碳，简称DLC）涂层材料具有超高硬度、低摩擦因数、优良化学稳定性等特点，广泛应用于机械、电子、生物医学等领域[1-3]。

东京精密株式会社公司简介东京精密株式会社是日本著名半导体制造设备之一,公司总部设在日本东京都三鹰市, 在美国,欧洲,新加坡,中国等地设有分公司,研发基地或生产厂等.We develop our businesses in two key areas: semiconductor manufacturing equipment and precision measuring systems. Our philosophy is to generate long-term growth through the creation of "WIN-WIN," or mutually beneficial, relationships, with all our stakeholders - customers, business partners, shareholders and employees.（公司网站原文）东京精密主要从事半导体加工设备及精密测量仪器制造及开发. 半导体加工设备有硅片加工用地倒角机、内圆切片机, 半导体加工前道工序用的光刻机（LEEPL）、CMP、晶片表面综合检查设备及测试封装用的探针台、划片机、硅片背面抛光机等.过去，东京精密简称“TSK”，在国内半导体行业享有盛誉。

现在东京精密采用了新的商标“ACCRETECH”，她是由英文成长ACCRETE和技术TECHNOLOGY的合成词，是融合公司”以WIN-WIN精神工作，创世界一流产品“经营理念的新标志。

参展产品：硅片材料的内圆切片机、硅片倒角机，光刻机，CMP，硅片表面检查系统，探针台背面减薄抛光机，划片机。

网址：http://www.accretech.jp/Semiconductor Manufacturing Equipment:Product listWafer Manufacturing SystemVariety of products line for wafer manufacturers including Wafer Slicing Machine and Wafer Edge Grinding Machine.Sliced Wafer Carbon Demounting and Cleaning Machine : C-RW-200/300Feature 1Automatic demounting of wafers from the slicing base, cleaning and storing into the cassette.Wafer Edge Grinding: W-GM-5200•Newly-developed grinding unit enhances the rotative precision of the spindle, and improves the surface roughness.•The non-contact measuring method achieves the stable alignment.•Performs the non-contact measuring of the pre-processed wafer thickness at multiple points, the diameter and notch depth of thepost-processed wafer.•The modular concept to make the optimum process line possible.•Low damage grinding method is available.Feature 1Machine specification ready for 300 mm and 200 mm wafer.Feature 2Visual system (optional) for measuring the chamfer width of periphery and notch.Wafer Edge Grinding: W-GM-4200•Newly-developed grinding unit enhances the rotative precision of the spindle, and improves the surface roughness.•The non-contact measuring method achieves the stable alignment.•Performs the non-contact measuring of the pre-processed wafer thickness at multiple points, the diameter and notch depth of thepost-processed wafer.•The modular concept to make the optimum process line possible.•Low damage grinding method is available.Feature 1Machine specification ready for 75 - 150 mm wafer or for 150 - 200 mm wafer. Feature 2Capable of various material processes, such as chemical compound semiconductor.Wafer Slicing Machine: S-LM-116GPrecise slicing machine for fragile materials such as glass, ceramics, ferrite. Feature 116"-size blade for easy handling, lifting and adjustment.Feature 2Open-structure loading unit for easy mounting of the workpiece.Feature 3Easy setting of slicing speed and wafer thickness with digital switch.Feature 4Strong frame, highly rigid table provides long-term stability in performance. Feature 5Easy coolant adjustment and dressing operation.Wafer Slicing Machine: A-WS-100SScribes wafer substrate with high precisionFeature 1Easy alignmentWith fine adjustment in horizontal and rotative directionsFeature 2Easy scribe settingWith the touch panel to set the index amount, number of times of scribing, etc. CMPCMPs remove unevenness on wafer surfaces that occur during the production process. Applications are growing due to the increase of layers in semiconductor devices and the growing variety of wiring materials. ChaMP: For 300mm WafersCombining the technological expertise built up by Accretech in precision measuring equipment and semiconductor manufacturing equipment, we now offer "the ChaMP Series", the CMP systems compatible with 300 mm wafers, with process performance required by design rules for 90 nm and 32 nm devices, and able to keep up with the most advanced volume-production fabs.Feature 1Air-float Head "Sylphide"•Reference polishing is made possible via an air cushion that provides uniform pressure distribution.•Wafer pressure is applied by an airbag independent of ring pressure, providing excellent low-pressure controllability and stability.•Zone control is available.Feature 2Edge Exclusion of 1 mm!Feature 3Wafer Pressure Controllability & RepeatabilityFeature 4Simple Maintenance for Polishing Heads - Ring Change Demounting (approximately 5 seconds)Slide the snap ring cover up with both handsSpread the snap ring with your thumb (the retaining ring drops off)Completely remove the retaining ringMounting (approximately 10 seconds)1. Grip the snap ring with both hands and push the retainer into thecarrier. Rotate it slightly to align the faces where the positioningframe slips into place.2. Attach the snap ring round the whole circumference and slide thecover down.ChaMP: For 150 or 200mm WafersFor 150 or 200mm WafersChaMP: Compact CMP SystemSmall footprintWafer Probing MachinesWafer probing machines perform electrical tests of each chip on a wafer, ensuring the quality of semiconductor devices.Wafer Probing Machines: UF3000EXNext-generation high-spec probing machine the world No.1 supplier presents Phenomenal levels of throughput have been made possible with the synergistic effects of high-speed wafer handling enabled by a new algorithm, and the high-speed and low-noise XY Stage enabled by a newly developed purpose-built drive unit for probes. The Z axis ensures world-class load capacity and high precision, and offers excellent contact via an optimal structural design that employs topology which reliably eliminates changes in flatness due to positioning.With advanced OTS latest positioning system technology and by colorizing wafer alignment imaging and equipping a light super magnification function, the UF3000EX has improved dramatically in terms of precision and operability. Wafer Probing Machines: UF3000EX-eAssimilating the up-to-date technologies such as originative OTS, QPU and TTG, this super high-spec system provides the testing system which meets your needs for the miniaturization of the next-generation devices and various testing environment.Feature 1OTS - the newest positioning technology (Optical Target Scope)OTS enables to measure the relative position of the cameras with absolute accuracy, which improved dramatically.Based on the ACCRETECH metrology technology, OTS enables theself-correlation of the alignment optical system.Feature 2QPU - super high-rigid chucking (Quad-Pod Unit)To effectively attain the accuracy in positioning, the high rigidity of every part is greatly important.The UF3000 uses the new technology of 4 axes driving mechanism (QPU) for Z-axis, enabling the high-rigid, stable probe contact.Feature 3Load-portTesting environment satisfying the users' needs is available by the common platform of 8-inch and 12-inch cassettes and the front allocation of the inspection tray. The machine is also ready for AMHS (Automated Material Handling System).Feature 4TTG (Touch To Go)Pursuing the easy operation, the UF3000 adopts the function to move to the position you touch on the map or image shown on the touch panel. Setting up is easy, and screen configuration is possible by the user definition.Wafer Probing Machine: UF2000Tokyo Seimitsu, now known as Accretech, has continued to lead the semiconductor industry as the world's number one manufacturer of wafer probing machines. The newly developed UF2000 high-precision 200mm wafer prober is designed for devices with decreasing pad pitches typified by LCD drivers and other such devices, and features enhanced functionality in all areas, while offering the same functions and operating ease as the previous model.Feature 1Achieves overall precision of ±1.5µm.Feature 2Adopts new processor, newly designed loader and image processing system with enhanced performance, dramatically boosting throughput.Wafer Probing Machine: UF200REvolving and Proliferating Wafer Probing Machine, UF SeriesBased on a flexible platform, the high accuracy and high rigidity, UF series is further evolved. Wafers are varying with the progress of line width shrinkage and assembly technology. This machine can be used for processing very thin wafers and can be used as a handler for the wafer level burn-in system.Feature 18-inch multipurpose machine.Wafer Probing Machine: UF190REvolving and Proliferating Wafer Probing Machine, UF SeriesBased on a flexible platform, the high accuracy and high rigidity, UF series is further evolved. Wafers are varying with the progress of line width shrinkage and assembly technology. This machine can be used for processing very thin wafers and can be used as a handler for the wafer level burn-in system.Feature 1High-performance, high-throughput, and excellent cost performance machine.Feature 2The UF190A features the same high-performance and excellent operability as the UF200 earned a reputation including the automatic needle alignment function and the color LCD touch panel.Wafer Probing Machine: FP200AEvolving and Proliferating Wafer Probing Machine, UF Series Based on a flexible platform, the high accuracy and high rigidity, UF series is further evolved. Wafers are varying with the progress of line width shrinkage and assembly technology. This machine can be used for processing very thin wafers and can be used as a handler for the wafer level burn-in system. Feature 1Frame transfer ready for the thinner wafer.Wafer Probing Machines Network: VEGANETThe operation status of the wafer probing machines can be centralizedly monitored to further improve the operation rateSystem monitorOperation rate controlProber status monitorData analysisWafer Probing Machines Network: LIGHTVEGAThe resource control will be centralized on the user hostWafer Probing Machines Network: GEM Network SystemWafer Probing Machines Network: VEGA PLANETDedicated terminals contributing to the efficiency enhancement of test areas Feature 1Device data compile terminalFeature 2Remote operation terminalFeature 3Logging data analysis terminalFeature 4Map viewerPolish GrindersPolish grinders simultaneously thin wafers while performing damage removal caused by the grinding process, and offer various applications for peripheral processes in the one system.Polish Grinder: PG3000/PG200PG3000PG200The product of a unique ACCRETECH innovation, this Polish Grinder combines the wafer thinness required for IC cards and three-dimensional mounting technology with damage removal functions in a single device.Feature 1Performs the processes of the rough grinding, fine grinding, polishing and cleaning wafers on the both sides in a single machine.Feature 2All the processes are completed without moving the wafer on the same chuck table.Feature 3The smallest footprint in the worldFeature 4Environmental - friendly - subsurface damage reduction without chemicals. Feature 5System configurationPolish Grinder: PG3000RM/PG200RMPG3000 RM : For 300mm WafersPG200 RM : For 200mm WafersACCRETECH also offers the "RM option", having the additional process of the tape removing for thinner wafer after the tape mounting, in addition to the standard process of PG300/200.Feature 1Optional RM moduleThe RM200/300 offers a single-unit solution supplementing PG200/300 processing with additional functionality to remove protective tape from thinner wafers and apply wafers to dicing frames.Feature 2Performs the processes of the rough grinding, fine grinding, polishing and cleaning wafers on the both sides in a single machine.Feature 3All the processes are completed without moving the wafer on the same chuck table.Feature 4The smallest footprint in the world.Feature 5Environmental - friendly - subsurface damage reduction without chemicals. Feature 6System configurationWafer Dicing MachinesWafer dicing machine cut wafers into individual semiconductor chips with blades. ACCRETECH Laser dicing machines use lasers instead of blades to dicewafers at high speed in a completely dry process.Wafer Dicing Machines：AD3000T/STokyo Seimitsu Wafer Dicing Machine realizes the remarkable “CoO (Cost of Owne rship)” by the world smallest footprint, high throughput, and high processing quality reinforced by the collaboration of theup-to-date technology.Wafer Dicing Machines:A-WD-200THigh throughput achieved by a new conceptThe A-WD-200T uses an opposing, twin spindle arrangement. Thisunique concept minimizes motion and delivers a massive boost inthroughput.Wafer Dicing Machines:A-WD-250SFully automated dicing machine for 8 inch wafer and large-sizedsubstratesWafer Dicing Machines: AD20TRevolutionary axis design orientation creates the smallest twin spindleDicing SawWafer Dicing Machines:A-WD-10BThis multipurpose dicing machine realizes ease of use with theadaptation of the much sought-after space saving factor, slide coversystem and functionmanagement system.Wafer Dicing Machines:PS280Now, with two independent stages, cutting and positioning canproceed in parallel. The result - a maximum dicing speed up to twicethat previously possible!New connected handlers, shorten coordination time - bringingincreased operation efficiency and substantial savings in processingtime.Automatic Cleaning System:A-CS-100AStand-alone wafer cleaning unit, A-CS-100A will provide best solution for cleaning and drying the wafer such as sawn with semi-automaticdicing saws.High-pressure water spray up to 10 MPa driven by horizontal swinging arm will achieve excellent cleaning quality.Wafer Dicing Machines:ML300High performance laser dicing machine for 300 mm wafers with SDE.Wafer Dicing Machines:ML200We have developed a dicing machine equipped with stealth dicingtechnology (developed by Hamamatsu Photonics) as a stealth dicingengine, exhibiting excellent performance.Precision ACCRETECH BladeWith the diamond, the world-hardest substance, super-abrasive grit,we offer the cutting blade and solution that are high quality and costcutting.•Precision ACCRETECH BladeProduct listMeasuring Systems:Product list"No measurement,no manufacturing" - ACCRETECH supplys the best from Multi-perpose measuring to In-line measuring.Automatic Measuring SystemsMachine control gauges control processing machines based on data taken before, during and after operation. This indispensable system is used to prevent defects and boost accuracy in manufacture, thereby raising productivity. We also produce air micrometers, electric micrometers and high-precision sensors.•Machine Control Gauges•Various Sensors and Electric / Air Micrometers•High Precisions Digital Measurement Instrument•Laser Interferometer / Built-in Measuring Instruments•Automatic Measuring SystemsIndustrial Measuring SystemsWe manufacture a variety of high-precision industrial measuring systems, including: 3D Coordinate Measuring Machines, Surface Texture and Contour Measuring Instruments and Cylindrical Form Measuring Instruments.•3D Coordinate Measuring Machines•Surface Texture and Contour Measuring Instruments•Roundness and Cylindrical Profile Measuring Instruments。

descriptionGafchromic ™ HD-V2 film is a radiochromic dosimetry film designed for the quantitative measurement of absorbed dose of high-energy photons. As a self-developing film, HD-V2 is a perfect fit for the processorless environment. Since radiochromic film requires no post-exposure processing, there are no chemicals to dispose of and the film can be handled and used without need of a darkroom.Gafchromic ™ HD-V2 uses a yellow marker dye. When used in conjunction with an rgb film scanner and FilmQA Pro ™ software, the marker dye in HD-V2 film enables all the benefits of multi-channel dosimetry. Using the marker dye feature is not mandatory. You can continue to perform dosimetry using only the red color channel, but you give up all the advantages of the multi-channel method that will make your film dosimetry better.To learn more about FilmQA Pro ™ software and multi-channel film dosimetry, visit https:///industries/medical/filmqa-pro-software .The structure of Gafchromic ™ HD-V2 film is shown in Figure 1. The film is comprised of an active layer , nominally 8μm thick, containing the active component, marker dye, stabilizers and other components giving the film its energy-independent response. The thickness of the active layer may vary slightly from batch-to-batch. The active layer is coated on a clear, 97 μm polyester substrate.self-developing film for the quantitative measurement of absorbed dose of high-energy photonskey features and benefits¢ dynamic dose range: 10 Gy to 1000 Gy¢ develops in real time without post-exposure treatment ¢ energy-dependence: minimal response differencefrom 100keV into the MV range¢ near tissue equivalent¢ high spatial resolution – can resolve features to atleast 5μm¢ can be handled in room light – eliminates the needfor a darkroom¢ active coating exposed for detection of low energyphoton and electron¢ proprietary new technology incorporating a markerdye in active layer:– e nables non-unformity correction by using multichannel dosimetry – d ecreases UV/light sensitivityfigure 1. configuration of Gafchromic HD-V2 dosimetry filmactive layer — 8 micronspolyester substrate — 97 micronsperformance data and practical user guidelinesWhen the active component in Gafchromic ™ HD-V2 film is exposed to radiation, it reacts to form a blue colored polymer with absorption maxima at approximately 670 nm as shown in Figure 3.Gafchromic ™ HD-V2 radiochromic dosimetry film may be measured with transmission densitometers, film scanners or spectrophotometers. As one can infer from the Figure 3, the response of the dosimetry film media is enhanced by measurement with red light. In using a spectrophotometer the greatest response is obtained by scanning the film and using the peak absorbances. Most densitometers measure over a band of wavelengths and transmission densitometers for measuring colored films measure over various narrow color bands within the visible spectrum, e.g. visual, red, green and blue.Such densitometers are commonly and widely employed in the photographic industry.To obtain two-dimensional information in speedy fashion, flatbed color scanners are shown to work well with all Gafchromic ™ films including HD-V2 films. The commonly available professional photo scanners such as EPSON* Expression 10000XL, 11000XL, 12000XL and 1680 flatbed color scanners can be used. These scanners are color scanners and measure the red, green, and blue color components of the film in a color depth of 16 bit per channel.A typical dose response of HD-V2 film on an rgb color scanner is shown in Figure 4. We recommend it to fit the calibration curve in function form of where dx(D) is the optical density of film in scanner channel x at dose D, and a, b, c are the equation parameters to be fitted. The advantages of these functions are:¢ t hey are simple to invert and determine density as afunction of dose, or dose as a function of density¢ t hey have rational behavior with respect to the physicalreality that the density of the film should increase with increasing exposure yet asymptote towards a nearconstant value at high exposures – polynomial functions characteristically have no correspondence to physical reality outside the data range over which they are fitted¢ s ince these functions have the described rationalbehavior , fewer calibration points are required saving time and film – t o cover a dose range of 0 – 1000 Gy requires 6-8 dose points, for example, 0, 25, 50, 100, 200, 400, 800 and 1200 Gydx (D) = –log a+b D c+D(),Gafchromic ™ HD-V2 film has an asymmetrical cross section (see Figure 1). Measurements indicate that the response of scanner or densitometer may be dependent on which side of the film is facing the light source. It is advised that HD-V2 film be consistently measured with the same side of the film facing the light source regardless of whether landscape or portrait orientation is used.To help in distinguishing between the sides, sheets ofGafchromic ™ HD-V2 films are marked with a small slit near one corner. When film is viewed in a landscape orientation with the slit in the top right corner as shown in Figure 2, the unlaminated active layer is on the side facing the viewer.figure 2. Gafchromic HD-V2 film in landscapeview showing slit in top right corner30Gy 2.5250Gy 100Gy 250Gy1.5500Gy10.50400450500550wavelength, nma b s o r p t i o n600650700figure 3. spectra ofGafchromic HD-V2 as a function of absorbed dosesfigure 4. response ofGafchromic HD-V2 in all color channelsfor U.S. orders and inquiries email:**************************for international orders and inquiries email: ***********************************/contact® Registered trademark, Ashland or its subsidiaries, registered in various countries™Trademark, Ashland or its subsidiaries, registered The information contained in this document is intended for use onlyby persons having technical skill and at their own discretion and risk. All statements, information and data presented herein are believedto be accurate and reliable, but are not to be taken as a guarantee,an express warranty, or an implied warranty of merchantability or fitness for a particular purpose, or representation, express or implied, for which Ashland and its subsidiaries assume legal responsibility. Certain end uses of our products may be regulated pursuant torules governing medical devices. A purchaser must make its own determination of our products’ suitability for purchaser’s use, whether alone or in conjunction with other products, the protection of the environment, and the health and safety of its employees and customers.。

材料科学与工程专业英语匡少平课后翻译答案精编W O R D版IBM system office room 【A0816H-A0912AAAHH-GX8Q8-GNTHHJ8】Alloy合金applied force作用力amorphous materials不定形材料artificial materials人工材料biomaterials生物材料biological synthesis生物合成biocompatibility生物相容性brittle failure脆性破坏carbon nanotub e碳纳米管carboxylic acid羟酸critical stress临近应力dielectric constant介电常数clay minera l粘土矿物cross-sectional area横截面积critical shear stress临界剪切应力critical length临界长度curing agent固化剂dynamic or cyclic loading动态循环负载linear coefficient of themal expansio n性膨胀系数electromagnetic radiation电磁辐射electrodeposition电极沉积nonlocalizedelectrons游离电子electron beam lithography电子束光刻elasticity 弹性系数electrostation adsorption静电吸附elastic modulus弹性模量elastic deformation弹性形变elastomer弹性体engineering strain工程应变crystallization 结晶fiber-optic光纤维Ethylene oxide环氧乙烷fabrication process制造过程glass fiber玻璃纤维glass transition temperature 玻璃化转变温度heat capacity热熔Hearing aids助听器integrated circuit集成电路Interdisplinary交叉学科intimate contact密切接触inert substance惰性材料implant移植individual application个体应用deformation局部形变mechanical strength机械强度mechanical attrition机械磨损Mechanical properties力学性Materials processing材料加工质mechanical behavior力学行为magnetic permeability磁导率magnetic hybrid technique混合技术induction磁感应mass per unit of volume单位体积质量monomer identity单体种类molecular mass分子量microsphere encapsulation technique微球胶囊技术macroscopical宏观的naked eye 肉眼nonlocalized nanoengineered materials纳米材料nanostructured materials纳米结构材料nonferrous metal有色金属线nucleic acid核酸nanoscale纳米尺度Nanotechnology纳米技术nanobiotechnology纳米生物技术nanocontact printing纳米接触印刷optical property光学性质optoelectronic device光电设备oxidation degradation 氧化降解piezoelectric ceramics压电陶瓷Relative density相对密度stiffnesses刚度sensor传感材料semiconductors半导体specific gravity比重shear 剪切Surface tention表面张力self-organization自组装static loading静载荷stress area应力面积stress-strain curves应力应变曲线sphere radius球半径submicron technique亚微米技术substrate衬底supramolecalar超分子sol-gel method溶胶凝胶法thermal/electrical conductivity 热/点导率thermoplastic materials热塑性材料Thermosetting plastic热固性塑料thermal motion热运动toughness test韧性试验tension张力torsion扭曲Tensile Properties拉伸性能Two-dimentional nanostructure二维纳米结构Tissue engineering组织工程transplantation of organs器官移植the service life使用寿命the longitudinal direction纵向the initial length of the materials初始长度the acceleration gravity重力加速度the normal vertical axis垂直轴the surface to volume ratio 比表面密度the burgers vector伯格丝矢量the mechanics and dynamics of tissues 组织力学和动力学phase transformation temperature相转变温度plastic deformation塑性形变Pottery陶瓷persistence length余晖长度polymer synthesis聚合物合成Polar monomer记性单体polyelectrolyte高分子电解质pinning point钉扎点plasma etching 等离子腐蚀pharmacological acceptability药理接受性pyrolysis高温分解ultrasonic treatment超射波处理yield strength屈服强度vulcanization硫化1-1:直到最近，科学家才终于了解材料的结构要素与其特性之间的关系。

Growth of SiC Nanorods on Si SubstrateAbstractSilicon carbide (SiC) is a ™-™ compound semiconductor material with a wide band gap. Semiconductor electronic devices and circuits made from SiC are presently being developed for high-temperature, high-power, and high-radiation conditions in which conventional semiconductors cannot adequately perform. One-dimensional SiC, such as nanowires and nanorods, is of great interests for many applications due to their excellent properties, such as high mechanical strength, high thermal stability, high thermal conductivity. Especially SiC nanorods are widely considered as reinforcement materials for ceramic composites providing very high strength and toughness due to their very high elastic modulus and strength over their bulk-counterpart. In this study, the SiC nanorods were fabricated by vapor-liquid-solid (VLS) mechanism on Si substrate. The SiC nanaorods were characterized by scanning electron microscopy (SEM), X-ray diffraction (XRD)and energy diffraction spectrometer (EDS).The factors which influenced the formation of SiC nanorods were studied.Keywords: SiC nanorods, VLS mechanism, CVDIntroductionSilicon carbide (SiC) is a wide band gap semiconductor with many super properties, such as high breakdown field，high thermal conductivity, high saturation drift velocity, low relative dielectric constant and excellent resistance to oxidation and corrosion[1-2]. These outstanding properties make SiC a very attractive semiconductor material. For example, SiC is commercially applied for optoelectronic devices [3], such as photodiodes and light-emitting diodes which emit throughout the visible spectrum into the ultraviolet. The applications of SiC also cover the area of high-temperature sensors, high-power devices, and microwave devices (both avalanche diodes and field effect transistors).In the meantime, since carbon nanotubes emerged into the scientific world in 1991 and their exceptional excellent properties were introduced, one-dimensional nanomaterials such as SiC, GaN, have attracted much interest from researchers because the extreme geometry of the nanomaterials is of importance to investigate the physical and chemical properties of the materials such as their quantum size effect. These nanosized materials are important for ceramic nanocomposite materials [4, 5]. They are also claimed to be promising raw materials for engineering ceramic devices offering superplasticity and high strength at high temperatures. Furthermore nanoscale filters or support for a catalytic surface might be interesting application of SiC nanopowders.A lot of methods have been developed to synthesize SiC nanorods [6]. SiC nanorods can be fabricated without the metallic catalysts. For instance, Zhou [7] fabricated SiC nanowires by the hot filament chemical vapor deposition (CVD) method. B.-C. Kang synthesized SiC nanorods by CVD method.Li [8] synthesized SiC nanowires by using a SiC rod as the anode to arc-discharge. And Hyung Suk Ahn [9] synthesized SiC nanorods by using LPCVD. SiC nanorods can be also fabricated with the metallic catalysts. For example, B.-C. Kang fabricated SiC nanorods by using nickel as a catalyst. And Zhang [10] et al. synthesized SiC nanorods using Fe powders as the catalyst. Among these methods, carbothermal reduction of silica-containing materials and the CVD method are the most commonly employed.In carbonthermal reduction process, three mechanisms are involved to form SiC nanorods. They are called vapor-solid (VS) mechanism, two-stage growth (TS) mechanism and vapor-liquid-solid (VLS) mechanism. [11] By the VS mechanism, the nanorods are grown by direct accommodation of silicon and carbon atoms to the growth plane from the silicon- and carbon-carrying vapors. The nanorods are formed in the raw materials containing metal impurities such as rice-hulls by the TS mechanism. The impurities form discrete liquid droplets on the growth plane. The droplets are quickly covered with vapor species because of their high accommodation coefficient and act as nucleation sites for thenanorods growth. It results in axial growth of nanaorods (first stage), and, then in lateral thickening (second stage) [11, 12]. The essential features of VLS mechanism can be expressed as the growth of nanorods via the assistance of liquid solution containing the desired ingredient of the nanorods to be grown. The processes are complex and the fundamental issues remain to be ascertained. The growth of nanorods involves the dissolution of solute at the vapor/liquid interface and its subsequent precipitate at the liquid/solid interface during the VLS growth process. In this paper, nickel was used as a metallic catalyst to deposit SiC nanorods on Si substrate via the VLS mechanism.ExperimentSiC nanorods were fabricated in metalorganic chemical vapor deposition (MOCVD) system. The water-cooled reactor, as shown inFig. 1 schematic configuration of MOCVD reactorFig.1, was a horizontal quartz tube. First, nickel thin film with thickness of 400∗500 nm, which acted as a catalyst in growing SiC nanorods, was deposited on Si substrate by DC sputtering. The Si substrates covered with nickel thin flim were set on a SiC-coated graphite susceptor, which was heated by ratio frequency (RF) induction. According to Ni-Si and Ni-C phasediagram [13-15], the growth temperature was selected between 1250ε and 1380ε . Silane (SiH4) and acetylene (C2H2) were used as source gas. Hydrogen (H2) gas purified by a Pd purifier was used as the carrier gas. The flow rate of H2 was fixed to be 500 sccm (standard cubic centimeter per minute). And the growth pressure of SiC nanorods was fixed to be 60 Torr.Two processes were carried out to synthesize SiC nanorods. One was called two-step process, in which only C2H2 was first introduced into the reactor to fabricate carbon nanotubes on the Si substrates covered nickel thin film at 1150ε for several minutes. Then the growth temperature increased to 1150ε∗1350ε , and C2H2 and SiH4 were reacted as the source gas to synthesize SiC nanorods. Another process was called one-step process, in which C2H2 and SiH4 as the source gases were introduced into the reactor at the same time.The crystal structure of SiC nanorods was characterized by X-ray diffraction (XRD). The morphology of SiC nanorods was characterized by scanning electron microscopy (SEM). Energy dispersive spectrometer(EDS) was carried out to identify their chemical composition.Results and discussion1.SiC nanorods synthesized by two-step processBy the two-step process, carbon nanotubes were first synthesized on the Si substrate in the carbonized process. The morphology and the composition characterized by SEM and EDS, were shown in Fig.2 and Fig.3 respectly. The Ag peak appeared in the EDS image was introduced in the experiment during the SEM and EDS analysis. According to the figure, high density of carbon nanotubes was grown on the Si substrate.Fig. 2 SEM images of carbon naotubes grown on a Si substrateFig. 3 EDS spectrum of carbon nanotubesgrown on a Si substrateThe XRD spectrum of SiC nanorods synthesized by two-step process was shown in Fig.4. In the XRD patterns, characteristic peaks from (111), (200) and (220) plane of ß-SiC appeared at 35.68°, 47.68° and 60.16°, respectively. Peaks from other polytypes of SiC were not observed, so the SiC nanorods were zinc-blende structure.The morphology of SiC nanorods was depicted in Fig.5. High density of nanorods was randomly grown on the substrate. The diameters of SiC nanorods were almost the same.2. SiC nanorods synthesized by one-step processThe characters of the SiC nanorods fabricated by one-step process were characterized by XRD, SEM and EDS. The results are shown in Fig.6∗8 and table 1. In general, SiC nanorods were synthesized by one-step process.Fig. 4 XRD patterns of SiC nanorods Fig. 5 SEM image of SiC nanorodssynthesized by two-step methodAlthough all the samples were growth by VLS mechanism, it was clearly that the diameter of the SiC nanorods fabricated by one-step process was much larger than that prepared by two-step process. The reasons should be the confinement effect of carbon nanotubes in two-step process. The size of carbon nanotubs limited the lateral growth of SiC nanorods and led to the diameter of SiC nanorods almost the same as that of carbon nanotubes. For the one-step process, however the main factors which determined the diameter of SiC nanorods should be the volume of liquid droplet and wetting behavior [16-17], so the diameter of SiC nanorods, Fig. 7 SEM image of SiC nanorodsfabricated by one-step process Fig. 6 XRD pattern of SiC nanorods fabricatedby one-step process Fig.8 EDS spectrum of SiC nanorods by one-step processwas much larger.The atomic content of carbon was higher than that of silicon for the SiC nanorods made by one-step process as shown in table 1. It should be originate from the result of C2H2 activity. Because of its high activity, C2H2 should be decomposed very quickly at 1250ε . A lot of carbon atoms deposited on Si substrate. However, not enough silicon atoms reacted with them. So the redundant carbon atoms formed amorphous carbon on the substrate.SummarySiC nanorods were successfully synthesized via VLS mechanism by two-step process and one-step process. The structure, morphology and composition were characterized by XRD, SEM and EDS. Factors which affected the diameter of SiC nanorods were discussed.References[1].Philip G. Neudeck, SiC technology (1998).[2].Philip G. Neudeck, High-temperature electronics –a role for wide bandgapsemiconductors, Proceedings of the IEEE, Vol 90, No 6 (2004).[3].Han-Kyu Seong, Heon-Jin Choi and Sang-Kwon Lee, Optical and electricaltransport properties in silicon carbide nanowires, Applied Physics Letters, Vol 85,No 7 (2004).[4].B.-C. Kang*, S.-B. Lee, J.-H. Boo*, Growth of ß -SiC nanowires on Si(100)substrates by MOCVD using nickel as a catalyst, Thin Solid Films 464–465 (2004) 215– 219[5].Heon-Jin Choia,*, Han-Kyu Seonga, Jung-Chul Leeb, Yun-Mo Sungb, Growthand modulation of silicon carbide nanowires, Journal of Crystal Growth 269 (2004) 472–478[6].Qingyi Lu, Junqing Hu, Kaibin Tang,a) and Yitai Qian, Growth of SiC nanorodsat low temperature, Appl. Phys. Lett VOL 75, No 4,[7].X.T. Zhou, N. Wang, H.L. Lai, H.Y. Peng, I. Bello, N.B. Wang, C.S. Lee, S.T.Lee, Appl. Phys. Lett. 74 (1999) 3942.[8].Y.B. Li, S.S. Xie, X.P. Zou, D.S. Tang, Z.Q. Liu, W.Y. Zhou, G.Wang, J. Cryst.Growth 223 (2001) 125.[9].Hyung Suk Ahn, Doo Jin Choi, Fabrication of silicon carbide whiskers andwhisker-containing composite coatings without using a metallic catalyst, Surface and Coatings Technology 154 (2002) 276-281.[10].Y ingjun Zhang, Nanlin Wang et al, synthesis of SiC nanorods using floatingcatalyst, Solid state communications 118(2001)595-598[11].H eon-Jin Choi *, June-Gunn Lee, Stacking faults in silicon carbide whiskers,Ceramics International 26 (2000) 7-12[12].R.S. Wagner, W.C. Ellis, Appl. Phys. Lett. 4 (5) (1964) 89.[13].C. Rado, et al, wetting and bonding of Ni±Si alloys on Silicon, Acta mater. Vol.47, No. 2, pp. 461-473, 1999[14].J. Acker*, K. Bohmhammel, Optimization of thermodynamic data of the Ni±Sisystem, Thermochimica Acta 337 (1999) 187-193[15].H ee Jin Jeong , Seung Yol Jeong ,Young Min Shin , Dual-catalyst growth ofvertically aligned carbon nanotubes at low temperature in thermal chemical vapor deposition, Chemical Physics Letters 361 (2002) 189–195[16].I ng-Chi Leu*, Min-Hsiung Hon, Nucleation behavior of silicon carbide whiskersgrown by chemical vapor deposition, Journal of Crystal Growth 236 (2002) 171–175[17].I ng-Chi Leu, et al Factors determining the diameter of silicon carbide whiskersprepared by chemical vapor deposition, Materials chemistry and physics 56(1998),256-561.。

摘要摘要滤波器作为通信系统前端电路不可或缺的组件，对于整个通信系统而言，其性能的好坏将直接影响到信号的接收，发射以及传播。

而随着整个通信系统的不断发展以及完善，对于各个组件的要求也在不断的提高，滤波器也朝着小型化高性能的方向发展。

在大量学者几十年的研究过程中，基片集成波导技术（Substrate Integrated Waveguide, SIW）因其独特的结构和电磁特性吸引了滤波器设计者们的目光。

SIW其结构既如微带线结构一样，质量轻、体积小、易加工且与平面电路集成方便，又像传统波导一样，辐射损耗小、功率容量大。

这些特性使得其可以成为顺应小型化高性能滤波器发展的设计平台。

而说到滤波器的高性能，不得不提到滤波器的高选择性，高选择性滤波器可以更加有效的滤除不必要的干扰信号，可以大大提高有用信号的传输效率，然而提高滤波器的选择性最常见的方法就是引入传输零点（Transition Zeros, TZs），而传输零点的获取可以通过交叉耦合，源和负载耦合等方法来实现。

本文的主要工作就是研究将SIW技术和交叉耦合以及源和负载耦合等方法相结合设计出具有传输零点的高选择性带通滤波器。

首先，本文简单介绍了滤波器的发展现状以及基本理论知识，包括分类以及基本参数等。

其次，文章又讲解了本文所设计的滤波器的载体SIW，详细介绍分析了其基本结构和特性，并又介绍了两种常见的SIW与微带线的过渡结构，接着又举例说明了三种常用的SIW腔之间的耦合结构，这些都为下文将SIW与交叉耦合理论相结合设计出高选择性滤波器提供了理论基础。

再次，本文介绍了交叉耦合理论，重点介绍了该理论中常见的三谐振器耦合（Coupled Triplet, CT）和四谐振器耦合（Coupled Quadruplet, CQ）结构的相位模型，也以此讨论TZ的位置变化，并通过仿真实例来印证了CT结构相位模型，接着又结合仿真实例讨论了二次模谐振腔对CT结构传输零点位置的影响，最后运用上述方法与SIW相结合利用金属通孔扰动一次模使其频率上升的方法设计出了一款通带两边各具一个传输零点的高选择性带通滤波器。

A Parallel-Strip Ring Power Divider WithHigh Isolation and ArbitraryPower-Dividing RatioAbstract—In this paper, a new power divider concept, which provides high flexibility of transmission line characteristic impedance and port impedance, is proposed. This power divider is implemented on a parallel-strip line, which is a balanced transmission line. By implementing the advantages and uniqueness ofthe parallel-strip line, the divider outperforms the conventional divider in terms of isolation bandwidths. A swap structure of the two lines of the parallel-strip line is employed in this design, which is critical for the isolation enhancements. A lumped-circuit model of the parallel-strip swap including all parasitic effects has been analyzed. An equal power divider with center frequency of 2 GHz was designed to demonstrate the idea. The experimental results show that the equal power divider has 96.5%—10-dB impedance bandwidth with more than 25-dB isolation and less than 0.7-dB insertion loss. In order to generalize the concept with an arbitrary power ratio, we also realize unequal power dividers with the same isolation characteristics. The impedance bandwidth of the proposed power divider will increase with the dividing ratio, which is opposite to the conventional Wilkinson power divider. Unequal dividers with dividing ratios of 1 : 2 and 1 : 12 are designed and measured. Additionally, a frequency independent 1800 power divider has been realized with less than 20 phase errors.Index Terms—Arbitrary power-dividing ratio, parallel-strip line, ring structure, unequal power divider.I. INTRODUCTIONTHE WIKINSON power divider is one of the conventional and fundamental components in microwave engineering and exists in many microwave circuits. Both distributed and lumped Wilkinson power dividers have been applied in microwave integrated circuits and monolithic microwave integrated circuits [1]. Recently, extensive studies have been made to enhance the performances of the Wilkinson power divider, including size reductions by capacitive loading [2], folded circuitry [3] and resonating structure [4], [5], multiband operation [6], [7], unequal power dividing/combining [8], and active device [9] and waveguide implementations [10]. The power dividers discussed in this paper are focused on the isolation enhancement. The proposed divider is realized in the parallel-strip transmission line. Some parallel-strip circuits were reported with performance enhancement [11], [12]. The parallel-strip line provides more design flexibility than a micro-strip line, especially in realization of a high-impedance line and transitions.Many balanced circuits such as push–pull amplifiers, balanced mixers, frequency multipliers, and antenna arrays employ the Wilkinson power divider because of its simple design with high port-to-port isolation. Isolation is one of the important issuesin the design of the power divider and directional coupler. High isolation implies the minimization of unwanted coupling between active devices, as well as the elimination of unexpected distortions and oscillations. It is because it may provide a positivefeedback path for other frequencies, e.g., in Fig. 1, as unwanted oscillation at f1 may be set up outside of the operation frequency f0. Therefore, a wideband isolation operation is always preferred to suppress the coupling in other frequency bands.Fig. 1. Balanced circuit at frequency f0 and unwanted feedback at f1.The parallel-strip line belongs to a family of balanced transmission line. The conventional printed circuit board (PCB) fabrication technique is able to easily realize parallel-strip lines. It is a simple structure of a dielectric substrate sandwiched between two strip conductors. The signals flowing on the upper and lower strip conductors are always equal in magnitude and 1800out-of-phase. The quasi-TEM mode electric and magnetic fields distributions are closed to the micro-strip line. In this paper, a parallel-strip swap is employed to enhance isolation performance of the power divider. The swap is a passive microwave component. It forms a compact realization of 1800 phase shift by interchanging the connection of two conductors in the balanced transmission line. Various swaps were proposed for performance enhancement in a 1800 hybrid coupler [13]–[15].A new equal power divider, which is realized on a parallel-strip line with a ring-like structure, was first demonstrated in [16]. The four arms and two shunt resistors in the divider provide a high degree of freedom for choosing the circuit parameters. In this paper, the proposed concept is generalized to be arbitrary power dividing without an increase in design complexity. It shows a frequency-independent isolation characteristic, arbitrary power-dividing ratio without an external matching network, avoidance of a very thin strip line for achieving high characteristic impedance, and ease of realizing wideband 1800 dividing. While the conventional Wilkinson powerdivider exhibits limited isolation bandwidth, unequal Wilkinson power dividing relies on an external quarter-wave transformer for realizing unequal power dividing for the same port impedances.High characteristics impedance transmission lines are required for the unequal power divider. The unequal divider has been used with strict restrictions in design and fabrication because it requires a transmission line with very high impedance [8]. On the other hand, the very thin transmission line limits the power handling of the devices. To overcome this limitation in realizing characteristic impedance, the upper and lower strip lines of the parallel-strip line are offset so that it will be easier to highly increase the characteristic impedance. Three power dividers with power-dividing ratios of 1 : 1, 1 : 2, and 1 : 12 were designed, fabricated, and tested.Fig. 2. Schematic diagram of proposed power divider with four arms, a swap, and two shunt resistors.II. THEORETICAL ANALYSISThe structure of the proposed divider is illustrated in Fig. 2.In [13], the equal power divider has been analyzed using even and odd-mode analysis because of symmetry of the divider. For the same reason, the circuit parameters, such as port impedance and line impedances, should be the same as their corresponding parameters Z A=Z C, Z B=Z D, and Z2=Z3. In this paper, we try to generalize the analysis to an unequal power divider with an arbitrary dividing ratio.It consists of an 1800 swap, four quarter-wave-long arms (with characteristic impedances Z A, Z B, Z C, and Z D) and two shunt resistors with resistance . These five parameters determine the input impedances, isolation, and dividing ratio of the divider. In order to determine the arm characteristic impedances and resistor values, several parameters should be known, including port impedances Z1, Z2, and Z3 and power ratio K.Firstly, the impedance matching is considered. To achieve maximum power transfer, all the ports should be matched. The input impedance at port 1 is determined by Z A and Z C and port impedances Z2 and Z3.As illustrated in Fig. 3, it is assumed thata signal is injected to port 1 and will only pass through ports 2 and 3. There is no net current flowing from ports 2 to 3 due to port isolation between ports in the shaded region. Arms B and D with characteristic impedances Z B and Z D , respectively, the two shunt resistors, and the swap can thus be replaced by an open circuit in analysis. The two arms are connected in shunt; the input impedance at port 1 can be expressed as(1)The signal injected to port 2 can be divided into two parts, one flowing to port 1 and the other being absorbed by shunt resistors as shown in Fig. 4. Obviously, there is no net current flowing from arm to arm and port 3 in the shaded region, which can be replaced by an open circuit in analysis. The input impedance at port 2 can be given as(2)Similarly, the input impedance at port 3 can be expressed as(3)For the unequal power dividing and assuming the power ratio of ports 2 and 3 to be K, the power ratio can be determined by the ratio of input impedance of the arms A and C, as shown in Fig. 3, as follows:(4)123221)(-+=C A Z Z Z Z Z 12212)2(-+=B A Z R Z Z Z 12213)2(-+=D C Z R Z Z Z 32222232Z Z Z Z Z Z Z Z k A C A C ==By solving (1), (2), and (4), Z A and Z C are determined and are expressed in (5) and(6), respectively.Solving (4) and (1),(5)Solving (4) and (2),(6)Hence, the ratio of the square of Z B and Z D and shunt resistor can be determined by solving (2), (3), (5), and (6).Solving (5) and (2),(7)Solving (6) and (3),(8)There are four conditions, but five unknown parameters Z A , Z B, Z C , Z D , and R. Therefore, the solutions are singular, which implies there is no unique solution. The 31)1(Z Z k Z C +=21)11(Z Z k Z A +=)11(232kZ R Z D +=)1(222k Z R Z B +=infinite number of solutions provide a high degree of freedom when the divider is designed. For example, the divider can not only be designed for any port impedance without external matching circuits, but also provides unequal power dividing with equal port impedance.Isolation is a very important design issue. The symmetrical structure and the swap provide the possibility of frequency-independent isolation characteristics. Signals flowing through paths A –C and B –D should be equal in magnitude, but 1800 out-of -phase. In order to provide frequency-independent isolation, the phase difference between paths A –C and B –D should be frequency independent at 1800 out-of-phase and with equal amplitude, which is provided by the swap, and the characteristic impedance should be the sameZ A = Z D and Z B = Z C (9)Equation (9) represents the fifth condition for designing a divider with frequency-independent isolation and arbitrary power ratio. After combining the previous conditions, the parameters Z A , Z B, Z C , Z D , and R become unique. The design formulas can be summarized asR=2Z1 (10a)(10b)(10c)31)1(Z Z k Z Z C B +==21)11(Z Z k Z Z D A +==Fig. 5. Geometries of parallel-strip swap and parallel-strip line with equal physical length.III. PARALLEL SWAP AND DISCONTINUITYThe swap is the interchange between the two signal lines in the balance transmission line so that the signal is said to be ―reversed,‖ therefore, it provides 1800 phase shift without the existence of a delay line. It can be easily realized in some of the nonmicrostrip transmission lines such as a coplanar waveguide, coplanar strip line, and parallel-strip line. Fig. 5 shows the geometry of the parallel-strip swap. The upper and lower strip lines are connected by two vertical metical vias. The sections of the swap and parallel-strip line are simulated using Ansoft’s High Frequency Structure Simulator (HFSS). Within the entire simulation band, less than 0.5-dB extra insertion loss is introduced and 1800 phase shift is provided with less than 2 phase error, as shown in Fig. 6. The swap introduces discontinuity for the divider and always degrades the circuit performance. It is necessary to develop proper analysis models. The structure of parallel- strip swap with two shunt resistors used in the proposed divider is shown in Fig. 7. Two resistors are soldered across the two gaps at the upper and lower strip lines. These resistors are used to absorb the signal. They are necessary to provide proper impedance matching and port-to-port isolation, similar to the resistor in the Wilkinson power divider.Extra insertion loss and phase delay are introduced by the vertical via, which can be analyzed by a lumped-circuit model. The lump-circuit model of the swap with two shunt resistors (R S) is illustrated in Fig. 8. The parasitic capacitance (C S) is used to model the edge couplings between strips with different layers. The parasitic capacitance (C C) is used to model the total effect due to edge couplings between strips with the same layers and coupling between the vias. The parasitic inductance (L V) and resistance (R V) are introduced by vertical conductor in via-holes and soldering. Theparasitic components can be extracted from full-wave simulations so that the lumped model of the swap was done.The Z-parameter of the lumped equivalent model of the core in Fig. 8 is given by(11)Fig. 6. Simulated frequency responses of insertion loss and phase difference of a section of parallel-strip swap and line with same physical length.⎪⎪⎭⎫ ⎝⎛+--+=⎪⎪⎭⎫ ⎝⎛212121212221121121Z Z Z Z Z Z Z Z Z Z Z ZFig. 7. 3-D view of parallel-strip swap with two shunt resistors.Fig. 8. Lump equivalent model of parallel-strip line swap.where Z 1= R V + jwL V and Z 2= (1/ R S +1/jwC C )-1 Hence, the S-parameter converted from Z-parameters of the core is determined as follows:(12)(13) ))((020*********Z Z Z Z Z Z Z S S +++==))(()(020********Z Z Z Z Z Z Z S S ++-==The structure shown in Fig. 7 is simulated by the full-wave electromagnetic (EM) simulator HFSS, determining the optimum design of the vias on the substrate dielectric constant of 2.65 and thickness of 1.5 mm where all the gapwidthsFig. 9. Simulated S-parameters of the parallel-strip line swap using lumped model and full-wave EM simulation. (a) Magnitude response. (b) Phase response.are 0.2 mm and the radius of the metallic via is 0.55 mm. Deembedding of the parameters has been performed by utilizing the microwave circuit simulator, Agilent Technologies’s Advanced Design System (ADS). Both EM and circuit simulationsof the parallel-strip swaps with 70.71- terminations are shown in Fig. 9. Good agreement of both the magnitudes and phases responses are achieved within the frequency band of interest. The values of parasitic elements are L V =2.181 nH,C S=0.2939 pF, C C=0.3878 pF, and R V =0.2624Ω. The model circuit is analyzed and, hence, the scattering matrix representing the parallel-strip swap with shunt resistor (R S) is, therefore, obtained, and the entire circuit can thus be easily modeled in the circuit simulation.IV. RESULTS OF SIMULATION AND EXPERIMENTA. Equal Power DividerThe power dividers are fabricated in a conventional printed circuit technique and the dividers designed for demonstration are built on a substrate with a dielectric constant of 2.65 and a thickness of 1.5 mm, as shown in Fig. 10. The derivation in Section II is based on an ideal transmission line model. This analysis provides initial design parameters. Discontinuities or parasitic elements such as T-junctions and steps will be introduced. EM optimization is required to determine all circuit parameters with the best performance.Fig. 10. Implementation of proposed equal power divider on PCB. (a) Upper layer. (b) Bottom layer. are built on a substrate with a dielectric constant of 2.65 and a thickness of 1.5 mm, as shown in Fig. 10. The derivation in Section II is based on an ideal transmission line model. This analysis provides initial design parameters. Discontinuities or parasiticelements such as T-junctions and steps will be introduced. EM optimization isrequired to determine all circuit parameters with the best performance.All the port impedances are designed at 50 , i.e., Z1=Z2=Z3=50Ω The designparameters of an equal power divider are Z A=Z B=Z C= Z D = 70.71Ωand R=100Ω.By removing portion of the ground of a micro-strip line, the parabolic tapered transition between the parallel-strip line and micro-strip line [11] was employed for connecting the coaxial connector for measurement purposes with less than 0.1-dB insertion loss within the entire tested frequency band. However, an approximate 0.5-dB extra insertion loss will be introduced if a subminiature A (SMA) connector is directly connected to the SMA connector. Fig. 11 shows both simulated and measured results of the equal power divider. The EM simulation tool is Ansoft’s HFSS. The measured insertion loss from ports 1 to 2 and 3 are less than 3.7 dB within the operation frequency band, as shown in Fig. 11(a). Some mismatches come from an inaccurate prediction of the vertical structure from the EM simulator and soldering. The mismatches in return losses shown in Fig. 11(b) are due to unexpected errors from soldering between the divider and SMA connectors. The ring-like structure implies similar input and output impedance characteristics, as shown in Fig. 10. The total usable impedance bandwidth is wider than that of the conventional Wilkinson power divider. Due to the imbalances of the two paths, e.g., electrical delay and insertion loss in the swap, the isolation has a finite value. Fortunately, the isolation can still provide great improvement over the conventional divider.The impedance bandwidths of return loss lower than 10 dB of the proposed divider is measured at 96.5%, as observed in Fig. 11(b). In Fig. 11(c), the proposed divider demonstrates more than 25 dB in the entire frequency band in the measurement, while a conventional Wilkinson power divider shows approximately 33% isolation bandwidth of more than 20-dB isolation. Good agreement between experimental and simulated results can be observed.B. Unequal Power DividersApart from the equal power divider, two unequal power dividers with ratios of 1 : 2 and 1 : 12 are realized. The impedance bandwidth is usually reduced with the dividing ratio in the conventional Wilkinson power divider; however, the bandwidth of the proposed divider is increased with a power ratio of . The relation is shown in Fig. 12. Figs. 13 and 14 show the frequency responses of -parameters and the dividing ratio of the 1 : 2 power divider. The design parameters are Z A=Z D=61.24Ω, ZB=ZC= 86.61Ω, and R=100Ω. Measured results agree withEMsimulation.Within the 125% operation bandwidth with lower than 10-dB return loss, more than 26-dB port-to-port isolation is achieved and the average divider ratio is approximately 2.07.Fig. 11. Simulated and measured results of proposed equal power divider.(a) Insertion losses. (b) Return losses. (c) Isolation.A high dividing ratio implies the existence of some high characteristicimpedance transmission lines. The implementation ofhigh characteristic impedance remains challenge because of theFig. 15. Cross section and 3-D view of offset parallel-strip line.Fig. 16. Relationship of characteristics impedance and normalized offset distance with different normalized strip width, where z denotes characteristics impedance, w denotes width of the strip line, d denotes offset distance, and h denotes substrate thickness.technique of extremely thin micro-strip line fabrication. The realization of the unequal power divider may be limited by fabrication of the thin strip line and low power-handling capacity of the divider.In order to easily realize a high-impedance transmission line, a micro-strip defected ground structure was proposed for the 1 : 4 unequal divider [8]. In [17], thecharacteristics impedance parallel- strip line was increased by offsetting the upper and lower strip lines in the finite ground micro-strip line for stopband enhancement. Similarly, the characteristics impedance of a parallel-strip line can be increased by offsetting the strip lines, as shown in Fig. 15. Fig. 16 shows the relationship between characteristics impedances and normalized circuit parameters on the same substrate. It is obvious that the characteristics impedance (z) increases with offset distance (d) without use of very narrow strip lines. A high characteristic impedance parallel-strip line can be realized by offsetting the upper and lower strip lines andit does not need a very narrow line.In the 1 : 12 power divider, two arms with high characteristic impedance are realized by offsetting the parallel-strip line. Figs. 17 and 18 show its -parameters and the dividing ratio varied with frequency. The design parameters are Z A=Z D=50.04Ω, Z B=Z D=180.27Ω, and R=100Ω. Good agreement of both simulated and measured results are obtained. Within the 150% operation bandwidth with lower than 10-dBreturn loss, more than 24-dB port-to-port isolation is achieved and the average divider ratio is approximately 12.68.Fig. 17. Simulated and measured S-parameters of 1 : 12 proposed divider.Fig. 18. Simulated and measured dividing ratio of 1 : 12 proposed divider.C. Frequency-Independent 180 Power DividerConventionally, the symmetric power divider is used for in-phase powerdividing/combining. A power divider with wideband 1800 out-of-phase operation is needed for many balanced circuit such as a push–pull amplifier and balanced mixer. The 1800 hybrid or the power divider with a 1800 delay line is used for such purpose.A 1800 divider can be easily realized by adding an extra section of delay line. However, a delay line limits the bandwidth of phase balances. The conventional 1800 hybrid coupler or Wilkinson power divider with a delay line may not fulfill actual application demands and may degrade system performance. With a similar approach to [12], the frequency-independent 1800 differential phase between ports 2 and 3 is realized by tapering the lower line in port 2 and the upper line in port 3, the parallel-strip line-to-micro-strip line transition, which is used for measurement, is formed as shownin Fig. 19. All circuit parameters are the same as the equal power divider in Section IV. The magnitudes of simulated and measured -parameters are close to that of the equal power divider, as shown in Fig. 11. A frequency-independent 1800 phase difference is observed, as shown in Fig. 20. A small phase error within 2 is introduced due to the thickness of the substrate of the PCB, while it can be minimized by using a thinner substrate with a lower dielectric constant. Similarly, the 1800 unequal power divider with an arbitrary dividing ratio can be realized via the same technique.Fig. 19. Implementation of proposed 1800 equal power divider on PCB. (a) Upper layer. (b) Bottom layer.Fig. 20. Phase response of 1800 equal power divider.V. CONCLUSIONA novel power divider with better isolation than the conventional Wilkinson power divider has been presented. Design formulas for the proposed divider have been proven analytically. The ring-like structure provides design flexibility such as unequal power dividing without extra impedance matching networks. The equal and unequal power dividers were designed and tested with out-performed isolation characteristics. Additionally, a 1800 equal power divider was realized by making use of the balanced structure of the parallel-strip line. Similarly, a 1800unequal power divider can be designed. The proposed design leads to realization of a new geometrical configuration for a high-performance power-divider concept.R EFERENCES[1] L. H. Lu, P. Bhattacharya, L. P. B. Katehi, and G. E. Ponchak, ―X-band and K-band lumped Wilkinson power dividers with a micromachined technology,‖ in IEEE MTT-S Int. Microw. Symp. Dig., 2000, pp. 287–290.[2] K. Hettak, G. A. Morin, and M. G. Stubbs, ―Compact MMIC CPW and asymmetric CPS branch-line couplers and Wilkinson dividers using shunt and seri es stub loading,‖ IEEE Trans. Microw. Theory Tech., vol. 53, no. 5, pp. 1624–1635, May 2005.[3] L. Chiu, T. Y. Yum, Q. Xue, and C. H. Chan, ―The folded hybrid ring and its applications in balance devices,‖ in IEEE Eur. Microw. Conf., 2005, pp. 1–4.[4] K. M. Shum, Q. Xue, and C. H. Chan, ―Curved PBG cell and its applications,‖in Asia–Pacific Microw. Conf., 2001, pp. 767–770.[5] D. J. Woo and T. K. Lee, ―Suppression of harmonics in Wilkinson power divider using dual-band rejection by asymmetric DGS,‖ IEEE Trans. Microw. Theory Tech., vol. 53, no. 6, pp. 2139–2144, Jun. 2005.[6] L. Wu, Z. Sun, H. Yilmaz, and M. Berroth, ―A dual-frequency Wilkinson power divider,‖ IEEE Trans. Microw. Theory Tech., vol. 54, no. 1, pp. 278–284, Jan. 2006.[7] M. Chongcheawchamnan, S. Patisang, M. Krairiksh, and I. D. Robertson, ―Tri-band Wilkinson power divider using a three-section transmission-line transformer,‖ IEEE Microw. Wireless Compon. Lett.,to be published.[8] J. S. Lim, S. W. Lee, C. S. Kim, J. S. Park, D. Ahn, and S. W. Nam, ―A 4 : 1 unequal Wilkinson power divider,‖ IEEE Microw. Wireless Compon. Lett., vol. 11, no. 3, pp. 124–126, Mar. 2001.[9] L. H. Lu, Y. T. Liao, and C. R. Wu, ―A miniaturized Wilkinson power divider withCMOSactive inductors,‖ IEEE Microw.Wireless Compon. Lett., vol. 15, no. 11, pp. 775–777, Nov. 2005.[10] X. Xu, R. G. Bosisio, and K. Wu, ―A new six-port junction based on substrate integrated waveguide technology,‖ IEEE Trans. Microw. Theory Tech., vol. 53, no. 7, pp. 2267–2273, Jul. 2006.[11] S. G. Kim and K. Chang, ―Ultrawide-band transitions and new microwave components using double-sided parallel-strip lines,‖ IEEE Trans. Microw. Theory Tech., vol. 52, no. 9, pp. 2148–2152, Sep. 2004.[12] L. Chiu, T. Y. Yum, Q. Xue, and C. H. Chan, ―A wide band compact parallel-strip 180_ Wilkinson power divider for push-pull circuitries,‖ IEEE Microw. Wireless Compon. Lett., vol. 16, no. 1, pp. 49–51, Jan. 2006.[13] C. W. Kao and C. H. Chen, ―Novel uniplanar 180 hybrid-ring couplers with spiral-type phase inverters,‖ IEEE Microw. Guided Wave Lett., vol. 10, no. 10, pp. 412–414, Oct. 2000.[14] B. R. Heimer, L. Fan, and K. Chang, ―Uniplanar hybrid couplers using asymmetrical coplanar striplines,‖ IEEE Trans. Microw. Theory Tech., vol. 45, no. 12, pp. 2234–2240, Dec. 1997.[15] T. Q. Wang and K. Wu, ―Size-reduction and band-broadening design technique of uniplanar hybrid ring coupler using phase inverter for M(H)MIC’s,‖ IEEE Trans. Microw. Theory Tech., vol. 47, no. 2, pp.198–206, Feb. 1999.[16] L. Chiu and Q. Xue, ―A new parallel-strip power divider with enhanced isolation performance,‖ in Proc. Asia–Pacific Microw. Conf., Dec. 2006, pp. 411–416.[17] S. Sun and L. Zhu, ―Stopband-enhanced and size-miniaturized lowpass filters using high-impedance property of offset finite-ground microstrip line,‖ IEEE Trans. Microw. Theory Tech., vol. 53, no. 9, pp.2844–2850, Sep. 2005.具有高隔离度和任意功分比的平行带状功分器摘要:在这篇文章中，提出了一种新型的功率分配器概念，并提及传输线特性阻抗和端口阻抗的高弹性。

收稿日期:2018-06-12Si 衬底GaN 外延生长的应力调控巩小亮，陈峰武，罗才旺，鲍苹，魏唯，彭立波，程文进(中国电子科技集团公司第四十八研究所,湖南长沙410111)摘要:针对Si 衬底GaN 外延生长中由于张应力引起的表面裂纹问题,采用AlN/AlGaN 多缓冲层结构和低温AlN 插入层技术,在标准厚度Si (111)衬底上制备了100mm(4英寸)无裂纹GaN 外延材料。

试验结果表明,AlN/AlGaN 各层厚度的合理搭配和低温AlN 插入层可以起到良好的应力调控效果,无裂纹GaN 层生长厚度达到1.6μm ,晶体质量良好,表面粗糙度低于2nm ;HEMT 结构外延片电学性能测试结果表明Si 衬底GaN 的生长质量满足制备器件的要求。

关键词:Si 衬底GaN ;外延生长;金属有机物化学气相沉积;应力调控中图分类号:TN304.054文献标识码:A文章编号:1004-4507(2018)04-0027-06Stress Control in Epitaxial Growth of GaN on Si SubstrateGONG Xiaoliang ，CHEN Fengwu ，LUO Caiwang ，BAO Ping ，WEI Wei ，PENG Libo ，CHENG Wenjin(The 48th Research Institute of CETC ，Changsha 410111，China)Abstract:This paper aims at solving the problem of surface crack caused by tensile stress in epitaxial growth of GaN on Si substrate.A 100mm (4inch)GaN epitaxial layer was prepared on a standard thickness Si (111)substrate using the AlN/AlGaN multi buffer layer structure and low temperature AlN insertion layer technology.The test results show that properly choosing the thickness of AlN/AlGaN layers and adopting the low temperature AlN insertion layer are quite effective in stress control.The growth thickness of the crack-free GaN layer reaches 1.6μm ，with a high crystal quality and a surface roughness lower than 2nm.Electrical property test of the HEMT structure shows that the growth quality of GaN film on Si substrate meets the requirements of device fabrication.Key words:GaN on Si ；Epitaxial growth ；Metal organic chemical vapor deposition （MOCVD ）；Stress control.GaN 半导体材料因其大禁带宽度、高的击穿场强、高电子饱和速度和较高的热导率等特性，在光电子、微波射频和电子电力器件领域具备优越的应用前景[1]。

高铬铸铁High chromium cast iron高铬铸铁是高铬白口抗磨铸铁的简称，是一种性能优良而受到特别重视的抗磨材料。

它以比合金钢高得多的耐磨性，和比一般白口铸铁高得多的韧性、强度，同时它还兼有良好的抗高温和抗腐蚀性能，加之生产便捷、成本适中，而被誉为当代最优良的抗磨料磨损材料之一。

高铬铸铁属金属耐磨材料、抗磨铸铁类铬系抗磨铸铁的一个重要分支，是继普通白口铸铁、镍硬铸铁而发展起来的第三代白口铸铁。

早在1917年就出现了第一个高铬铸铁专利。

高铬铸铁一般泛指含Cr量在11-30%之间，含C量在2.0-3.6%之间的合金白口铸铁。

High chromium cast iron is of high chromium white cast irons for short, is an excellent performance and highly wear resistant material. Its wear resistance is much higher than the alloy steel, and much higher than the general white cast iron toughness, strength, and it also has good resistance to high temperature and corrosion resistance, and convenient manufacture, low cost, and is regarded as the most excellent abrasive resistant materials.An important branch of high chromium cast iron metal wear resistant materials, antiwear cast iron chromium wear resistant cast iron, is the third generation of white cast iron after the general white cast iron, Ni hard cast iron and developed. As early as in 1917, the first high chromium cast iron patent. High chromium cast iron generally refers to the content of Cr in 11-30%, C content in 2.0-3.6% alloy white cast iron.美国高铬铸铁执行标准为ASTMA532M，英国为BS4844，德国为DIN1695，法国为NFA32401。

Ultra-High Efficiency Photovoltaic Cells for Large Scale Solar Power GenerationYoshiaki NakanoAbstract The primary targets of our project are to dras-tically improve the photovoltaic conversion efficiency and to develop new energy storage and delivery technologies. Our approach to obtain an efficiency over40%starts from the improvement of III–V multi-junction solar cells by introducing a novel material for each cell realizing an ideal combination of bandgaps and lattice-matching.Further improvement incorporates quantum structures such as stacked quantum wells and quantum dots,which allow higher degree of freedom in the design of the bandgap and the lattice strain.Highly controlled arrangement of either quantum dots or quantum wells permits the coupling of the wavefunctions,and thus forms intermediate bands in the bandgap of a host material,which allows multiple photon absorption theoretically leading to a conversion efficiency exceeding50%.In addition to such improvements, microfabrication technology for the integrated high-effi-ciency cells and the development of novel material systems that realizes high efficiency and low cost at the same time are investigated.Keywords Multi-junctionÁQuantum wellÁConcentratorÁPhotovoltaicINTRODUCTIONLarge-scale photovoltaic(PV)power generation systems, that achieve an ultra-high efficiency of40%or higher under high concentration,are in the spotlight as a new technology to ease drastically the energy problems.Mul-tiple junction(or tandem)solar cells that use epitaxial crystals of III–V compound semiconductors take on the active role for photoelectric energy conversion in such PV power generation systems.Because these solar cells operate under a sunlight concentration of5009to10009, the cost of cells that use the epitaxial crystal does not pose much of a problem.In concentrator PV,the increased cost for a cell is compensated by less costly focusing optics. The photons shining down on earth from the sun have a wide range of energy distribution,from the visible region to the infrared region,as shown in Fig.1.Multi-junction solar cells,which are laminated with multilayers of p–n junctions configured by using materials with different band gaps,show promise in absorbing as much of these photons as possible,and converting the photon energy into elec-tricity with minimum loss to obtain high voltage.Among the various types of multi-junction solar cells,indium gallium phosphide(InGaP)/gallium arsenide(GaAs)/ger-manium(Ge)triple-junction cells that make full use of the relationship between band gaps and diverse lattice con-stants offered by compound semiconductors have the advantage of high conversion efficiency because of their high-quality single crystal with a uniform-size crystal lat-tice.So far,a conversion efficiency exceeding41%under conditions where sunlight is concentrated to an intensity of approximately5009has been reported.The tunnel junction with a function equivalent to elec-trodes is inserted between different materials.The positive holes accumulated in the p layer and the electrons in the adjacent n layer will be recombined and eliminated in the tunnel junction.Therefore,three p–n junctions consisting of InGaP,GaAs,and Ge will become connected in series. The upper limit of the electric current is set by the mini-mum value of photonflux absorbed by a single cell.On the other hand,the sum of voltages of three cells make up the voltage.As shown in Fig.1,photons that can be captured in the GaAs middle cell have a smallflux because of the band gap of each material.As a result,the electric currentoutputAMBIO2012,41(Supplement2):125–131 DOI10.1007/s13280-012-0267-4from the GaAs cell theoretically becomes smaller than that of the others and determines the electric current output of the entire tandem cell.To develop a higher efficiency tandem cell,it is necessary to use a material with a band gap narrower than that of GaAs for the middle cell.In order to obtain maximum conversion efficiency for triple-junction solar cells,it is essential to narrow down the middle cell band gap to 1.2eV and increase the short-circuit current density by 2mA/cm 2compared with that of the GaAs middle cell.When the material is replaced with a narrower band gap,the output voltage will drop.However,the effect of improving the electric current balance out-performs this drop in output voltage and boosts the effi-ciency of the entire multi-junction cell.When a crystal with such a narrow band gap is grown on a Ge base material,lattice relaxation will occur in the middle of epitaxial crystal growth because the lattice constants of narrower band-gap materials are larger than that of Ge (as shown in Fig.2).As a result,the carrier transport properties will degrade due to dislocation.Researchers from the international research center Solar Quest,the University of Tokyo,aim to move beyond such material-related restrictions,and obtain materials and structures that have effective narrow band gaps while maintaining lattice matching with Ge or GaAs.To achieve this goal,we have taken three approaches as indicated in Fig.3.These approaches are explained in detail below.DILUTE NITROGEN-ADDED BULK CRYSTAL Indium gallium nitride arsenide (InGaNAs)is a bulk material consists of InGaAs,which contains several percent of nitrogen.InGaNAs has a high potential for achieving a narrow band gap while maintaining lattice matching with Ge or GaAs.However,InGaNAs has a fatal problem,that is,a drop in carrier mobility due to inhomogeneousdistribution of nitrogen (N).To achieve homogeneous solid solution of N in crystal,we have applied atomic hydrogen irradiation in the film formation process and addition of a very small amount of antimony (Sb)(Fig.3).The atomic hydrogen irradiation technology and the nitrogen radical irradiation technology for incorporating N efficiently into the crystal can be achieved only through molecular beam epitaxy (MBE),which is used to fabricate films under high vacuum conditions.(Nitrogen radical irradiation is a technology that irradiates the surface of a growing crystal with nitrogen atoms that are resolved by passing nitrogen through a plasma device attached to the MBE system.)Therefore,high-quality InGaNAs has been obtained only by MBE until now.Furthermore,as a small amount of Sb is also incorporated in a crystal,it is nec-essary to control the composition of five elements in the crystal with a high degree of accuracy to achieve lattice matching with Ge or GaAs.We have overcome this difficulty by optimizing the crystal growth conditions with high precision and devel-oped a cell that has an InGaNAs absorption layer formed on a GaAs substrate.The short-circuit current has increased by 9.6mA/cm 2for this cell,compared with a GaAs single-junction cell,by narrowing the band gap down to 1.0eV.This technology can be implemented not only for triple-junction cells,but also for higher efficiency lattice-matched quadruple-junction cells on a Ge substrate.In order to avoid the difficulty of adjusting the compo-sition of five elements in a crystal,we are also taking an approach of using GaNAs with a lattice smaller than that of Ge or GaAs for the absorption layer and inserting InAs with a large lattice in dot form to compensate for the crystal’s tensile strain.To make a solid solution of N uniformly in GaNAs,we use the MBE method for crystal growth and the atomic hydrogen irradiation as in the case of InGaNAs.We also believe that using 3D-shaped InAs dots can effectively compensate for the tensile strainthatFig.1Solar spectrum radiated on earth and photon flux collected by the top cell (InGaP),middle cell (GaAs),and bottom cell (Ge)(equivalent to the area of the filled portions in the figure)occurs in GaNAs.We have measured the characteristics of a single-junction cell formed on a GaAs substrate by using a GaNAs absorption layer with InAs dots inserted.Figure 4shows that we were able to succeed in enhancing the external quantum efficiency in the long-wavelength region (corresponding to the GaNAs absorp-tion)to a level equal to GaAs.This was done by extending the absorption edge to a longer wavelength of 1200nm,and increasing the thickness of the GaNAs layer by increasing the number of laminated InAs quantum dot layers.This high quantum efficiency clearly indicates that GaNAs with InAs dots inserted has the satisfactory quality for middle cell material (Oshima et al.2010).STRAIN-COMPENSATED QUANTUM WELL STRUCTUREIt is extremely difficult to develop a narrow band-gap material that can maintain lattice matching with Ge orGaAs unless dilute nitrogen-based materials mentioned earlier are used.As shown in Fig.2,the conventionally used material InGaAs has a narrower band gap and a larger lattice constant than GaAs.Therefore,it is difficult to grow InGaAs with a thickness larger than the critical film thickness on GaAs without causing lattice relaxation.However,the total film thickness of InGaAs can be increased as an InGaAs/GaAsP strain-compensated multi-layer structure by laminating InGaAs with a thickness less than the critical film thickness in combination with GaAsP that is based on GaAs as well,but has a small lattice constant,and bringing the average strain close to zero (Fig.3.).This InGaAs/GaAsP strain-compensated multilayer structure will form a quantum well-type potential as shown in Fig.5.The narrow band-gap InGaAs layer absorbs the long-wavelength photons to generate electron–hole pairs.When these electron–hole pairs go over the potential bar-rier of the GaAsP layer due to thermal excitation,the electrons and holes are separated by a built-in electricfieldFig.2Relationship between band gaps and lattice constants of III–V-based and IV-based crystalsto generate photocurrent.There is a high probability of recombination of electron–hole pairs that remain in the well.To avoid this recombination,it is necessary to take out the electron–hole pairs efficiently from the well and transfer them to n-type and p-type regions without allowing them to be recaptured into the well.Designing thequantumFig.3Materials and structures of narrow band-gap middle cells being researched by thisteamFig.4Spectral quantum efficiency of GaAs single-junction cell using GaNAs bulk crystal layer (inserted with InAs dots)as the absorption layer:Since the InAs dot layer and the GaNAs bulk layer are stacked alternately,the total thickness of GaNAs layers increases as the number of stacked InAs dot layers is increased.The solid line in the graph indicates the data of a reference cell that uses GaAs for its absorption layer (Oshima et al.2010)well structure suited for this purpose is essential for improving conversion efficiency.The high-quality crystal growth by means of the metal-organic vapor phase epitaxy (MOVPE)method with excellent ability for mass production has already been applied for InGaAs and GaAsP layers in semiconductor optical device applications.Therefore,it is technologically quite possible to incorporate the InGaAs/GaAsP quantum well structure into multi-junction solar cells that are man-ufactured at present,only if highly accurate strain com-pensation can be achieved.As the most basic approach related to quantum well structure design,we are working on fabrication of super-lattice cells with the aim of achieving higher efficiency by making the GaAsP barrier layer as thin as possible,and enabling carriers to move among wells by means of the tunnel effect.Figure 6shows the spectral quantum effi-ciency of a superlattice cell.In this example,the thickness of the GaAsP barrier layer is 5nm,which is not thin enough for proper demonstration of the tunnel effect.When the quantum efficiency in the wavelength range (860–960nm)that corresponds to absorption of the quan-tum well is compared between a cell,which has a con-ventionally used barrier layer and a thickness of 10nm or more,and a superlattice cell,which has the same total layer thickness of InGaAs,the superlattice cell demonstrates double or higher quantum efficiency.This result indicates that carrier mobility across quantum wells is promoted by even the partial use of the tunnel effect.By increasing the P composition in the GaAsP layer,the thickness of well (or the In composition)can be increased,and the barrier layer thickness can be reduced while strain compensation is maintained.A cell with higher quantum efficiency can befabricated while extending the absorption edge to the long-wavelength side (Wang et al.2010,2012).GROWTH TECHNIQUE FOR STRAIN-COMPENSATED QUANTUM WELLTo reduce the strain accumulated in the InGaAs/GaAsP multilayer structure as close to zero as possible,it is nec-essary to control the thickness and atomic content of each layer with high accuracy.The In composition and thickness of the InGaAs layer has a direct effect on the absorption edge wavelength and the GaAsP layer must be thinned to a satisfactory extent to demonstrate fully the tunnel effect of the barrier layer.Therefore,it is desirable that the average strain of the entire structure is adjusted mainly by the P composition of the GaAsP layer.Meanwhile,for MOVPE,there exists a nonlinear rela-tionship between the P composition of the crystal layer and the P ratio [P/(P ?As)]in the vapor phase precursors,which arises from different absorption and desorption phenomena on the surface.As a result,it is not easy to control the P composition of the crystal layer.To break through such a difficulty and promote efficient optimiza-tion of crystal growth conditions,we have applied a mechanism to evaluate the strain of the crystal layer during growth in real time by sequentially measuring the curvature of wafers during growth with an incident laser beam from the observation window of the reactor.As shown in Fig.7,the wafer curvature during the growth of an InGaAs/GaAsP multilayer structure indicates a periodic behavior.Based on a simple mechanical model,it has become clear that the time changes ofwaferFig.5Distribution of potential formed by the InGaAs/GaAsP strain-compensated multilayer structure:the narrow band-gap InGaAs layer is sandwiched between wide band-gap GaAsP layers and,as a result,it as quantum well-type potential distribution.In the well,electron–hole pairs are formed by absorption of long-wavelength photons and at the same time,recombination of electrons and holes takes place.The team from Solar Quest is focusing on developing a superlattice structure with the thinnest GaAsP barrier layercurvature are proportionate to the strain of the crystal layer relative to a substrate during the growing process.One vibration cycle of the curvature is same as the growth time of an InGaAs and GaAsP pair (Sugiyama et al.2011).Therefore,the observed vibration of the wafer curvature reflects the accumulation of the compression strain that occurs during InGaAs growth and the release of the strain that occurs during GaAsP growth.When the strain is completely compensated,the growth of the InGaAs/GaAsP pair will cause this strain to return to the initial value and the wafer curvature will vibrate with the horizontal line as the center.As shown in Fig.7,strain can be compensated almost completely by adjusting the layer structure.Only by conducting a limited number of test runs,the use of such real-time observation technology of the growth layer enables setting the growth conditions for fabricating the layer structure for which strain has been compensated with highaccuracy.Fig.6Spectral quantum efficiency of GaAs single-junction cell using InGaAs/GaAsP superlattice as theabsorption layer:This structure consists of 60layers of InGaAs quantum wells.The graph also shows data of a reference cell that uses GaAs for its absorption layer (Wang et al.2010,2012)Fig.7Changes in wafer curvature over time during growth of the InGaAs/GaAsP multilayer structure.This graph indicates the measurement result and the simulation result of the curvature based on the layer structure(composition ?thickness)obtained by X-ray diffraction.Since compressive strain is applied during InGaAs growth,the curvature decreases as time passes.On the other hand,since tensile strain is applied during GaAsP growth,the curvature changes in the oppositedirection (Sugiyama et al.2011)FUTURE DIRECTIONSIn order to improve the conversion efficiency by enhancing the current matching of multi-junction solar cells using III–V compound semiconductors,there is an urgent need to create semiconductor materials or structures that can maintain lattice matching with Ge or GaAs,and have a band gap of1.2eV.As for InGaNAs,which consists of InGaAs with several percent of nitrogen added,we have the prospect of extending the band edge to1.0eV while retaining sufficient carrier mobility for solar cells by means of atomic hydrogen irradiation and application of a small quantity of Sb during the growth process.In addition,as for GaNAs bulk crystal containing InAs dots,we were able to extend the band edge to1.2eV and produce a high-quality crystal with enoughfilm thickness to achieve the quantum efficiency equivalent to that of GaAs.These crystals are grown by means of MBE. Therefore,measures that can be used to apply these crys-tals for mass production,such as migration to MOVPE, will be investigated after demonstrating their high effi-ciency by embedding these crystals into multi-junction cells.As for the InGaAs/GaAsP strain-compensated quantum well that can be grown using MOVPE,we are working on the development of a thinner barrier layer while compen-sating for the strain with high accuracy by real-time observation of the wafer curvature.We have had the prospect of achieving a quantum efficiency that will sur-pass existing quantum well solar cells by promoting the carrier transfer within the multilayer quantum well struc-ture using the tunnel effect.As this technology can be transferred quite easily to the existing multi-junction solar cell fabrication process,we strongly believe that this technology can significantly contribute to the efficiency improvement of the latest multi-junction solar cells. REFERENCESOshima,R.,A.Takata,Y.Shoji,K.Akahane,and Y.Okada.2010.InAs/GaNAs strain-compensated quantum dots stacked up to50 layers for use in high-efficiency solar cell.Physica E42: 2757–2760.Sugiyama,M.,K.Sugita,Y.Wang,and Y.Nakano.2011.In situ curvature monitoring for metalorganic vapor phase epitaxy of strain-balanced stacks of InGaAs/GaAsP multiple quantum wells.Journal of Crystal Growth315:1–4.Wang,Y.,Y.Wen,K.Watanabe,M.Sugiyama,and Y.Nakano.2010.InGaAs/GaAsP strain-compensated superlattice solar cell for enhanced spectral response.In Proceedings35th IEEE photovoltaic specialists conference,3383–3385.Wang,Y.P.,S.Ma,M.Sugiyama,and Y.Nakano.2012.Management of highly-strained heterointerface in InGaAs/GaAsP strain-balanced superlattice for photovoltaic application.Journal of Crystal Growth.doi:10.1016/j.jcrysgro.2011.12.049. AUTHOR BIOGRAPHYYoshiaki Nakano(&)is Professor and Director General of Research Center for Advanced Science and Technology,the University of Tokyo.His research interests include physics and fabrication tech-nologies of semiconductor distributed feedback lasers,semiconductor optical modulators/switches,monolithically integrated photonic cir-cuits,and high-efficiency heterostructure solar cells.Address:Research Center for Advanced Science and Technology, The University of Tokyo,4-6-1Komaba,Meguro-ku,Tokyo153-8904,Japan.e-mail:nakano@rcast.u-tokyo.ac.jp。

热电转换薄膜材料制备英文The development of efficient and cost-effective thermoelectric materials has become a crucial focus in the pursuit of sustainable energy solutions. Thermoelectric materials, which can directly convert thermal energy into electrical energy and vice versa, hold immense potential in a wide range of applications, from waste heat recovery to temperature regulation and energy harvesting. One promising approach to enhancing the performance of thermoelectric materials is the utilization of thin-film technology.Thin-film thermoelectric materials possess several advantages over their bulk counterparts. They offer improved power density, enhanced figure of merit (ZT), and the ability to be integrated into compact and flexible devices. The fabrication of high-quality thin-film thermoelectric materials, however, presents unique challenges that require careful consideration of the underlying physics, material properties, and deposition techniques.One of the key factors in the development of efficient thin-film thermoelectric materials is the choice of the material composition. The ideal thermoelectric material should exhibit a high Seebeck coefficient, high electrical conductivity, and low thermal conductivity,resulting in a high ZT value. This delicate balance of properties is often achieved through the careful selection and optimization of the material constituents, as well as the microstructural and nanostructural features.Bismuth telluride (Bi2Te3) and its alloys have been extensively studied as promising thin-film thermoelectric materials due to their relatively high ZT values at room temperature. These materials can be deposited using various thin-film deposition techniques, such as sputtering, evaporation, and chemical vapor deposition (CVD). Each of these methods has its own advantages and challenges, and the choice of the appropriate technique depends on factors such as film thickness, uniformity, and scalability.Sputtering, for example, is a widely used technique for the deposition of thin-film thermoelectric materials. It offers good control over the film composition and microstructure, and can be easily scaled up for large-area deposition. However, sputtering can also introduce defects and impurities in the film, which can adversely affect the thermoelectric performance.Evaporation, on the other hand, is a simpler and more cost-effective deposition method, but it may not provide the same level of control over the film composition and microstructure as sputtering. Chemical vapor deposition, while offering excellent control over the filmproperties, can be more complex and resource-intensive.In addition to the choice of deposition technique, the optimization of the thin-film growth parameters, such as substrate temperature, deposition rate, and post-deposition annealing, is crucial for obtaining high-performance thermoelectric thin films. These parameters can significantly influence the crystalline structure, defect density, and doping concentration of the films, all of which have a direct impact on the thermoelectric properties.Furthermore, the integration of thin-film thermoelectric materials into functional devices requires the development of efficient thermal and electrical contacts, as well as the design of appropriate device architectures. The integration of thin-film thermoelectric materials with other functional layers, such as heat sinks or thermal insulation, can also enhance the overall performance and efficiency of the thermoelectric device.One of the promising avenues for improving the performance of thin-film thermoelectric materials is the use of nanostructuring techniques. By controlling the size, shape, and distribution of nanostructures within the thin films, it is possible to manipulate the electronic and thermal transport properties, leading to enhanced thermoelectric performance. Strategies such as the incorporation of quantum dots, nanowires, or superlattice structures have shownpromising results in enhancing the ZT values of thin-film thermoelectric materials.Another area of active research in the field of thin-film thermoelectric materials is the exploration of novel material compositions and heterostructures. The development of new thermoelectric materials, such as half-Heusler alloys, oxide-based materials, and organic-inorganic hybrid systems, has the potential to expand the range of operating temperatures and improve the overall performance of thin-film thermoelectric devices.In conclusion, the development of high-performance thin-film thermoelectric materials is a critical step towards the realization of efficient and sustainable energy conversion technologies. The careful selection of material compositions, the optimization of deposition techniques, and the integration of advanced nanostructuring and heterostructure design strategies are all essential elements in the ongoing quest to enhance the thermoelectric figure of merit and unlock the full potential of thin-film thermoelectric materials. As research in this field continues to progress, we can expect to see increasingly efficient and practical thermoelectric devices that can contribute to the global effort towards a more sustainable energy future.。

1550 nm high contrast grating VCSELChristopher Chase, Yi Rao, Werner Hofmann, and Connie J.Chang-Hasnain* Department of Eletrical Engineering and Computer Sciences, University of California, Berkeley,CA 94720, USAAbstract: We demonstrate an electrically pumped high contrast grating(HCG) VCSEL operating at 1550 nm incorporating a porton implant-defined aperture. Output powers of ＞1 mW are obtained at room temperature under continuous wave operation. Devices operate continuous wave at temperatures exceeding 60℃. The novel device design, which is grown in a single epitaxy step, may enable lower cost long wavelength VCSELs.References and Links1. C. J. Chang-Hasnain, “Tunable VCSEL,” IEEE J. Sel. Top. Quantum Electron. 6(6), 978–987(2000).2.M. Lackner, M. Schwarzott, F. Winter, B. Kögel, S. Jatta, H. Halbritter, and P. Meissner, “COand CO2 spectroscopy using a 60 nm broadband tunable MEMS-VCSEL at 1.55 μm,” Opt.Lett. 31(21), 3170–3172(2006).3.M. Ortsiefer, R. Shau, G. Böhm, F. Köhler, and M. C. Amann, “Low-threshold index-guided1.5 μm longwavelength vertical-cavity surface-emitting laser with high efficiency,” Appl.Phys. Lett. 76(16), 2179 (2000).4.W. Yuen, G. S. Li, R. F. Nabiev, J. Boucart, P. Kner, R. J. Stone, D. Zhang, M. Beaudoin, T.Zheng, C. He, K.Yu, M. Jansen, D. P. Worland, and C. J. Chang-Hasnain, “High-performance1.6 μm single-epitaxy top-emitting VCSEL,” Electron. Lett. 36(13), 1121–1123 (2000).5.S. Nakagawa, E. Hall, G. Almuneau, J. K. Kim, D. A. Buell, H. Kroemer, and L. A. Coldren,“88 °C, continuouswave operation of apertured, intracavity contacted, 1.55 μm vertical-cavity surface-emitting lasers,” Appl. Phys. Lett. 78(10), 1337 (2001).6.N.Nishiyama, C. Caneau, B. Hall, G. Guryanov, M. Hu, X. Liu, M. Li, R. Bhat, and C. Zah,“Long-Wavelength Vertical-Cavity Surface-Emitting Lasers on InP With Lattice Matched AlGaInAs-InP DBR Grown by MOCVD,” IEEE J. Sel. Top. Quantum Elec tron. 11(5), 990–998 (2005).7. A.Syrbu, A. Mereuta, A. Mircea, A. Caliman, V. Iakovlev, C. Berseth, G. Suruceanu, A.Rudra, E. Deichsel, and E. Kapon, “1550 nm-band VCSEL 0.76 mW singlemode output power in 20–80°C temperature range,” Electron. Lett. 40(5), 306 (2004).8. C.Mateus, M. Huang, L. Chen, C. Chang-Hasnain, and Y. Suzuki, “Broad-Band Mirror(1.12-1.62 μm) Using a Subwavelength Grating,” IEEE Photon. Technol. Lett. 16(7),1676–1678 (2004).9.M.C.Huang,Y.Zhou, and C. J. Chang-Hasnain, “A surface-emitting laser incorporating ahigh-index-contrast subwavelength grating,” Nat. Photonics 1(2), 119–122 (2007).10.Y. Zhou, M. C. Y. Huang, C. Chase, V. Karagodsky, M. Moewe, B. Pesala, F. G. Sedgwick,and C. J. Chang-Hasnain, “High-Index-Contrast Grating (HCG) and Its Applications in Optoelectronic Devices,” IEEE J. Sel.Top. Quantum Electron. 15(5), 1485–1499 (2009). 11. A.Haglund, J. Gustavsson, J. Bengtsson, P. Jedrasik, and A. Larsson, “Design and Evaluationof Fundamental-Mode and Polarization-Stabilized VCSELs With a Subwavelength Surface Grating,” IEEE J. Quantum Electron.42(3), 231–240 (2006).12.M.Ortsiefer, M. Gorblich, Y. Xu, E. Ronneberg, J. Rosskopf, R. Shau, and M. Amann,“Polarization Control in Buried Tunnel Junction VCSELs Using a Birefringent Semiconductor/Di electric Subwavelength Grating,” IEEE Photon. Technol. Lett. 22(1), 15–17 (2010).13.M.C. Y. Huang, Y. Zhou, and C. J. Chang-Hasnain, “A nanoelectromechanical tunable laser,”Nat. Photonics 2(3), 180–184 (2008).14. C. Chase, Y. Zhou, and C. J. Chang-Hasnain, “Si ze effect of high contrast gratings inVCSELs,” Opt. Express 17(26), 24002–24007 (2009).15.V. Karagodsky, B. Pesala, C. Chase, W. Hofmann, F. Koyama, and C. J. Chang-Hasnain,“Monolithically integrated multi-wavelength VCSEL arrays using high-contrast gratings,”Opt. Express 18(2), 694–699 (2010).16.W.Hofmann, C. Chase, M. Müller, Y. Rao, C. Grasse, G. Böhm, M. Amann, and C. J.Chang-Hasnain, “Long-Wavelength High-Contrast Grating Vertical-Cavity Surface-Emitting Laser,” IEEE Photon. J. 2(3), 415–422 (2010).17.P. Gilet, N. Olivier, P. Grosse, K. Gilbert, A. Chelnokov, I. Chung, and J. Mørk,“High-index-contrast subwavelength grating VCSEL,” in Vertical-Cavity Surface-EmittingLasers XIV, J. K. Guenter and K. D. Choquette, eds. (SPIE, 2010), V ol. 7615, p. 76150J.1. IntroductionLong wavelength VCSELs are promising as a low cost laser source for metro area access networks [1], high speed optical interconnects, and diode laser spectroscopy [2]. They have traditionally been more challenging to realize when compared to GaAs-based short wavelength VCSELs because of several additional technical challenges posed by the InP material system, the most difficult of which are the top mirror and current aperture.The InP system is challenging to form a current aperture in because there is no easily oxidizable material in the system, unlike GaAs in which an aluminum oxide current aperture can be easily formed. Traditionally this problem has been overcome by forming a buried tunnel junction in the VCSEL structure [3]. Other approaches to solving this problem have been shown using an oxide aperture formed after pseudomorphic growth of GaAs-based materials above the active region [4], or by etching away layers in the middle of the VCSEL structure [5]. These aperture approaches are technically challenging and add expense to mass manufacturing long wavelength VCSELs.In addition to the challenge of the current aperture, the p-side mirror on the VCSEL also poses problems. The index contrast available in the InGaAIAs/InGaAsP/InP material system is substantially smaller than other VCSEL material systems. This small index contrast means greater than 40 pairs of epitaxial DBR are required on both bottom and top of the VCSEL structure, an extremely challenging technological proposition from the standpoint of epitaxial growth.This necessitates an alternative approach to the p-side mirror of the VCSEL structure. Typically a short current spreading p-region followed by a tunnel junction with n- region and intra-cavity contacts is employed [3]. The top mirror is then formed by either evaporating a dielectric mirror [6], wafer fusing an epitaxially-grown DBR grown on another material system [7], using an Sb-based DBR [5], or a metamorphically grown GaAs/AIGaAs top DBR [4]. These options are technologically challenging from a growth and fabrication standpoint and relatively costly compared to using a monolithic structure already including a p-GaAs/A1GaAs DBR as is used in a short wavelength VCSEL.Our group has reported that a high contrast grating [8], a grating subwavelength in period made of high index bars completely surrounded by a low index media such as oxide or air, cantotally replace the top DBR in a VCSEL [9]. An HCG provides intrinsic polarization control to VCSELs [10], a highly sought feature. Previously subwavelength gratings have been shown to provide polarization differentiation in VCSELs [11, 12], but because they were not completely surrounded by a low index material, they do not provide enough reflectivity for a VCSEL to lase, so a mirror in addition to the subwavelength grating was still required. When integrated on a wavelength-tunable VCSEL, a much faster tuning speed can be achieved due to the small mass of the HCG compared to a conventional DBR [13, 14]. In addition, HCGs can be leveraged to make controllably-defined arrays of VCSELs operating at different wavelengths for use in applications such as wavelength division multiplexing [IS].Electrically-pumped HCG VCSELs have been demonstrated at wavelengths of 850 nm, 980 nm and recently 1.32 um [9,10,16,17]. Many potential applications for VCSE current aperture Ls in next generation access networks and passive optical networks (PONS) require the VCSELs to operate at 1.55 um, and the InP material system is the widespread choice for a 1.55um active region. Here we report for the first time a 1.55 um HCG VCSEL on an InP platform operating continuous wave at room temperature. Due to a great reduction in epitaxial layer thickness above the active region, we can use proton implantation to form a current aperture. This novel design, hence, enables only one epitaxy step and simple fabrication, a feature that is very promising to manufacture high yield, low cost, long wavelength VCSELs.2. VCSEL design and fabricationA cross section of the device is shown schematically in Fig. 1. It consists of, starting from the substrate side, 45 pairs of n-DBR, an InP heat sink layer, an active region with 6 GaAlInAs quantum wells, and a thin layer of p-GaAlInAs, followed by a tunnel junction. Above the tunnel junction there are 2 pairs of n-DBR, followed by a -1.8 um air gap and a 195 nm thick InP high contrast grating. The grating is 12 X 12 μm2wide in all cases described here. Electrical confinement is provided in the structure by a proton implantation at a depth near the tunnel junction. The size of the proton implant aperture is varied from 8 to 25 um. Contacts are deposited on the backside of the wafer and topside on a contact layer above the HCG layer and surrounding the etched HCG.Fig 1. Schematic of a 1550 nm VCSEL with a suspended TE-HCG in place of a typical top DBR. Current confinement isprovided through the use of a proton-implant-defined aperture.The HCG in this structure is～195 nm thick and has a period of～1070 nm and semiconductor width of ～370 nm. The grating is designed to highly reflect light with electric field polarized parallel to the direction of the grating bars (TE), but not to the orthogonal polarization (TM). The grating is optimized so that it has a wide tolerance to the air gap dimension for ease of fabrication. Figure 2(a) shows the simulated reflectivity of HCG as a function of wavelength and light polarization (TE light (blue) has its electric field polarized along the bar direction while TM (red) is polarized perpendicular to the grating bar direction). The simulation is performed using rigorous coupled wave analysis (RCWA) [18]. Over 99% of TE-polarized light is reflected, while only～50% of TM-polarized light is. Figure 2(b) shows the reflectivity of the TE light as a function of wavelength over a smaller reflectivity interval. The TE HCG is over 99% reflective over a 150 nm range. In this simulation, parameters are fixed at: a grating thickness of 195 nm, a period of 1075 nm, and a grating duty cycle of 35% (～370 nm InP/～700 nm air). The HCG material is InP with a refractive index of 3.17 in all cases.Fig.2. a) Reflectivity of the HCG as a function of wavelength and polarization. The grating is highly reflective for TE light (blue, light with electric field polarized along the direction of the grating), and much less so for TM light (red, light polarized perpendicular to the direction of the grating). b) Zoomed in reflectivity of the TE polarization. The grating is over 99%reflective over a bandwidth of 150 nm.Device fabrication was carried out as follows. A current aperture was formed by protecting the aperture area by a thick photoresist, followed by a H + ion implantation with a dosage between 1014cm-2to 1015cm-2 and energy between 250keV to 400keV. A top annular n-contact subsequently was fabricated by lithography, metal evaporation and lift-off. A mesa was etched around the contact ring to the depth of the n-DBRs to electrically isolate the devices from each other.The HCG was defined by electron beam lithography and transferred by several steps of wet etching. In principle, the pattern could also be defined using a standard DUV lithography stepper. The HCG is then released by a selective etch of a sacrificial region below the HCC followed by critical point drying to prevent the structure from being damaged during the drying process. A scanning electron microscope (SEM) image of a completed HCG VCSEL is shown in Fig. 3(a). A zoomed in SEM image of the HCG is shown in Fig. 3(b).Fig. 3. SEM images of a (a) a completed 1550 nm HCG VCSEL (b) Zoomed in image of the high contrast grating, which is just195 nm thick.3.Characteristics3.1 Light-current-voltage characteristicsA series of VCSELs were fabricated with an identical HCG size of 12 X 12 um2and various implant aperture sizes, ranging from 5 to 20 um. The fabricated devices show excellent electrical and optical characteristics. Figure 4(a) shows the light-current (solid) and voltage-current (dashed) characteristics of a VCSEL with a 13 um proton implant aperture at various heat sink temperatures. The VCSELs have a threshold current of～3 mA at room temperature (AT) and lase continuous wave (CW) at temperatures exceeding 60 ℃. The RT peak output power is ～1.1 mW with slope efficiencies >0.25 mW/mA. Other devices with slightly higher thresholds showed up to 1.4 mW peak output powers at room temperature. The devices show a differential resistance of 60-100 Ω depending on aperture size.Fig.4. a) Light-current (solid lines) and voltage-current (dashed lines) characteristics of a HCG VCSEL with a 13 μm proton implant aperture at various heat sink temperatures. Devices show over 1.1 mW output power at room temperature and operate continuous wave to >60° C.b) Spectrum of the same device under various heat sink temperatures. A wavelength shift of0.12nm/K is extractedFigure 4 (b) shows its optical spectrum at a constant bias current of 8 mA at various heat sink temperatures. A wavelength shift of 0.12 nm/K is observed. A thermal resistance of 1.55 K/mW is also obtained, indicating good heat transfer away from the active region. At all biases the VCSELs emit in a single transverse mode with a side mode suppression ratio > 45dB. Single mode emission was seen in VCSELs with proton implant aperture size up to 20um. It should be noted though that the HCG is only 12 X 12 μm2, so the finite HCG size is also providing some transverse mode discrimination.3.2 Optical mode characteristicsFavorable optical mode characteristics for optical communications applications are also obtained due to the use of the HCG and a proton implant aperture. An important characteristic for VCSELs for mid-and long-reach optical communications links is polarization stability, as any polarization instability can have deleterious effects on an optical link. HCG VCSELs are polarization stable due to the high differentiation between the reflectivity in the orthogonal electric field polarizations as is shown in Fig. 2(a). Figure 5(a) shows the polarization-resolved light-current characteristics of a device with a 15 um proton implant aperture and 12 X12um2 HCG. The orthogonal polarization is suppressed by >20 dB (limited by the polarizer in the experimental setup).Since proton implant defined apertures provide little optical index guiding, it is possible to achieve larger size apertures while maintaining a single transverse mode emission profile .This makes the devices ideal for high coupling efficiency to a single mode fiber. The near-field intensity profile of a device with a 15 um proton implant aperture and 12 X12um2 HCG is shown in Fig. 5(b). This device emits in a single fundamental transverse mode with a full width half maximum (FWHM) of ～6.5 um. Generally, the devices have FWHMs of 40-50% of their lithographically defined aperture size. VCSFLs with >20 um proton-implant-defined apertures show no significant higher order transverse mode, since the finite area of HCG reflectivity (12 X12um2)contributes to the suppression of the higher order transverse modes in the largest aperture devices.Fig.5. a) Polarization-resolved light-current characteristics of a 1550 nm HCG VCSEL. A polarization suppression ratio of >20 dB is achieved, with the measurement limited by the polarizer. b) Near field intensity profile of the device at 2.5 X I th. A FWHM of ~6.5μm is obtained with a VCSEL with a proton implant aperture size of 15 μm.4.ConclusionWe present a 1550 nm VCSEL utilizing an HCG as a top mirror and proton implantation to form an electrical aperture. These devices can be simply fabricated using a monolithic epitaxial growth without the need for additional regrowth or dielectric mirror deposition.These devices have >1 mW output power at room temperature and operate continuous wave to greater than 60℃. Single mode operation is achieved with large apertures and no degenerate polarization modes. This simple VCSEL structure is promising for manufacturable, low-cost, long wavelength VCSEL for optical communications applications.AcknowledgementsThe authors would like to acknowledge support from the National Science Foundation through CIAN NSP ERC under grant #EEC-0812072 and a National Science Foundation Graduate Research Fellowship. We also thank the Berkeley Microfabrication Laboratory for their fabrication support.(译文)1550 nm高对比度光栅的VCSEL克里斯托弗大通，易扰，沃纳霍夫曼，康妮J.Chang - Hasnain *电子工程与计算机科学系，加州大学伯克利分校，加州94720，美国摘要：我们展示了一个工作在1550nm波长集成了波顿植入定义光圈的电动泵高对比度光栅（HCG）的VCSEL。

专利名称：EPITAXIALLY GROWN ACOUSTO-OPTIC STRUCTURE AND DEVICE发明人：EISENBEISER, Kurt, W.,FINDER, Jeffrey, M.申请号：US2001048391申请日：20011210公开号：WO02/075437P1公开日：20020926专利内容由知识产权出版社提供摘要：High quality epitaxial layers of monocrystalline piezoelectric materials (106) and acousto-optic materials (108) can be grown overlying monocrystalline substrates (102) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (104) on a silicon wafer (102). The accommodating buffer layer (104) is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide (110). The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Acousto-Optic device (1018) may be formed using the piezoelectric materials (106) and the acousto-optic materials (108) formed using other epitaxially grown monocrystalline layers.申请人：MOTOROLA, INC.地址：US国籍：US代理机构：KOCH, William, E.更多信息请下载全文后查看。