复旦大学王鹏飞半浮栅晶体管Science论文补充材料

/cgi/content/full/341/6146/640/DC1Supplementary Materials forA Semi-Floating Gate Transistor for Low-Voltage Ultrafast Memoryand Sensing OperationPeng-Fei Wang,* Xi Lin, Lei Liu, Qing-Qing Sun, Peng Zhou, Xiao-Yong Liu, Wei Liu, YiGong, David Wei Zhang*Corresponding author. E-mail: pfw@Published 9 August 2013, Science341, 640 (2013)DOI: 10.1126/science.1240961This PDF file includes:Materials and MethodsSupplementary TextFigs. S1 to S8ReferenceMaterials and MethodsThe Semi-Floating-Gate (SFG) transistors were fabricated using the 0.18-μm manufacturing technologies with specifically designed ion-implant processes and photolithography masks. The process flow and device structures are summarized in Fig. S1. First, a phosphorous-doped drain extension region was formed by ion-implantation and a 6-nm gate oxide layer was grown (Fig. S1A). Then a contact window inside the gate oxide was opened by lithography and buffered-HF wet etching. Boron was implanted into this contact window using the photo-resist as a masking layer (Fig. S1B). After that, the first boron-doped poly-Si layer was deposited and contacted the drain extension region via the aforementioned contact window. The Semi-FG pattern was then formed by lithography and reactive ion etching process which stops on the underlying thin SiO2 layer. This plasma-damaged SiO2 layer was then etched away and a 6 nm SiO2 dielectric was grown and nitrided as the inter-poly-dielectric. An n+-doped poly-Si was then deposited and the control-gate structure shown in Fig. S1C was formed. After the spacer processes, arsenic ions were implanted to form the heavily n-doped source and drain regions. The transmission electron microscope (TEM) cross-sections of the device are shown in Fig. S1D. In Fig. S1E, there is a SiO2 layer between the p+ doped poly-Si and the silicon substrate. However, at the position indicated in Fig. S1F, that SiO2 layer was etched away. With the p+ poly contacts the n-doped drain extension region, a floating pn-junction is formed and became the floating-gate of the device. The processed structures show very good process compatibility with the commercial dual-poly-gate manufacturing technology. Only minor modifications on the standard manufacturing process flow are required and high device yield on 8-inch silicon wafer is obtained. To further reduce the cell size, self-aligned techniques can be used to minimize the size of contact window between the p+ poly and the n-extension region.Supplementary TextThe DC characteristics of the SFG transistors were measured using a parameter analyzer (model Agilent B1500) and a RF probe-station. Figs. S2A to S2D compare the device symbols, the typical transfer I-V curves for MOSFET, FG-MOSFET, and two types of SFG transistors. For comparison, a MOSFET has a gate over the semiconductor channel (Fig. S2A) and a floating-gate MOSFET has a floating-gate between the control-gate and the semiconductor channel (Fig. S2B). The floating-gate MOSFET stores logic “0” with high V th or “1” with low V th by changing the amount of charge inside the floating-gate. By adding a diode or a gated diode between the floating-gate and the drain electrode of FG-MOSFET, a SFG transistor is realized. When the SFG transistor is exposed under light, the photo-carriers generated from the pn-junction diode will be partially collected by the floating-gate and in turn the I D-V CG curves will shift accordingly when changing the light intensity and exposure time. The change in threshold voltage of SFG transistor ( ) is expressed as , where is the change of the amount of charges inside the floating-gate (), is the floating-gate capacitance, and is the coupling ratio of control-gate (S1). During the light exposure process, is increased due to the photocurrent flowing into the floating-gate. The device symbol andthe measured transfer I D-V CG curves for SFG transistor for light sensing are shown in Fig. S2C. It can be seen that V th decreases when the light intensity increases. The device symbol and the measured I D-V CG curves of a SFG transistor optimized for memory function are shown in Fig. S2D. Compared to the SFG transistor shown in Fig. S2C, this SFG cell extends the control-gate over the pn-diode. A gate controlled diode or Tunneling FET (TFET) is formed and connects the semi-floating-gate to the drain. As a result, the TFET can now be used to charge or discharge the floating-gate. The current of TFET depends on the band-to-band tunneling generation rate, i.e. . G BTBT is the band-to-band tunneling generation rate, and it is expressed as. A BTBT and B BTBT are constants, E g is the band-gap energy, and E is the magnitude of the electric field. With a higher V D, the electric field increases and the charge current increases exponentially. As shown in Fig. S2D, the threshold voltage decreases when the drain voltage increases. Fast switching behavior is also observed in the transfer I D-V CG curves. The subthreshold swing even reaches 30 mV/dec when V D equals 3.0V.Because SFG transistor has an entirely new device structure, process and device simulations were carried out using Silvaco TCAD tools before device fabrication. First, the process simulations were performed. The resulted structure was then imported to the device simulator for transient behavior simulation. The ion-implantation conditions were designed for the optimized device performance from the device simulation. Asymmetric doping profiles for the source and drain of the embedded P-TFET are specifically designed to obtain the favorable device electrical behavior. Since the processing parameters were obtained from the process simulation results, the simulated structure is almost identical to the experimental device structure shown in Fig. S1D. The models for simulating a conventional MOSFET were included in the SFG transistor simulation. In addition, Kane’s local band-to-band tunneling model was included for simulating the tunneling current during the device operation. Fig. S3A - S3D display the simulated device structures with current and potential contours. The writing-1 operation is with V CG = -2.0 V and V D = 2.0 V. During the writing-1 operation, the drain is positively biased and the semi-floating-gate has a negative potential, resulting in current flows from the drain to the semi-floating-gate (Fig. S3A). The writing-0 operation is with V CG = 2.0 V and V D = 0 V. During the writing-0 operation, the n+ drain is biased with 0 V and the semi-floating-gate potential is elevated by the capacitive coupling of increased V CG, resulting in current flows from the semi-floating-gate to the drain (Fig. S3B). After writing-1 and writing-0 operations, the potential contours for the “1” and “0” devices at the standby status are plotted in Fig. S3C and S3D. It can be seen that the semi-floating-gate potential of the “1” state is 0.75 V, which is 1.64 V higher than that of the “0” state with the same bias conditions.The transient electrical behavior of the simulated device is shown in Fig. S3E. With the band-to-band tunneling model turned on, the high-speed memory function is realized (black line in the read-out current subfigure of Fig. S3E). It is found from the simulation that the gate-controlled band-to-band tunneling current is the key to high speed writingoperation, especially at the nano-second level. The green line in the read-out current subfigure of Fig. S3E is simulated with the band-to-band tunneling model turned off. It can be seen that writing-1 operation does not work with the same voltage setting. For comparison, the measured transient operation characteristic of the SFG transistor is shown in Fig. S3F. The transient behavior of the measured device is similar to the simulated device with band-to-band tunneling model.The transient behaviors of SFG transistors were measured using the circuit configuration shown in Fig. S4A. The measurement environment includes a RF probe-station, a pulse generator, a transimpedance amplifier circuit, and a high-speed oscilloscope. Two channel signal pulses were generated by the pulse generator (Agilent 81160A) and coupled to the drain and the control-gate electrodes of SFG transistor. A transimpedance amplifier circuit (Fig. S4B) was designed to convert the read-out current of SFG transistor to voltage signal for oscilloscope tracing. In Fig. S4C, the examples of traces captured by the oscilloscope during transient operation are shown. The writing-1 operation was performed by pulses of V D = 2V and V CG = -2V for 3 ns. Then, during the read operation, the voltage drop on the feedback resistor R f was measured by the oscilloscope and then converted to the I drain signal shown in Fig. S4D. It can be seen the readout current is about 2 μA after a 3-ns writing “1” operation. Unlike the conventional DRAM cell, the read operation of the SFG memory device is non-destructive because of its gain cell nature, which means no write-back operation is needed after the reading operation.In order to evaluate the operation speed of SFG transistor for memory application, short writing time with the target pulse width of 0.6 ns was executed (Fig. S5A). Due to the parasitic capacitance of the measurement cables, the rising / falling edges were 0.9 ns and the actual peak width at half height (PWHH) was increased to 1.3 ns. However, the writing-1 and writing-0 operations were successfully demonstrated in Fig. S5B. Meanwhile, it was found that the off-chip read-out circuit oscillates at the beginning of reading operation. Figs. S5B to S5D show the transient operation of the devices with different reading operation time. The reading operation duration was 9 μs in Fig. S5B. First, a writing-1 operation was performed with V D= 2V and V CG= -1.8V. A read-out current of about 1.5 μA was measured for the “1” cell. Then, a writing-0 operation was performed with V D= 0V and V CG= 2V. A very small current representing “0” was measured for the “0” cell. It can be seen that the read-out current oscillates at the beginning of the reading operation. With longer reading time such as 22.4 μs and 45 μs shown in Figs. S5C and S5D, the read-out current became stable. The oscillation was caused by the amplification circuit board (Fig. S4B) which can be improved by using the on-chip read-out circuits. Meanwhile, higher operation speed is expected by reducing the rising / falling edges of the pulses when using the integrated supporting circuits.In Figure S6A, 40 test devices were tested. The operation sequence was writing-0, reading, writing-1, and then reading. A “0” could be written into the transistor with V D of -1V and V CG of 2 V for 3 ms. During the subsequent reading operation, a very small drain current of 30 nA was measured with V D = 2 V and V CG = 2 V. After a writing-1 operation at V D =2 V and V CG = -2 V for 3 ms, the threshold voltage was lowered and a large draincur rent of about 2 μA was measured with V D = 2 V and V CG = 2 V. The wafer map of the reading-1 drain current of 40 test devices showed high uniformity across the whole wafer. The retention time and operation endurance properties were evaluated. In Fig. S6B, the retention time for “0” cell reaches 1 second at room temperature, while the “1” cell does not have retention issue because the semi-floating-gate voltage will be pinned to the drain voltage in the standby state. The retention performance of “0” is good because of the low leakage current of reversely biased p-n structure in the standby status. In Fig. S6C, the device operation endurance was investigated by repeating the full operation sequences. Almost no degradation was observed for 1012cycles of operation. The extrapolated endurance reaches 1015, which is far beyond the endurance of 106 for the conventional floating-gate memory cell.As a memory device, the immunity to various disturb mechanisms is also very important. Figs. S7A to S7F show the disturb properties of SFG memory cell measured at room temperature. Six types of disturb mechanisms on “1” and “0” cells are characterized. Most of the disturb endurances exceed 100 ms except for the disturbance of the writing-0 control-gate voltage on the “1” cell when V D at standby status is set to 1.0 V. During this writing-0 V CG disturb with V CG = 2.0 V and V D = 1.0 V, the pn junction will be weakly forward-biased if “1” is already stored inside the cell. The disturb endurances can be further improved by optimizing the operation voltages and the operation sequences. Using the image sensing SFG transistor, an imaging array can be configured. In Fig. S8, the schematic view of the SFG image sensor array is shown. The source lines and bit lines are arranged above the shallow trench isolation (STI) structure to maximize the fill factor. Using SFG cell as an APS cell, the pixel density of image sensing chip can be increased and the reading operation becomes non-destructive.Fig. S1.Brief summary of the process flow for fabricating the SFG transistor (A to C) and the TEM pictures of SFG transistor along the channel direction (D to F). Inset E is taken from the MOSFET channel where poly-Si on SiO2 can be seen. Inset F is taken from the contact interface between semi-floating-gate and n-doped drain extension region whereno oxide interface exists.Fig. S2Device symbols and transfer characteristics for MOSFET (A), FG-MOSFET (B), and SFG transistors (C, D). The semi-floating-gate is realized by connecting the floating-gate of FG-MOSFET to the drain via a pn junction diode. When the diode works as a photo-diode, photo-sensing function can be realized. When extending the control-gate over the diode, an embedded TFET is formed and dramatically accelerates the writing-1operation.Fig. S3(A, B) Simulated current contours of writing-1 operation and writing-0 operation. During the writing-1 operation, the drain is positively biased and the semi-floating-gate has a negative potential. Current will flow from the drain to the semi-floating-gate. During the writing-0 operation, the n+ drain is biased with 0 V and the semi-floating-gate potential is elevated by the capacitive coupling of increased V CG. Current will flow from the semi-floating-gate to the drain. (C, D) Simulated potential contours for the “1” and “0” devices at the standby state. The semi-floating-gate potential of the “1” state is higher than that of the “0” state with the same external voltages. (E) Simulated transient operation of the SFG transistor. V CG, V D, and the read out I D are displayed separately. In the read out I D figure the simulation results with or without the band-to-band tunneling model are compared. Device does not work when the band-to-band tunneling model is turned off in the simulation. (F) Experimental transient operations are shown for comparison with thesimulation results of Fig. S3E.Fig. S4(A) Transient measurement circuit. The measurement environment includes a RF probe-station, a pulse generator, a transimpedance amplifier circuit, and a high-speed oscilloscope. (B) Specific transimpedance amplifier circuit for converting the current signal to voltage signal for oscilloscope tracing. (C) Examples of measured voltage signals shown on the screen of oscilloscope. (D) Control-gate voltage, drain voltage, and the read-out current of a SFG transistor using 3-ns writing-1 pulse. The voltages are measured directly and the read-out current is converted from the voltage-drop on thefeedback resistor.Fig. S5(A) Measured drain voltage and control-gate voltage pulses for writing “1” and writing “0”, where the peak-width-at-half-height (PWHH) is measured as 1.3 ns. Transient measurement sequence of writing “1” - standby - reading - writing “0” - standby -reading with various reading pulse widths of 9 μs (B), 22.5 μs (C), and 45μs (D).Fig. S6(A) Measured reading-1 drain current wafer map and two transient operation cycles of 40 SFG transistors. The operation sequence is writing-0, reading, writing-1, and then reading. (B) Data retention time of “1” and “0” at room temperature. The read-out operation is performed with various standby periods after the writing operation. (C) Measured operation endurance property. Full writing-reading sequences are repeated with3 ns writing time.Fig. S7Disturb performances of SFG memory cell measured at room temperature. (A) Writing-1 V D disturb on the “1” and “0” cells. (B) Writing-1 V CG disturb on the “1” and “0” cells.(C) Writing-0 V D disturb on the “1” and “0” cells. (D) Writing-0 V CG disturb on the “1” and “0” cells. (E) Reading-operation V D disturb on the “1” and “0” cells. (F) Reading-operation V CG disturb on the “1” and “0” cells.Fig. S8Schematic view of the SFG image sensor array. The source lines and bit lines arearranged above the shallow trench isolation (STI) structure to maximize the fill factor.ReferencesS1. P. Pavan, L. Larcher, and A. Marmiroli, Floating gate devices: operation and compact modeling (Kluwer Acdemic Publisher, Dordrecht, 2004), pp. 37-40.。