摘 要21世纪以来，音频电子产品市场增长势头迅猛，越来越多的消费电子产品如MP3播放器、PMP等都要求高品质音频功能。
而实现此功能需要高性能的音频编解码芯片，因此研究音频系统中的DAC具有广泛的现实意义。
本文重点研究了音频DAC中的数字部分：过采样插值滤波器和数字ΔΣ调制器。
详细分析了过采样技术、插值滤波器的原理以及数字ΔΣ调制器的原理、结构和稳定性。
对于插值滤波器，首先选择合适的数字滤波器，然后根据系统的设计指标采用多级实现插值滤波器，最后在算法级分别设计、优化和仿真验证插值滤波器；对于数字ΔΣ调制器，首先选择合适的结构，然后根据理论分析和matlab仿真结果，确定数字ΔΣ调制器的阶数和量化比特数，最后根据系统设计指标与电路面积的考虑，在算法级设计、优化和仿真验证数字ΔΣ调制器。
采用Verilog HDL电路实现整个音频DAC的数字部分；为了节省电路面积，利用了多种方式，如采用CSD编码实现常系数乘法器，优化ΔΣ调制器的系数以减少乘法器数量，插值滤波器的实现采用时分复用共享乘法器等；为了降低功耗，对半带滤波器采用了多相分解技术。
此外，通过FPGA的综合实现来验证整个系统的正确性。
对于CIC滤波器，提供了一种易于RTL实现并能有效补偿通带衰减的方法。
本文通过对ΔΣ DAC理论的深入研究，尤其是插值滤波器和数字ΔΣ调制器部分，设计并实现了音频DAC的数字部分，最后通过了FPGA综合仿真验证，一共使用了1971个LE，3672bit的嵌入式RAM，电路规模大约为3万门。
最后对后仿真的结果进行测试，其信噪比可达到102.83dB，完全达到了预期的设计指标。
关键词：数模转换器，过采样，插值滤波器，ΔΣ调制器，噪声整形AbstractAudio electronics market grows rapidly since the 21st century. More and more consumer electronics, such as MP3 players, PMP, require high-quality audio performance. And the realization of this performance requires high-performance audio codec chip, the research of the DAC audio system has a wide range of practical significance.This paper focuses on the digital part of the audio DAC, including oversampling digital interpolation filters and ΔΣ modulator. Analyzes the oversampling technique, the principle of interpolation filters and the digital ΔΣ modulator principle, structure and stability.For the interpolation filters, first selects the appropriate digital filter, and then implements the multi-level interpolation filters according to the system specifications, finally designs, optimizes and simulates the interpolation filter in the algorithm level; For digital ΔΣ modulator, first selects appropriate structure, and determines the digital ΔΣmodulator orders and the number of the quantization bits according to the theoretical analysis and matlab simulation results, finally according to the system design specifications and consideration of the circuit area, designs, optimizes and simulates the digital ΔΣ Modulator .Using Verilog HDL to implement the digital part of the audio DAC; In order to save circuit area, using a variety of ways, such as the use CSD coding constant coefficient multipliers, optimizes the coefficient of ΔΣ modulator to reduce the number of multipliers, shares multiplier for implementation of the interpolation filter by time division multiplexing, etc.; In order to reduce the power consumption of half-band interpolation filter, use poly phase decomposition technique.In addition, verify the integrated system using FPGA. For the CIC filter, provides an effective compensation method, that is easy to RTL implementation.Based on the theoretical study on the ΔΣ DAC, specially the interpolation filter and the digital ΔΣ modulator, designs and implements the digital part of the audio DAC, and finally synthesizes and post-simulates by using the FPGA. The circuit consumes 1971 LEs and 3672bits embedded RAM, which equivalents to 30,000 logic gate. Finally, the SNR of the test result is 102.83dB, which fully achieves the desired design specifications.Key Words: digital analog converter, oversampling, interpolation filter, ΔΣmodulator,noise shaping独创性声明本人声明所呈交的学位论文是我个人在导师指导下进行的研究工作及取得的研究成果。
