中国保险汽车安全指数CIASI——正面25%偏置碰撞试验规程

择CPU再选择其他的配件，当然这也没什么不对。

只是选择了CPU就应该选择与之相适应的主板，而其余的配件就必须与主板相配套，那么了解主板芯片组的特性就显得非常重要了。

本文的目的就是让那些购机、升级的菜鸟朋友们了解芯片组特性，再根据自己的需求确定主板，之后，有方向地去选择内存、显卡、硬盘等主要配件。

Intel芯片组：一、845系列芯片组包括：支持SDRAM的845芯片组、支持DDR266的845D芯片组、支持DDR266以及FSB533的845E/G/GL芯片组、支持DDR333以及FSB533的845PE/GE/GV 芯片组等诸多子产品。

845系列芯片组的82845E/82845GL/82845G/82845GV/82845GE/82845PE，除82845GL以外都支持533MHz FSB（82845GL只支持400MHz FSB），支持内存方面，所有845系列北桥都支持最大2GB内存。

82845GL/82845E支持DDR 266，其余都支持DDR 333。

除82845GL/82845GV之外都支持AGP 4X规范。

所有的533Mhz 外频芯片组都将支持Hyper-Threading（超线程技术）。

但对于845G 芯片组来说，即使升级BIOS也不能支持Hyper-Threading ，因为它的硬件架构不允许其支持Hyper-Threading。

而i845E 和850E就可以通过升级BIOS 来获得支持。

Intel将发布845G B-step以取代845G A-step芯片组，而且之后的845GV、GE、PE和Springdale都将支持Hyper-Threading。

845E芯片组对于845D芯片组来说，其实并没有重大改变，仅仅是使用了支持USB2.0的ICH4和支持FSB533而已，但845D芯片组也同样能够支持FSB533，而且经过超频之后内存子系统性能更高，整体甚至超过了845PE芯片组。

AT25128B and AT25256BSPI Serial EEPROM128K (16,384 x 8), 256K (32,768 x 8)DATASHEET Features●Serial Peripheral Interface (SPI) Compatible●Supports SPI Modes 0 (0,0) and 3 (1,1)Data Sheet Describes Mode 0 Operation●Low-voltage and Standard-voltage OperationV CC = 1.8V to 5.5V●20MHz Clock Rate (5V)●64-byte Page Mode and Byte Write Operation●Block Write ProtectionProtect 1/4, 1/2, or Entire Array●Write Protect (WP) Pin and Write Disable Instructions for Both Hardware andSoftware Data Protection●Self-timed Write Cycle (5ms max)●High ReliabilityEndurance: 1,000,000 Write CyclesData Retention: 100 Years●Green (Pb/Halogen-free/RoHS Compliant) Packaging Options●Die Sales: Wafer Form, Waffle Pack, and Bumped WafersDescriptionThe Atmel® AT25128B/256B provides 131,072/262,144 bits of Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) organized as16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The AT25128B/256B is available in space saving JEDEC SOIC, TSSOP, UDFN, and VFBGA packages.The AT25128B/256B is enabled through the Chip Select pin (CS) and accessed via a 3-Wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate erase cycle is required before write.Block Write protection is enabled by programming the status register with one of four blocks of Write Protection. Separate Program Enable and Program Disable instructions are provided for additional data protection. Hardware Data Protection is provided via the WP pin to protect against inadvertent write attempts. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.AT25128B/256B [DATASHEET]Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_01201521.Pin ConfigurationsTable 1-1.Pin Configurations 2.Absolute Maximum Ratings*Operating Temperature . . . . . . . . . . .-55︒C to +125︒C Storage Temperature. . . . . . . . . . . . .-65︒C to +150︒C Voltage on any pinwith respect to ground . . . . . . . . . . . . . -1.0V to +7.0V Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V DC Output Current. . . . . . . . . . . . . . . . . . . . . . .5.0mA*Notice:Stresses beyond those listed under “AbsoluteMaximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions forextended periods may affect device reliability.Note: Drawings are not to scale.8-lead SOICCS SO WP GNDV CC HOLD SCK SI12348765Top ViewTop View8-lead TSSOP12348765CS SO WP GNDV CC HOLD SCK SIV CC HOLD SCK SICS SO WP GND123487658-ball VFBGABottom View8-pad UDFNBottom ViewV CC HOLD SCK SI CS SO WP GND123487653AT25128B/256B [DATASHEET]Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_0120153.Block DiagramFigure 3-1.Block DiagramV CCAT25128B/256B [DATASHEET]Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_01201544.Electrical Characteristics4.1Pin Capacitance (1)Table 4-1.Pin CapacitanceNote:1.This parameter is characterized and is not 100% tested.4.2DC CharacteristicsTable 4-2.DC CharacteristicsNote:1.V IL min and V IH max are reference only and are not tested.Applicable over recommended operating range from T A = 25°C, f = 1MHz, V CC = +5V (unless otherwise noted).Applicable over recommended operating range from: T AI = -40︒C to +85︒C, V CC = +1.8V to +5.5V, (unless otherwise noted).5AT25128B/256B [DATASHEET]Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_0120154.3AC CharacteristicsTable 4-3.AC CharacteristicsApplicable over recommended operating range from T AI = -40 to +85°C, V CC = As Specified, CL = 1 TTL Gate and 30pF (unless otherwise noted).AT25128B/256B [DATASHEET]Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_0120156Note:1.This parameter is characterized and is not 100% tested.5.Serial Interface DescriptionMaster: The device that generates the serial clock.Slave: Because the Serial Clock pin (SCK) is always an input, the AT25128B/256B always operates as a slave.Transmitter/Receiver: The AT25128B/256B has separate pins designated for data transmission (SO) and reception (SI).MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.Serial Opcode: After the device is selected with CS going low, the first byte will be received. This byte contains the opcode which defines the operations to be performed.Invalid Opcode: If an invalid opcode is received, no data will be shifted into the AT25128B/256B, and the serial output pin (SO) will remain in a high-impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication.Chip Select: The AT25128B/256B is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the SO pin will remain in a high-impedance state.Hold: The HOLD pin is used in conjunction with the CS pin to select the AT25128B/256B. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high-impedance state.Write Protect: The Write Protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is one, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is zero. This will allow the user to install the AT25128B/256B in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to one.Table 4-3.AC Characteristics (Continued)Applicable over recommended operating range from T AI = -40 to +85°C, V CC = As Specified, CL = 1 TTL Gate and 30pF (unless otherwise noted).7AT25128B/256B [DATASHEET]Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015Figure 5-1.SPI Serial InterfaceMaster :MicrocontrollerSlave :AT25128B/256BAT25128B/256B [DATASHEET]Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_01201586.Functional DescriptionThe AT25128B/256B is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the 6800 series of microcontrollers.The AT25128B/256B utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Figure 6-1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition.Table 6-1.Instruction Set for the AT25010B/020B/040BWrite Enable (WREN): The device will power-up in the Write Disable state when V CC is applied. Allprogramming instructions must therefore be preceded by a Write Enable instruction. The WP pin must be held high during a WREN instruction.Write Disable (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin.Read Status Register (RDSR): The Read Status Register instruction provides access to the status register. The Read/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction.Table 6-2.Status Register FormatTable 6-3.Read Status Register Bit Definition9AT25128B/256B [DATASHEET]Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015Write Status Register (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128B/256B is divided into four array segments. None, one-quarter (¼), one-half (½), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be read-only. The block write protection levels and corresponding status register control bits are shown in Table 6-4.Bits BP1, BP0, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, t WC , RDSR).Table 6-4.Block Write Protect BitsThe WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is one. The hardware write protection is disabled when either the WP pin is high or the WPEN bit is zero. When the device is hardware write protected, writes to the Status Register including the Block Protect bits, the WPEN bit, and the block protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected.Note:When the WPEN bit is hardware write protected, it cannot be changed back to zero as long as the WP pin is held low.Table 6-5.WPEN Operation Read Sequence (READ): Reading the AT25128B/256B via the SO pin requires the following sequence. After the CS line is pulled low to select a device, the Read opcode is transmitted via the SI line followed by the byte address to be read (Table 6-6). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The Read Sequence can be continued since the byte address isautomatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll-over to the lowest address allowing the entire memory to be read in one continuous read cycle.AT25128B/256B [DATASHEET]Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_01201510Write Sequence (WRITE): In order to program the AT25128B/256B, the Write Protect pin (WP) must be held high and two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then a Write (WRITE) instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection level. During an internal write cycle, all commands will be ignored except the RDSR instruction.A Write instruction requires the following sequence. After the CS line is pulled low to select the device, the Write opcode is transmitted via the SI line followed by the byte address and the data (D7 D0) to be programmed (see Table 6-6 for the address key). Programming will start after the CS pin is brought high. The low-to-hightransition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.The Ready/Busy status of the device can be determined by initiating a Read Status Register (RDSR)instruction. If Bit 0 is one, the write cycle is still in progress. If Bit 0 is zero, the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle.The AT25128B/256B is capable of an 64-byte Page Write operation. After each byte of data is received, the six low-order address bits are internally incremented by one; the high-order bits of the address will remain constant. If more than 64 bytes of data are transmitted, the address counter will roll-over, and the previously written data will be overwritten. The AT25128B/256B is automatically returned to the Write Disable state at the completion of a write cycle.Note:If the WP pin is brought low or if the device is not Write Enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to reinitiate the serial communication.Table 6-6.Address Key7.Timing Diagrams — SPI Mode 0 (0,0)Figure 7-1.Synchronous Data Timing (for Mode 0)Figure 7-2.WREN TimingFigure 7-3.WRDI TimingSOSISCKCSV V ILV V ILV V ILV V SOSISCK CSWREN OpcodeHI-ZSOSISCK CSWRDI OpcodeHI-ZAT25128B/256B [DATASHEET]12Figure 7-5.WRSR TimingFigure 7-6.READ TimingSOSISCKCSSOSISCKCSInstruction76543210Data InHigh-impedanceMSBSOSI SCKCSFigure 7-8.HOLD TimingSOSISCKCSInstructionByte AddressData InHigh-impedance7654321015 14 13 (3)210HOLDSOSCKCSt HDAT25128B/256B [DATASHEET]148.Ordering Code DetailAtmel DesignatorProduct FamilyDevice DensityDevice RevisionShipping Carrier OptionOperating Voltage128 = 128 kilobit 256 = 256 kilobit25 = Standard SPI Serial EPPROMB or Blank = Bulk (Tubes)T = Tape and Reel, Standard Quantity Option E = Tape and Reel, Expanded Quantity OptionL = 1.8V to 5.5VPackage Device Grade or Wafer/Die ThicknessH = Green, NiPdAu Lead Finish, Industrial Temperature Range (-40°C to +85°C)U = Green, Matte Sn Lead Finish, Industrial Temperature Range (-40°C to +85°C)11 = 11mil Wafer ThicknessPackage OptionSS = JEDEC SOIC X = TSSOP MA = UDFN C = VFBGAWWU = Wafer UnsawnWDT = Die in Tape and ReelA T 25128B -S S H L -B9.Part MarkingsNote: 1.Contact Atmel Sales for Wafer sales.AT25128B/256B [DATASHEET]1611.18S1 — 8-lead JEDEC SOICAT25128B/256B [DATASHEET]1811.28X — 8-lead TSSOP11.38MA2 — 8-pad UDFNAT25128B/256B [DATASHEET]2011.48U2-1 — 8-ball VFBGA21AT25128B/256B [DATASHEET]Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_01201512.Revision HistoryX X X X X XAtmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311F: (+1)(408) 436.4200| © 2015 Atmel Corporation. / Rev.: Atmel-8698E-SEEPROM-AT25128B-256B-Datasheet_012015.Atmel ®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities ®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others.DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended,authorized, or warranted for use as components in applications intended to support or sustain life.SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems.Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.。

Mellanox OFED for Linux Installation GuideRev 1.5.1Mellanox Technologies350 Oakmead Parkway, Suite 100Sunnyvale, CA 94085U.S.A.Tel: (408) 970-3400Fax: (408) 970-3403Mellanox Technologies, Ltd.PO Box 586 Hermon Building Yokneam 20692Israel Tel: +972-4-909-7200Fax: +972-4-959-3245© Copyright 2010. Mellanox Technologies, Inc. All Rights Reserved.Mellanox®, BridgeX®, ConnectX®, InfiniBlast®, InfiniBridge®, InfiniHost®, InfiniPCI®, InfiniRISC®, InfiniScale®, andVirtual Protocol Interconnect are registered trademarks of Mellanox Technologies, Ltd.CORE-Direct , FabricIT, and PhyX are trademarks of Mellanox Technologies, Ltd.All other marks and names mentioned herein may be trademarks of their respective companies.Document Number: 2914Rev 1.5.1Mellanox Technologies 2NOTE:THIS HARDWARE, SOFTWARE OR TEST SUITE PRODUCT (“PRODUCT(S)”) AND ITS RELATED DOCUMENTATION ARE PRO-VIDED BY MELLANOX TECHNOLOGIES “AS-IS” WITH ALL FAULTS OF ANY KIND AND SOLELY FOR THE PURPOSE OF AIDING THE CUSTOMER IN TESTING APPLICATIONS THAT USE THE PRODUCTS IN DESIGNATED SOLUTIONS. THE CUS-TOMER'S MANUFACTURING TEST ENVIRONMENT HAS NOT MET THE STANDARDS SET BY MELLANOX TECHNOLOGIES TO FULLY QUALIFY THE PRODUCTO(S) AND/OR THE SYSTEM USING IT. THEREFORE, MELLANOX TECHNOLOGIES CAN-NOT AND DOES NOT GUARANTEE OR WARRANT THAT THE PRODUCTS WILL OPERATE WITH THE HIGHEST QUALITY . ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING , BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MER-CHANTABILITY , FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL MELLANOX BE LIABLE TO CUSTOMER OR ANY THIRD PARTIES FOR ANY DIRECT, INDIRECT, SPECIAL, EXEM-PLARY , OR CONSEQUENTIAL DAMAGES OF ANY KIND (INCLUDING , BUT NOT LIMITED TO, PAYMENT FOR PROCURE-MENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY , WHETHER IN CONTRACT, STRICT LIABILITY , OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY FROM THE USE OF THE PRODUCT(S) AND RELATED DOCUMENTATION EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.Mellanox OFED for Linux User’s Manual Rev 1.5.1 InstallationThis chapter describes how to install and test the Mellanox OFED for Linux package on a singlehost machine with Mellanox InfiniBand and/or Ethernet adapter hardware installed. The chapterincludes the following sections:•“Hardware and Software Requirements” (page 3)•“Downloading Mellanox OFED” (page 4)•“Installing Mellanox OFED” (page 4)•“Uninstalling Mellanox OFED” (page 15)Hardware and Software RequirementsHardware RequirementsPlatforms• A server platform with an adapter card based on one of the following Mellanox Technologies’InfiniBand HCA devices:-MT25408 ConnectX®-2 (VPI, IB, EN, FCoE) (firmware: fw-ConnectX2)-MT25408 ConnectX® (VPI, IB, EN, FCoE) (firmware: fw-25408)-MT25208 InfiniHost® III Ex (firmware: fw-25218 for Mem-Free cards, and fw-25208 for cards withmemory)-MT25204 InfiniHost® III Lx (firmware: fw-25204)-MT23108 InfiniHost® (firmware: fw-23108)Note For the list of supported architecture platforms, please refer to the Mellanox OFEDRelease Notes file.Required Disk Space for Installation•400MBSoftware RequirementsOperating System•Linux operating systemNote For the list of supported operating system distributions and kernels, please refer to the Mellanox OFED Release Notes file.Installer Privileges•The installation requires administrator privileges on the target machineMellanox Technologies3Rev 1.5.1Mellanox Technologies 4Downloading Mellanox OFEDStep 1.Verify that the system has a Mellanox network adapter (HCA/NIC) installed by ensuringthat you can see ConnectX or InfiniHost entries in the display.The following example shows a system with an installed Mellanox HCA:host1# lspci -v | grep Mellanox02:00.0 InfiniBand: Mellanox Technologies MT25418 [ConnectX IB DDR, PCIe 2.0 2.5GT/s] (reva0)Step 2.Download the ISO image to your host.The image’s name has the format MLNX_OFED_LINUX-<ver>-<OS label>.iso. You candownload it from > Products > IB SW/Drivers.Step e the md5sum utility to confirm the file integrity of your ISO image. Run the followingcommand and compare the result to the value provided on the download page.host1$ md5sum MLNX_OFED_LINUX-<ver>-<OS label>.isoInstalling Mellanox OFEDThe installation script, mlnxofedinstall , performs the following:•Discovers the currently installed kernel•Uninstalls any software stacks that are part of the standard operating system distribution oranother vendor's commercial stack•Installs the MLNX_OFED_LINUX binary RPMs (if they are available for the current kernel)•Identifies the currently installed InfiniBand and Ethernet network adapters and automatically 1upgrades the firmwarePre-installation Notes•The installation script removes all previously installed Mellanox OFED packages and re-installsfrom scratch. You will be prompted to acknowledge the deletion of the old packages.Note Pre-existing configuration files will be saved with the extension “.conf.saverpm”.•If you need to install Mellanox OFED on an entire (homogeneous) cluster, a common strategy isto mount the ISO image on one of the cluster nodes and then copy it to a shared file system suchas NFS. To install on all the cluster nodes, use cluster-aware tools (such as pdsh).•If your kernel version does not match with any of the offered pre-built RPMs, you can add yourkernel version by using the “mlnx_add_kernel_support.sh ” script located under the docs/directory.Usage:mlnx_add_kernel_support.sh -i|--iso <mlnx iso>[-t|--tmpdir <local work dir>][-v|--verbose]1.The firmware will not be updated if you run the install script with the ‘--without-fw-update’ option.Mellanox OFED for Linux User’s Manual Rev 1.5.1 ExampleThe following command will create a MLNX_OFED_LINUX ISO image for RedHat 5.4 underthe/tmp directory.MLNX_OFED_LINUX-1.5.1-rhel5.4/docs/mlnx_add_kernel_support.sh -i/mnt/MLNX_OFED_LINUX-1.5.1-rhel5.4.isoAll Mellanox, OEM, OFED, or Distribution IB packages will be removed.Do you want to continue?[y/N]:yRemoving OFED RPMs...Running mkisofs...Created /tmp/MLNX_OFED_LINUX-1.5.1-rhel5.4.isoInstallation ScriptMellanox OFED includes an installation script called mlnxofedinstall. Its usage is describedbelow. You will use it during the installation procedure described in Section , “Installation Proce-dure,” on page 6.Usage./mlnxofedinstall [OPTIONS]Note If no options are provided to the script, then all available RPMs are installed.Options-c|--config <packages config_file>Example of the configuration file can be found under docs -n|--net <network config file>Example of the network configuration file can be foundunder docs-p|--print-available Print available packages for the current platform and cre-ate a corresponding ofed.conf file. The installation scriptexits after creating ofed.conf.--with-fc Install FCoE support — Available on RHEL5.2 ONLY--with-32bit Install 32-bit libraries (default). This is relevant forx86_64 and ppc64 platforms.--without-32bit Skip 32-bit libraries installation--without-ib-bonding Skip ib-bonding RPM installation--without-depcheck Skip Distro's libraries check--without-fw-update Skip firmware update--force-fw-update Force firmware update--force Force installation (without querying the user)--all Install all kernel modules, libibverbs, libibumad, librd-macm, mft, mstflint, diagnostic tools, OpenSM, ib-bonding,MVAPICH, Open MPI, MPI tests, MPI selector, perftest, sdp-netstat and libsdp srptools, rds-tools, static and dynamiclibrariesMellanox Technologies5Rev 1.5.1Mellanox Technologies6--hpc Install all kernel modules, libibverbs, libibumad, librd-macm, mft, mstflint, diagnostic tools, OpenSM , ib-bonding,MVAPICH, Open MPI, MPI tests, MPI selector, dynamic librar-ies--basic Install all kernel modules, libibverbs, libibumad, mft,mstflint, dynamic libraries--msmInstall all kernel modules, libibverbs, libibumad, mft,mstflint, diagnostic tools, OpenSM , ib-bonding, dynamiclibrariesNOTE: With --msm flag, the OpenSM daemon is configured torun upon boot.-v|-vv|-vvvSet verbosity level -q Set quiet - no messages will be printed mlnxofedinstall Return CodesTable 1 lists the mlnxofedinstall script return codes and their meanings.Installation ProcedureStep 1.Login to the installation machine as root.Step 2.Mount the ISO image on your machine host1# mount -o ro,loop MLNX_OFED_LINUX-<ver>-<OS label>.iso /mntNote After mounting the ISO image, /mnt will be a Read Only folder.Step 3.Run the installation scripthost1# /mnt/mlnxofedinstallThis program will install the MLNX_OFED_LINUX package on your machine.Note that all other Mellanox, OEM, OFED, or Distribution IB packages will be removed.Do you want to continue?[y/N]:yUninstalling the previous version of OFEDTable 1 - mlnxofedinstall Return CodesReturn CodeMeaning 0The Installation ended successfully 1The installation failed 2No firmware was found for the adapter device 3Failed to start the mst driverMellanox OFED for Linux User’s Manual Rev 1.5.1 Starting MLNX_OFED_LINUX-1.5.1-rc6 installation ...Installing kernel-ib RPMPreparing... ########################################### [100%]1:kernel-ib ########################################### [100%]Installing kernel-ib-devel RPMPreparing... ########################################### [100%]1:kernel-ib-devel ########################################### [100%]Installing mft RPMPreparing... ########################################### [100%]1:mft ########################################### [100%]Installing mpi-selector RPMPreparing... ########################################### [100%]1:mpi-selector ########################################### [100%]Install user level RPMs:Preparing... ########################################### [100%]1:libibumad ########################################### [100%]Preparing... ########################################### [100%]1:libibumad ########################################### [100%]Preparing... ########################################### [100%]1:libibmad ########################################### [100%]Preparing... ########################################### [100%]1:libibmad ########################################### [100%]Preparing... ########################################### [100%]1:libibumad-devel ########################################### [100%]Preparing... ########################################### [100%]1:libibumad-devel ########################################### [100%]Preparing... ########################################### [100%]1:libibmad-devel ########################################### [100%]Preparing... ########################################### [100%]1:libibmad-devel ########################################### [100%]Preparing... ########################################### [100%]1:ofed-scripts ########################################### [100%]Preparing... ########################################### [100%]1:libibverbs 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8xLink Speed: 2.5Gb/sInstallation finished successfully.Programming HCA firmware for /dev/mst/mt25418_pci_cr0 deviceRunning: mlxburn -d /dev/mst/mt25418_pci_cr0 -fw /tmp/MLNX_OFED_LINUX-1.5.1/MLNX_OFED_LINUX-1.5.1-sles11/firmware/fw-25408/2_7_000/fw-25408-rel.mlx -dev_type 25408 -no-I- Querying device ...-I- Using auto detected configuration file: /tmp/MLNX_OFED_LINUX-1.5.1/MLNX_OFED_LINUX-1.5.1-sles11/firmware/fw-25408/2_7_000/MHGH28-XTC_A4-A7.ini (PSID = MT_04A0140005)-I- Generating image ...Current FW version on flash: 2.6.0New FW version: 2.7.0Burning FW image without signatures - OKRestoring signature - OK-I- Image burn completed successfully.Please reboot your system for the changes to take effect.warning: /etc/infiniband/openib.conf saved as /etc/infiniband/openib.conf.rpmsaveNote In case your machine has the latest firmware, no firmware update will occur and the installation script will print at the end of installation a message similar to the following:...Installation finished successfully.The firmware version 2.7.000 is up to date.Note: To force firmware update use '--force-fw-update' flag.Note In case your machine has an unsupported network adapter device, no firmware update will occur and the error message below will be printed. Please contact your hardwarevendor for help on firmware updates.Error message:-I- Querying device ...-E- Can't auto detect fw configuration file: ...Step 4.In case the installation script performed firmware updates to your network adapter hard-ware, it will ask you to reboot your machine.Step 5.The script adds the following lines to /etc/security/limits.conf for the userspace components such as MPI:* soft memlock unlimited* hard memlock unlimitedThese settings unlimit the amount of memory that can be pinned by a user space application.If desired, tune the value unlimited to a specific amount of RAM.Step 6.For your machine to be part of the InfiniBand/VPI fabric, a Subnet Manager must be run-ning on one of the fabric nodes. At this point, Mellanox OFED for Linux has alreadyinstalled the OpenSM Subnet Manager on your machine. For details on starting OpenSM,see Chapter 12, “OpenSM – Subnet Manager”.Step 7.(InfiniBand only) Run the hca_self_test.ofed utility to verify whether or not the InfiniBand link is up. The utility also checks for and displays additional information suchas•HCA firmware version•Kernel architecture•Driver version•Number of active HCA ports along with their states•Node GUIDNote For more details on hca_self_test.ofed, see the file hca_self_test.readme under docs/.host1# /usr/bin/hca_self_test.ofed---- Performing InfiniBand HCA Self Test ----Number of HCAs Detected (1)PCI Device Check ....................... PASSKernel Arch ............................ x86_64Host Driver Version .................... MLNX_OFED_LINUX-1.5.1 (OFED-1.5.1-mlnx9) 1.5.1-2.6.9_89.ELlargesmpHost Driver RPM Check .................. PASSHCA Firmware on HCA #0 ................. 2.7.000HCA Firmware Check on HCA #0 ........... PASSHost Driver Initialization ............. PASSNumber of HCA Ports Active 0Port State of Port #0 on HCA #0 ........ INITPort State of Port #0 on HCA #0 ........ DOWNError Counter Check on HCA #0 .......... PASSKernel Syslog Check .................... PASSNode GUID on HCA #0 .................... 00:02:c9:03:00:00:10:e0------------------ DONE ---------------------Note After the installer completes, information about the Mellanox OFED installation such as prefix, kernel version, and installation parameters can be retrieved by running the com-mand /etc/infiniband/info.Installation ResultsSoftware•The OFED and MFT packages are installed under the /usr directory.•The kernel modules are installed under:-InfiniBand subsystem:/lib/modules/`uname -r`/updates/kernel/drivers/infiniband/-mlx4 driver:Under /lib/modules/`uname -r`/updates/kernel/drivers/net/mlx4you will find mlx4_core.ko, mlx4_en.ko, mlx4_ib.ko (and mlx4_fc ifyou ran the installation script with --with-fc)-RDS:/lib/modules/`uname -r`/updates/kernel/net/rds/rds.ko-Bonding module:/lib/modules/`uname -r`/updates/kernel/drivers/net/bonding/bonding.ko •The package kernel-ib-devel include files are placed under /usr/src/ofa_kernel/include/. These include files should be used when building kernel modules that use the stack. (Note that the include files, if needed, are “backported” to your kernel.)•The raw package (un-backported) source files are placed under/usr/src/ofa_kernel-<ver>•The script openibd is installed under /etc/init.d/. This script can be used to load and unload the software stack.•The script connectx_port_config is installed under /sbin. This script can be used to con-figure the ports of ConnectX network adapter cards to Ethernet and/or InfiniBand. For details on this script, please see Section 3.1, “Port Type Management”.•The directory /etc/infiniband is created with the files info and openib.conf and con-nectx.conf. The info script can be used to retrieve Mellanox OFED installation information. The openib.conf file contains the list of modules that are loaded when the openibd script is used. The connectx.conf file saves the ConnectX adapter card’s ports configuration to Ether-net and/or InfiniBand. This file is used at driver start/restart (/etc/init.d/openibd start) .•The file 90-ib.rules is installed under /etc/udev/rules.d/•If OpenSM is installed, the daemon opensmd is installed under /etc/init.d/ and opensm.conf is installed under /etc.•If IPoIB configuration files are included, ifcfg-ib<n> files will be installed under:-/etc/sysconfig/network-scripts/ on a RedHat machine-/etc/sysconfig/network/ on a SuSE machine•The installation process unlimits the amount of memory that can be pinned by a user space application. See Step 5.•Man pages will be installed under /usr/share/man/Firmware•The firmware of existing network adapter devices will be updated if the following two condi-tions are fullfilled:1. You run the installation script in default mode; that is, without the option‘--without-fw-update’.2. The firmware version of the adapter device is older than the firmware version includedwiththe Mellanox OFED ISO imageNote If an adapter’s Flash was originially programmed with an Expansion ROM image, the automatic firmware update will also burn an Expansion ROM image.•In case your machine has an unsupported network adapter device, no firmware update will occur and the error message below will be printed. Please contact your hardware vendor for help on firmware updates.Error message:。

从430FX到X58——大话INTEL主板芯片组发展历史2008-06-17 04:25:57 分类：intel英特尔| 业界| 评论(10) | 浏览(8055)- 序 -主板是电脑中最为重要的硬件之一。

CPU、内存、显卡等都基于其上，硬盘、光驱、电源等都与其连通，显示器、键盘、鼠标、音箱等都同其衔接。

主板连接并控制着其它硬件之间的数据传输，是其它硬件的中心枢纽。

而主板芯片组则是主板的心脏，决定着主板的功能和特性。

世界上存在多家拥有自主设计能力研发生产主板芯片组的公司，分别是Intel（英特尔）、NVIDIA（英伟达）、VIA（威盛）、SIS（矽统）、ALI（扬智）、AMD（2006年7月24日AMD收购了ATI）等。

这些厂商的历代多款主板芯片组，在性能、价格和CPU的支持上都各有特色，而Intel的主板芯片组，经过多年发展，久历市场考验，凭借着其在电脑使用人群中绝对优势的主板芯片组占有率，毫无悬念理所当然的成为众多主板芯片组厂商中的领军品牌。

电脑技术发展飞快，回望这些年Intel主板芯片组走过的历程，我们能够从历史的脚印中未来Intel主板芯片组发展的可能方向和规律。

那么，就让我们一起走进“时间隧道”，共同来回顾一下Intel主板芯片组发展的光辉历史。

- 前言 -Intel主板芯片组历史上，曾有440BX、810、815、845、865、915、945、965、P35等诸多型号的经典产品，以及最近在台北Computex2008电脑展上刚刚发布的P45，还有Intel未来将要发布的搭配下一代Nehalem处理器的X58，让我们看的眼花缭乱晕乎其晕。

主板芯片组分为北桥芯片和南桥芯片（NVIDIA有部分IGP整合主板产品将北桥主板对和南桥主板对集成到一个主板芯片中）。

本文所讲的主要是主板的北桥芯片，它通常靠近CPU插槽一端，负责主板对CPU、内存、显卡等硬件的控制，我们平时所说的“845”主板就是指的使用845北桥芯片的主板。

本文介绍近期工程用到了CPCI，便上网搜集了一下PCI的资料，CPCI是PCI的子集，所用桥接芯片分主从两种，在此不赘述了。

至于PCI，本人整理介绍如下：随着Windows图形用户界面的迅速发展，以及多媒体技术的广泛应用，要求系统具有高速图形处理和I/O吞吐能力，这使原有的ISA、EISA总线远远不能适应而成为整个系统的主要瓶颈。

为此，1991年下半年，Intel公司首先提出PCI概念，并联合IBM、Compaq、AST、HP Apple、NCR、DEC 等100多家公司共谋计算机总线发展大业，成立了PCI集团。

PCI：Peripheral Component Interconnect，外围设备互联总线，是一种局部总线，已成为局部总线的新标准，广泛用于当前高档微机、工作站，以及便携式微机。

主要用于连接显示卡、网卡、声卡。

PCI总线是32位同步复用总线。

其地址和数据线引脚是AD31～AD0。

PCI的工作频率为33MHz。

一PCI总线特性1.PCI总线特点(1)传输速率高最大数据传输率为132MB/s，当数据宽度升级到64位，数据传输率可达264MB/s。

这是其他总线难以比拟的。

它大大缓解了数据I/O瓶颈，使高性能CPU的功能得以充分发挥，适应高速设备数据传输的需要。

(2)多总线共存采用PCI总线可在一个系统中让多种总线共存，容纳不同速度的设备一起工作。

通过HOST-PCI桥接组件芯片，使CPU总线和PCI总线桥接；通过PCI-ISA/EISA 桥接组件芯片，将PCI总线与ISA/EISA总线桥接，构成一个分层次的多总线系统。

高速设备从ISA/EISA总线卸下来，移到PCI总线上，低速设备仍可挂在ISA/EISA总线上，继承原有资源，扩大了系统的兼容性。

(3)独立于CPU PCI总线不依附于某一具体处理器，即PCI总线支持多种处理器及将来发展的新处理器，在更改处理器品种时，更换相应的桥接组件即可。

(4)自动识别与配置外设用户使用方便。

PCIE检测卡代码PCIEPCIE主板测试卡测试卡无中文显示，可参照以下代码。

一般来说：FF、00、C0、DO、CF、F1或什么也没有表示CPU没通过C1、C6、C3、D3、D4、D6、D8、BO、A7、E1 表示内存不过24、25、26、01、0A、OB、2A、2B、31 表示显卡不过某些集成显卡主板23、24、25表示可以正常点亮，某些VIA芯片组显示13则表示可以点亮，某些品牌机里的主板显示0B则表示正常，某些主板显示4E表示正常点亮，某些INTEL 芯片组的主板显示26或16则表示可以正常点亮。

C1、C6、C3、01、02这个组合循环跳变大部分是I/O坏或刷BIOS如显示05、ED、41则直接刷BIOS 00 .已显示系统的配置；即将控制INI19引导装入。

? 01处理器测试1，处理器状态核实，如果测试失败，循环是无限的。

处理器寄存器的测试即将开始，不可屏蔽中断即将停用。

CPU寄存器测试正在进行或者失败。

02确定诊断的类型（正常或者制造）。

如果键盘缓冲器含有数据就会失效。

停用不可屏蔽中断；通过延迟开始。

CMOS写入/读出正在进行或者失灵。

03清除8042键盘控制器，发出TESTKBRD 命令（AAH ）通电延迟已完成。

ROM BIOS 检查部件正在进行或失灵。

04使8042键盘控制器复位，核实TESTKBRD。

键盘控制器软复位/通电测试。

可编程间隔计时器的测试正在进行或失灵。

05如果不断重复制造测试1至5，可获得8042控制状态。

已确定软复位/通电；即将启动ROM。

DMA初如准备正在进行或者失灵。

06使电路片作初始准备，停用视频、奇偶性、DMA电路片，以及清除DMA电路片，所有页面寄存器和CMOS停机字节。

已启动ROM计算ROM BIOS检查总和，以及检查键盘缓冲器是否清除。

DMA初始页面寄存器读/写测试正在进行或失灵。

07处理器测试2，核实CPU寄存器的工作。

ROM BIOS检查总和正常，键盘缓冲器已清除，向键盘发出BAT （基本保证测试）命令。

目前的主流主板都板载了磁盘阵列控制芯片大家可以组成磁盘阵列来提高系统性能。

这里特指RAID 0 模式也是最常用最方便且容易而提高磁盘性能的方式目前市面上最多的大概采用4种磁盘控制芯片。

1： INTEL的 ICH X R 南桥芯片。

例如 ICH8R ICH9R 等。

P35主板现在就有黑潮BI100 使用 P35北桥+ICH7南桥微星 P35NEO2-FR 使用 P35北桥+ICH9R南桥。

还有一些主板用的P35+ICH9. 区分方式为南桥芯片代号是否带R 如果有R 那么是支持原生磁盘阵列的。

2：NV的芯片组。

比如 NF570 590等。

他们也支持原生磁盘阵列。

是NV自己的控制芯片。

3：第三方控制芯片例如 JMB36X 。

这种方式一般出现在不带原生阵列的主板芯片上。

比如现在N多的P35主板使用 P35+ICH9 。

ICH9就没有阵列但是为了实现这一功能厂家往往在板子上加入一个JMBXX磁盘控制芯片来提供磁盘阵列。

4：ATI的芯片组例如捷波悍马HA02-GT 使用的是ATI的芯片组 RD570X北桥+SB600南桥 SB600南桥支持磁盘阵列对于RAID0的性能。

磁盘控制芯片的影响是非常非常明显的。

目前来说性能最好的磁盘阵列是 INTEL的ICHXR南桥提供的阵列系统。

性能的提升几乎是100%的。

希捷单碟250G硬盘。

最高速度一般在95-105左右具体要看固件版本在ICH9R上组成阵列0 打开卷回写后性能几乎可以提升90%左右。

2块3250310RAID0后最高速度能达到接近200M/S 企业级盘甚至超过200M/S。

非常恐怖。

其次是 NV的芯片组提供的阵列系统。

大概能提升50-60%左右的性能。

2块3250310RAID0 最高速度大概在 150-160左右。

再次是 ATI 南桥大概能提升 30-40% 2块3250310RAID0最高速度大概是 130-145最差的算是 JMBXXX系列他们基于PCI总线。