UC2824中文资料

串行EEPROM AT24CXX芯片资料AT24CXX是美国ATMEL公司的低功耗CMOS串行EEPROM，典型的型号有AT24C01A/02/04/08/16等5种，它们的存储容量分别是1024/2048/4096/8192/16384位；也就是128/256/512/1024/2048字节；使用电压级别有5V，2.7V,2.5V,1.8V;本文主要介绍常用的AT24C02即256字节存储器的使用；它具有工作电压宽（2.5～5.5V）、擦写次数多（大于10000次）、写入速度快（小于10ms）等特点。

外行如图：AT24C02的1、2、3脚是三条地址线，用于确定芯片的硬件地址（实验板中直接接地只有一块器件）；第8脚和第4脚分别为正、负电源。

第5脚SDA为串行数据输入/输出，数据通过这条双向I2C总线串行传送，SDA和SCL 都需要和正电源间各接一个5.1K的电阻上拉。

第7脚为WP写保护端，接地时允许芯片执行一般的读写操作。

接电源端时不允许对器件写。

24C02中带有片内地址寄存器。

每写入或读出一个数据字节后，该地址寄存器自动加1，以实现对下一个存储单元的读写。

所有字节均以单一操作方式读取。

为降低总的写入时间，一次操作可写入多达8个字节的数据。

;这是将0100H地址中以下的8个数据写到24C02的01H为首址单元中去的汇编程序可直接在实验板上实验。

ORG 0000HSCL BIT P3.7;定义24C02的串行时钟线SDA BIT P3.6;定义24C02的串行数据线LJMP STARTSTART:LCALL STAR;调用MOV R2,#08H;一个数据有8位MOV DPTR,#0100H;定义源数据的位置LOOP:MOV A,#00HMOVC A,@A+DPTRLCALL SDATALCALL ACKJC LOOPINC DPTRDJNZ R2,LOOPLCALL STOP;调用停止子程序STAR:SETB SDASETB SCLNOPNOPNOPNOPCLR SDANOPNOPNOPNOPCLR SCLRETSDATA:MOV R0,#08HLOOP0:RLC AMOV SDA,CNOPNOPSETB SCLNOPNOPNOPCLR SCLDJNZ R0,LOOP0 RETACK:SETB SDA NOPNOPSETB SCL NOPNOPNOPNOPMOV C,SDA CLR SCLRETSTOP:CLR SDA NOPNOPNOPNOPSETB SCL NOPNOPNOPNOPSETB SDANOPNOPNOPRETORG 0100HDB 0A0H,10H,01H,02H,03H,04H,05H,06HEND读写子程序如下：;写串行E2PROM子程序XEPR; R3=10100000（命令1010+器件3位地址+读/写。

MN187165T7M MN187165T6S
松下MX-4A
松下
TC-25GF88GS TC-25GF86RS TC-29GF86R TC-29GF88G
MN187265T9X
松下MX-6
松下
TC-29F99G
音飞
2199
机芯
品牌
机型
CPU型号
松下M16M
松下
TX-32V1M TX-TX-33V1X TX-33V1EE TC-32V2H TC-33V2H TC-33V2X TC-33V2PX TC-33V2L TX-29V1M TX-29V1Z TX-29V1X TX-29V1R TX-29V1EE TX-29V2H TX-29V2HA TX-29V2X TX-29V2PX TX-29V2L TX-26V2X TX-26V2HA TX-26V2X TX-26V2E TX-26T1M TX-26T1Z TX-26T1EE TX-26L1EE TX-26L1R TX-26L1RA
M37222M6-C84SP
S5S
东芝
2155DE 2155DH 2155D 2155SH 2155XC 2155XMJ
S6ES
东芝
2560XHC 2560 2960
M37222M6-D86
S6SS
东芝
2989XP
TMP87CS38N-3446
S7E
东芝
1470XNC 2170XNC
TMP87CK38N-3505
MN1874862T5B
E1W
松下
TC-47WG25G宽屏幕投影电视机
MN1876476T4N
东芝F2DB F3SS F3SSR F91DB S3ES
机芯

UC2842/3/4/5UC3842/3/4/5 Current Mode PWM ControllerFEATURES•Optimized For Off-line And DC To DC Converters•Low Start Up Current (<1mA)•Automatic Feed ForwardCompensation•Pulse-by-pulse Current Limiting •Enhanced Load ResponseCharacteristics•Under-voltage Lockout With Hysteresis•Double Pulse Suppression •High Current Totem PoleOutput•Internally Trimmed Bandgap Reference•500khz Operation•Low R O Error Amp DESCRIPTIONThe UC1842/3/4/5 family of control ICs provides the necessary features to im-plement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include un-der-voltage lockout featuring start up current less than 1mA, a precision refer-ence trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The out-put stage, suitable for driving N Channel MOSFET s, is low in the off state. Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applica-tions. The corresponding thresholds for the UC1843 and UC1845 are 8.4V and 7.6V. The UC1842 and UC1843 can operate to duty cycles approaching 100%. A range of zero to 50% is obtained by the UC1844 and UC1845 by the addition of an internal toggle flip flop which blanks the output off every otherclock cycle. BLOCK DIAGRAMA/BNote 1: A = DIL-8 Pin Number. B = SO-14 Pin Number. Note 2:Toggle flip flop used only in 1844 and 1845.4/97ABSOLUTE MAXIMUM RATINGS (Note 1)Supply Voltage (Low Impedance Source). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V Supply Voltage (I CC <30mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Self Limiting Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1A Output Energy (Capacitive Load). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5µJ Analog Inputs (Pins 2, 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.3V Error Amp Output Sink Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Power Dissipation at T A ≤ 25°C (DIL-8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Power Dissipation at T A≤ 25°C (SOIC-14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725mW Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (Soldering, 10 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C Note 1:All voltages are with respect to Pin 5.All currents are positive into the specified terminal.Consult Packaging Section of Databook for thermal limitations and considerations of packages.CONNECTION DIAGRAMSDIL-8, SOIC-8 (TOP VIEW)N or J Package, D8 Package PLCC-20 (TOP VIEW) Q PackageSOIC-14 (TOP VIEW) D PackagePACKAGE PIN FUNCTIONFUNCTION PIN N/C1 COMP2 N/C3 N/C4 V FB5 N/C6 I SENSE7 N/C8 N/C9 R T/C T10 N/C11 PWR GND12 GROUND13 N/C14 OUTPUT15 N/C16 V C17 V CC18 N/C19 V REF20PARAMETERTEST CONDITIONSUC1842/3/4/5UC2842/3/4/5UC3842/3/4/5UNITSMINTYPMAXMINTYPMAXReference Section Output Voltage T J = 25°C, I O = 1mA 4.955.00 5.05 4.905.00 5.10V Line Regulation 12 ≤ V IN ≤ 25V 620620mV Load Regulation 1 ≤ I 0 ≤ 20mA625625mV Temp. Stability (Note 2) (Note 7)0.20.40.20.4mV/°C Total Output Variation Line, Load, Temp. (Note 2)4.95.14.825.18V Output Noise Voltage 10Hz ≤ f ≤ 10kHz, T J = 25°C (Note2)5050µV Long Term Stability T A = 125°C, 1000Hrs. (Note 2)525525mV Output Short Circuit -30-100-180-30-100-180mAOscillator Section Initial Accuracy T J = 25°C (Note 6)475257475257kHz Voltage Stability 12 ≤ V CC ≤ 25V0.210.21%Temp. Stability T MIN ≤ T A ≤ T MAX (Note 2)55%Amplitude V PIN 4 peak to peak (Note 2)1.71.7VError Amp Section Input Voltage V PIN 1 = 2.5V2.452.50 2.55 2.422.50 2.58V Input Bias Current -0.3-1-0.3-2µA A VOL2 ≤ V O ≤ 4V 65906590dB Unity Gain Bandwidth (Note 2) T J = 25°C 0.710.71MHz PSRR12 ≤ V CC ≤ 25V60706070dB Output Sink Current V PIN 2 = 2.7V, V PIN 1 = 1.1V 2626mA Output Source Current V PIN 2 = 2.3V, V PIN 1 = 5V -0.5-0.8-0.5-0.8mA V OUT High V PIN 2 = 2.3V, R L = 15k to ground 5656V V OUT LowV PIN 2 = 2.7V, R L = 15k to Pin 80.71.10.71.1VCurrent Sense Section Gain(Notes 3 and 4) 2.853 3.15 2.853 3.15V/V Maximum Input Signal V PIN 1 = 5V (Note 3)0.91 1.10.91 1.1V PSRR12 ≤ V CC ≤ 25V (Note 3) (Note 2)7070dB Input Bias Current -2-10-2-10µA Delay to OutputV PIN 3 = 0 to 2V (Note 2)150300150300nsELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for -55°C ≤ T A ≤ 125°C for theUC184X; -40°C ≤ T A ≤ 85°C for the UC284X; 0°C ≤ T A ≤ 70°C for the 384X; V CC =15V (Note 5); R T = 10k; C T =3.3nF, T A =T J.Note 2:These parameters, although guaranteed, are not 100% tested in production.Note 3:Parameter measured at trip point of latch with V PIN 2 = 0.Note 4:Gain defined asA = ∆ V PIN 1∆ V PIN 3, 0 ≤ V PIN 3 ≤ 0.8VNote 5:Adjust V CC above the start threshold before setting at 15V.Note 6:Output frequency equals oscillator frequency for the UC1842 and UC1843.Output frequency is one half oscillator frequency for the UC1844 and UC1845.Note 7:Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:Temp Stability =V REF (max ) − V REF (min )T J (max ) − T J (min )V REF (max) and V REF (min) are the maximum and minimum reference voltages measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.PARAMETER TEST CONDITIONUC1842/3/4/5UC2842/3/4/5UC3842/3/4/5UNITSMINTYPMAXMINTYPMAXOutput Section Output Low Level I SINK = 20mA 0.10.40.10.4V I SINK = 200mA 1.5 2.21.52.2V Output High Level I SOURCE = 20mA 1313.51313.5V I SOURCE = 200mA1213.51213.5V Rise Time T J = 25°C, C L = 1nF (Note 2)5015050150ns Fall TimeT J = 25°C, C L = 1nF (Note 2)5015050150nsUnder-voltage Lockout Section Start Threshold X842/415161714.51617.5V X843/57.88.49.07.88.49.0V Min. Operating Voltage After Turn On X842/4910118.51011.5V X843/57.07.68.27.07.68.2VPWM SectionMaximum Duty Cycle X842/395971009597100%X844/5464850474850%Minimum Duty Cycle 0%Total Standby Current Start-Up Current 0.510.51mA Operating Supply CurrentV PIN 2 = V PIN 3 = 0V11171117mA V CC Zener VoltageI CC = 25mA 30343034VNote 2:These parameters, although guaranteed, are not 100% tested in production.Note 3:Parameter measured at trip point of latch with V PIN 2 = 0.Note 4:Gain defined as:A = ∆ V PIN 1∆ V PIN 3; 0 ≤ V PIN 3 ≤ 0.8V.Note 5:Adjust V CC above the start threshold before setting at 15V.Note 6:Output frequency equals oscillator frequency for the UC1842 and UC1843.Output frequency is one half oscillator frequency for the UC1844 and UC1845.ELECTRICAL CHARACTERISTICS:Unless otherwise stated, these specifications apply for −55°C ≤ T A ≤ 125°C for theUC184X; −40°C ≤ T A ≤ 85°C for the UC284X; 0°C ≤ T A ≤ 70°C for the 384X; V CC =15V (Note 5); R T = 10k; C T =3.3nF, T A =T J.ERROR AMP CONFIGURATIONError Amp can Source or Sink up to 0.5mAUNDER-VOLTAGE LOCKOUTCURRENT SENSE CIRCUITOSCILLATOR SECTIONDuring under-voltage lock-out, the output driver is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage currents.A small RC filter may be required to suppress switch transients .Peak Current (I S ) is Determined By The FormulaI SMAX ≈1.0VR SHigh peak currents associated with capacitive loads necessi-tate careful grounding techniques. Timing and bypass capaci-tors should be connected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sam-ple the oscillator waveform and apply an adjustable ramp to pin 3.Shutdown of the UC1842 can be accomplished by two meth-ods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the out-put of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling V CC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset.OUTPUT SATURATION CHARACTERISTICS ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSEOPEN-LOOP LABORATORY FIXTURE SHUT DOWN TECHNIQUESUNITRODE CORPORATION7 CONTINENTAL BLVD. • MERRIMACK, NH 03054TEL. (603) 424-2410 • FAX (603) 424-3460OFFLINE FLYBACK REGULATORSLOPE COMPENSATIONA fraction of the oscillator ramp can be resistivelysummed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%.Note that capacitor, C forms a filter with R2 to suppress the leading edge switch spikes.Power Supply Specifications1. Input Voltage95VAC to 130VA (50 Hz/60Hz)2. Line Isolation3750V 3. Switching Frequency 40kHz 4. Efficiency @ Full Load70%5. Output Voltage:A. +5V, ±5%; 1A to 4A load Ripple voltage: 50mV P-P MaxB. +12V, ±3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P MaxC. -12V ,±3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P MaxIMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1999, Texas Instruments Incorporated。

UC2724 UC3724FEATURES•500mA Output Drive, Source or Sink •8 to 35V Operation•Transmits Logic Signal Instantly •Programmable Operating Frequency •Under-Voltage Lockout•Able To Pass DC Information Across Transformer•Up To 600kHz Operation DESCRIPTIONThe UC1724family of Isolated Drive Transmitters,along with the UC1725 Isolated Drivers,provide a unique solution to driving isolated power MOSFET gates.They are particularly suited to drive the high-side devices on a high-voltage H-bridge.The UC1724devices transmit drive logic,and drive power, to the isolated gate circuit using a low cost pulse transformer.This drive system utilizes a duty-cycle modulation technique that gives in-stantaneous response to the drive control transistions,and reliably passes steady-state,or DC,conditions.High frequency operation,up to600kHz, allows the cost and size of the coupling transformer to be minimized.These devices will operate over an8to35Volt supply range.The dual high current totem pole outputs are disabled by an uder-voltage lockout circuit to prevent spurious responses during startup or low voltage conditions.These devices are available in8pin plastic or ceramic dual-inline pack-ages, as well as 16 pin SOIC package.Isolated Drive TransmitterBLOCK DIAGRAMUDG-92037 Note:Pin numbers refer to DIL-8 packages.CONNECTION DIAGRAMSELECTRICAL CHARACTERISTICS:Unless otherwise stated, V CC = 20V, R T = 4.3k Ω, C T = 1000pF, no load on anyoutput and these specifications apply for: –55o C < T A < 125o C for the UC1724, –25o C < T A < 85o C for the UC2724, and 0o C < T A < 70o C for the UC3724. T A =T J .PARAMETERTEST CONDITIONSMINTYPMAX UNITS Under-Voltage Lockout Start-Up Threshold V IN Rising7.759.5V Threshold Hysteresis 0.41.01.5V Retriggerable One-Shot Initial Accuracy T J = 25°C 1.54 1.92.25µs Temperature Stability Over Operating T J 1.02.9µs Voltage Stability V IN = 10 to 35V 0.20.5%/V Operating Frequency L LOAD = 1.4mH 100150200kHz Minimum Pulse Width RT = 2k CT = 300pF1005001200ns Operating FrequencyRT = 2k C T = 300pF L LOAD = 1.4mH5007501100kHzABSOLUTE MAXIMUM RATINGSSupply Voltage V IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40V Source/Sink Current (Pulsed). . . . . . . . . . . . . . . . . . . . . . . .1A Source/Sink Current (Continuous). . . . . . . . . . . . . . . . . . .0.5A Ouput Voltage (Pins 4, 6). . . . . . . . . . . . . . .–0.3 to (V IN +0.3)V P HI , R T , and C T inputs (Pins 1, 7, and 8). . . . . . . . .–0.3 to 6V Operating Junction Temperature (Note 2). . . . . . . . . . . .150°C Storage Temperature Range . . . . . . . . . . . . . .–65°C to 150°C Lead Temperature (Soldering, 10 Seconds). . . . . . . . . .300°C Note 1:All voltages are with respect to GND (Pin 2);all cur-rents are positive into, negative out of part.Note 2:Consult Unitrode Integrated Circuit Databook for ther-mal limitations and considerations of package.Note 3:Pin numbers refer to DIL-8 packages.RECOMMENDED OPERATION CONDITIONSInput Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+9V to +35V Sink/Source Load Current (each output). . . . . . . . .0 to 500mA Timing Resistor. . . . . . . . . . . . . . . . . . . . . . . . . . .2kW to 10kW Timing Capacitor . . . . . . . . . . . . . . . . . . . . . . . . .300pF to 3nF Operating Temperature Range (UC1724). . .–55°C<T A <125°C Operating Temperature Range (UC3724). . . . . .0°C<T A <70°C Note 4:Range over which the device is functional andparameter limits are guaranteed.TEMPERATURE RANGE PACKAGE UC1724J –55°C to +125°C CDIPUC2724DW –25°C to +85°C SOIC-Wide UC2724N PDIPUC3724DW 0°C to +70°CSOIC-Wide UC3724NPDIPORDERING INFORMATIONELECTRICAL CHARACTERISTICS:Unless otherwise stated, V CC = 20V, R T = 4.3k Ω, C T = 1000pF, no load on anyoutput and these specifications apply for: –55o C < T A < 125o C for the UC1724, –25o C < T A < 85o C for the UC2724, and 0o C < T A < 70o C for the UC3724. T A =T J .PARAMETERTEST CONDITIONSMINTYPMAX UNITSPhi Input (Control Input)HIGH Input Voltage 2.0V LOW Input Voltage 0.8V HIGH Input Current V IH =+2.4V –220–130µA LOW Input Current V IL =+0.4V–600–300µA Delay to One-Shot 350ns Delay to Output 250nsOutput Drivers Output Low LevelI SINK = 50mA 0.30.4V I SINK = 250mA 0.5 2.1V Output High Level (Volts Below V CC )I SOURCE = 50 mA 1.5 2.1V I SOURCE = 250 mA 1.7 2.5V Rise/Fall Time No load3090nsTotal Supply Current Supply CurrentC T = 1.4V1530mAUNITRODE CORPORA TION7 CONTINENTAL BLVD.• MERRIMACK, NH 03054TEL.(603) 424-2410FAX (603) 424-3460Additional InformationPlease refer to the following Unitrode application topics.[1]Application Note U-127,Unique Chip Pair Simplified Isolated High-Side Switch Drive by John A.O’Connor.[2]Design Note DN-35,IGBT Drive Using MOSFET Gate Drivers by John A.O’Conner.IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1999, Texas Instruments Incorporated。