FPGA可编程逻辑器件芯片XC7A200T-1FBG676I中文规格书

Chapter2 Zynq-7000SoC Package FilesAbout ASCII Package FilesThe ASCII files for each package include a comma-separated-values (CSV) version and a text version optimized for a browser or text editor. Each of the files consists of the following:•Device/Package name (Device—Package), date and time of creation•Eight columns containing data for each pin:°Pin—Pin location on the package.°Pin Name—The name of the assigned pin.°Memory Byte Group—Memory byte group between 0 and 3. For more information on the memory byte group, see the 7Series FPGAs Memory Interface Solutions UserGuide (UG586) [Ref7].°Bank—Bank number.°V CCAUX Group—Number corresponding to the V CCAUX_IO power supply for the given pin. V CCAUX is shown for packages with only one V CCAUX group.°Super Logic Region—Number corresponding to the super logic region (SLR) in the devices implemented with stacked silicon interconnect (SSI) technology.°I/O Type—CONFIG, HR, HP, MIO, DDR, or GTP/GTX depending on the I/O type. For more information on the I/O type, see the 7Series FPGAs SelectIO Resources UserGuide (UG471) [Ref8].°No-Connect—This list of devices is used for migration between devices that have the same package size and are not connected at that specific pin.•Total number of pins in the package.Pin Compatibility Between PackagesZynq-7000SoC devices are pin compatible only with other Zynq-7000SoC devices in the same package. In addition, FB/FBG/FBV and FF/FFG/FFV packages of the same pin-count designator are pin compatible. Table1-6 shows the pin compatible devices available for each Zynq-7000SoC device package. Pins that are available in one device but are notavailable in another device with a compatible package include the other device's name in the No Connect column of the package file. These pins are labeled as No Connects in the other device's package file.Some FB/FBG/FBV packages include V CCAUX_IO pins, but they are not utilized by the I/O.These pins are placeholders to ensure pin compatibility with FF/FFG/FFV packages. In the FF/FFG/FFV packages, if the high-performance option is chosen for the HP I/O, theV CCAUX_IO pins must be connected to a power supply separate from V CCAUX. Therefore, if there are plans to migrate to FF/FFG/FFV packages, V CCAUX_IO must be connected to the appropriate voltage regulator.Table 1-6:Pin CompatibilityPackage Pin Compatible DevicesCL225/CLG2257Z007S7Z010CL400/CLG4007Z007S7Z0107Z014S7Z020CL484/CLG4847Z014S7Z020SB/SBG/SBV485 or7Z012S7Z0157Z030CL/CLG485FB/FBG/FBV484 or RB4847Z030FB/FBG/FBV676 or7Z0307Z0357Z045FF/FFG/FFV676 or RF/RFG676FF/FFG/FFV900 or RF9007Z0357Z0457Z100FF/FFG/FFV1156 or RF11567Z100Notes:1.Pin compatible packages as well as the FB/FBG/FBV and FF/FFG/FFV packages have substantially different decouplingcapacitor recommendations. Refer to the Zynq-7000 SoC PCB Design Guide (UG933) [Ref2].Chapter 2:Zynq-7000SoC Package FilesDevice DiagramsChapter3SummaryThis chapter provides pinout, high-performance and high-range I/O bank, memorygroupings, and power and ground placement diagrams for each Zynq-7000SoCpackage/device combination.The figures provide a top-view perspective.The symbols for the multi-function I/O pins are represented by only one of the available pin functions; with precedence (by functionality) in this order:•PUDC_B•AD0P/AD0N–AD15P/AD15N•VRN, VRP, or VREF•DQS, MRCC, or SRCC。

Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching CharacteristicsDS191 (v1.18.1) July 2, 2018Product Specification AC Switching CharacteristicsAll values represented in this data sheet are based on the speed specifications in the ISE® Design Suite 14.7 and Vivado®Design Suite 2015.4 as outlined in Table 16.Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or Production. Each designation is defined as follows:Advance Product SpecificationThese specifications are based on simulations only and are typically available soon after device design specifications are frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-reporting might still occur.Preliminary Product SpecificationThese specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. The probability of under-reporting delays is greatly reduced as compared to Advance data.Production Product SpecificationThese specifications are released once enough production silicon of a particular device family member has beencharacterized to provide full correlation between specifications and devices over numerous production lots. There is no under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest speed grades transition to Production before faster speed grades.Testing of AC Switching CharacteristicsInternal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are representative of worst-case supply voltage and junction temperature conditions.For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. Unless otherwise noted, values apply to all Zynq-7000 devices.Speed Grade DesignationsSince individual family members are produced at different times, the migration from one category to another dependscompletely on the status of the fabrication process for each device. Table 17 correlates the current status of each Zynq-7000 device on a per speed grade basis.Table 16:Zynq-7000SoC Speed Specification Version By Device ISE 14.7Vivado 2015.4Device 1.081.11XC7Z030 and XC7Z045N/A1.11XC7Z035 and XC7Z100N/A 1.09XA7Z0301.061.10XQ7Z030 and XQ7Z045N/A 1.10XQ7Z100Table 17:Zynq-7000 Device Speed Grade DesignationsDeviceSpeed Grade Designations Advance Preliminary Production XC7Z030-3, -2, -2LI, -1XC7Z035-3, -2, -2LI, -1XC7Z045-3, -2, -2LI, -1XC7Z100-2, -2LI, -1XA7Z030-1I, -1QZynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching CharacteristicsDS191 (v1.18.1) July 2, 2018Product SpecificationProduction Silicon and Software StatusIn some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent speed specification releases.Table 18 lists the production released Zynq-7000 device, speed grade, and the minimum corresponding supported speed specification version and software revisions. The software and speed specifications listed are the minimum releases required for production. All subsequent releases of software and speed specifications are valid.Selecting the Correct Speed Grade and Voltage in the Vivado ToolsIt is important to select the correct device speed grade and voltage in the Vivado tools for the device that you are selecting.To select the -3, -2, or -1 (PL 1.0V) speed specifications in the Vivado tools, select the Zynq-7000, XA Zynq-7000, or Defense Grade Zynq-7000 sub-family, and then select the part name that is the device name followed by the package name followed by the speed grade. For example, select the xc7z030fbg676-3 part name for the XC7Z030 device in the FBG676 package and -3 speed grade.To select the -2LI (PL 0.95V) speed specifications in the Vivado tools, select the Zynq-7000 sub-family and then select the part name that is the device name followed by an i followed by the package name followed by the speed grade. For example, select the xc7z030ifbg676-2L part name for the XC7Z030 device in the FBG676 package and -2LI (PL 0.95V) speed grade. The -2LI (PL 0.95V) speed specifications are not supported in the ISE tools.A similar part naming convention applies to the speed specifications selection in the ISE tools for supported devices. See Table 18 for the subset of Zynq-7000 devices supported in the ISE tools.XQ7Z030-2I, -2LI, -1I, -1Q XQ7Z045-2I, -2LI, -1I, -1Q, -1LQ XQ7Z100-2I, -2LI, -1ITable 18:Zynq-7000 Device Production Software and Speed Specification Release DeviceSpeed Grade Designations -3E -2E -2I -2LI -1C -1I -1Q -1LQ XC7Z030ISE tools 14.5 v1.06 and Vivado tools 2013.1 v1.06Vivado tools 2014.4 v1.11ISE tools 14.5 v1.06 and Vivado tools 2013.1 v1.06N/A N/A XC7Z035Vivado tools 2014.4 v1.11N/A N/A XC7Z045ISE tools 14.5 v1.06 and Vivado tools 2013.1 v1.06Vivado tools 2014.4 v1.11ISE tools 14.5 v1.06 and Vivado tools 2013.1 v1.06N/A N/A XC7Z100N/A N/A Vivado tools 2013.2 v1.07Vivado tools 2014.4 v1.11N/A Vivado tools 2013.2 v1.07N/A N/A XA7Z030N/A N/A N/A N/A N/A Vivado tools 2014.2 v1.08N/A XQ7Z030N/A N/A ISE tools 14.7 v1.06 and Vivado tools 2013.3 v1.06Vivado tools 2015.4 v1.10N/A ISE tools 14.7 v1.06 and Vivado tools 2013.3 v1.06N/A XQ7Z045N/A N/A N/A Vivado tools 2015.2 v1.09XQ7Z100N/A N/A Vivado tools 2015.4 v1.10N/A Vivado tools2015.2 v1.09N/AN/A Table 17:Zynq-7000 Device Speed Grade Designations (Cont’d)DeviceSpeed Grade Designations Advance Preliminary Production。

General DescriptionXilinx® 7series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor, cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding high-performance applications. The 7series FPGAs include:•Spartan®-7 Family: Optimized for low cost, lowest power, and high I/O performance. Available in low-cost, very small form-factorpackaging for smallest PCB footprint.•Artix®-7 Family: Optimized for low power applications requiring serial transceivers and high DSP and logic throughput. Provides the lowest total bill of materials cost for high-throughput, cost-sensitiveapplications.•Kintex®-7 Family: Optimized for best price-performance with a 2X improvement compared to previous generation, enabling a new class of FPGAs.•Virtex®-7 Family: Optimized for highest system performance and capacity with a 2X improvement in system performance. Highestcapability devices enabled by stacked silicon interconnect (SSI)technology.Built on a state-of-the-art, high-performance, low-power (HPL), 28nm, high-k metal gate (HKMG) process technology, 7series FPGAs enable an unparalleled increase in system performance with 2.9Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3TMAC/s DSP, while consuming 50% less power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.Summary of 7Series FPGA Features•Advanced high-performance FPGA logic based on real 6-input look-up table (LUT) technology configurable as distributed memory.•36Kb dual-port block RAM with built-in FIFO logic for on-chip data buffering.•High-performance SelectIO™ technology with support for DDR3 interfaces up to 1,866 Mb/s.•High-speed serial connectivity with built-in multi-gigabit transceivers from 600Mb/s to max. rates of 6.6Gb/s up to 28.05Gb/s, offering a special low-power mode, optimized for chip-to-chip interfaces.• A user configurable analog interface (XADC), incorporating dual 12-bit 1MSPS analog-to-digital converters with on-chip thermal and supply sensors.•DSP slices with 25x18 multiplier, 48-bit accumulator, and pre-adder for high-performance filtering, including optimized symmetriccoefficient filtering.•Powerful clock management tiles (CMT), combining phase-locked loop (PLL) and mixed-mode clock manager (MMCM) blocks for high precision and low jitter.•Quickly deploy embedded processing with MicroBlaze™ processor.•Integrated block for PCI Express® (PCIe), for up to x8 Gen3 Endpoint and Root Port designs.•Wide variety of configuration options, including support for commodity memories, 256-bit AES encryption with HMAC/SHA-256 authentication, and built-in SEU detection and correction.•Low-cost, wire-bond, bare-die flip-chip, and high signal integrity flip-chip packaging offering easy migration between family members in the same package. All packages available in Pb-free and selected packages in Pb option.•Designed for high performance and lowest power with 28nm, HKMG, HPL process, 1.0V core voltage process technology and0.9V core voltage option for even lower power.7Series FPGAs Data Sheet: Overview DS180 (v2.6) February 27, 2018Product SpecificationTable 1:7Series Families ComparisonMax. Capability Spartan-7Artix-7Kintex-7Virtex-7Logic Cells102K215K478K1,955KBlock RAM(1) 4.2Mb13Mb34Mb68MbDSP Slices 1607401,9203,600DSP Performance(2)176 GMAC/s929GMAC/s2,845GMAC/s5,335GMAC/s MicroBlaze CPU(3)260 DMIPs303 DMIPs438 DMIPs441 DMIPs Transceivers–163296Transceiver Speed– 6.6Gb/s12.5Gb/s28.05Gb/sSerial Bandwidth–211Gb/s800Gb/s2,784Gb/sPCIe Interface–x4 Gen2x8 Gen2x8 Gen3Memory Interface800Mb/s1,066Mb/s1,866Mb/s1,866Mb/sI/O Pins400500500 1,200I/O Voltage 1.2V–3.3V 1.2V–3.3V 1.2V–3.3V 1.2V–3.3VPackage Options Low-Cost, Wire-Bond Low-Cost, Wire-Bond,Bare-Die Flip-Chip Bare-Die Flip-Chip and High-Performance Flip-ChipHighest PerformanceFlip-ChipNotes:1.Additional memory available in the form of distributed RAM.2.Peak DSP performance numbers are based on symmetrical filter implementation.3.Peak MicroBlaze CPU performance numbers based on microcontroller preset.Mixed-Mode Clock Manager and Phase-Locked LoopThe MMCM and PLL share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies and as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which speeds up and slows down depending on the input voltage it receives from the phase frequency detector (PFD).There are three sets of programmable frequency dividers: D, M, and O. The pre-divider D (programmable by configuration and afterwards via DRP) reduces the input frequency and feeds one input of the traditional PLL phase/frequency comparator. The feedback divider M (programmable by configuration and afterwards via DRP) acts as a multiplier because it divides the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the VCO within its specified frequency range. The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive one of the output dividers (six for the PLL, O0 to O5, and seven for the MMCM, O0 to O6), each programmable by configuration to divide by any integer from 1 to 128. The MMCM and PLL have three input-jitter filter options: low bandwidth, high bandwidth, or optimized mode. Low-bandwidth mode has the best jitter attenuation but not the smallest phase offset. High-bandwidth mode has the best phase offset, but not the best jitter attenuation. Optimized mode allows the tools to find the best setting.MMCM Additional Programmable FeaturesThe MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one output path. Fractional counters allow non-integer increments of 1/8 and can thus increase frequency synthesis capabilities by a factor of 8.The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency. At 1600MHz, the phase-shift timing increment is 11.2ps.Clock DistributionEach 7series FPGA provides six different types of clock lines (BUFG, BUFR, BUFIO, BUFH, BUFMR, and the high-performance clock) to address the different clocking requirements of high fanout, short propagation delay, and extremely low skew.Global Clock LinesIn each 7series FPGA (except XC7S6 and XC7S15), 32 global clock lines have the highest fanout and can reach every flip-flop clock, clock enable, and set/reset, as well as many logic inputs. There are 12 global clock lines within any clock region driven by the horizontal clock buffers (BUFH). Each BUFH can be independently enabled/disabled, allowing for clocks to be turned off within a region, thereby offering fine-grain control over which clock regions consume power. Global clock lines can be driven by global clock buffers, which can also perform glitchless clock multiplexing and clock enable functions. Global clocks are often driven from the CMT, which can completely eliminate the basic clock distribution delay.Regional ClocksRegional clocks can drive all clock destinations in their region. A region is defined as an area that is 50 I/O and 50 CLB high and half the chip wide. 7series FPGAs have between two and twenty-four regions. There are four regional clock tracks in every region. Each regional clock buffer can be driven from any of four clock-capable input pins, and its frequency can optionally be divided by any integer from 1 to 8.I/O ClocksI/O clocks are especially fast and serve only I/O logic and serializer/deserializer (SerDes) circuits, as described in theI/O Logic section. The 7series devices have a direct connection from the MMCM to the I/O for low-jitter, high-performance interfaces.Block RAMSome of the key features of the block RAM include:•Dual-port 36Kb block RAM with port widths of up to 72•Programmable FIFO logic•Built-in optional error correction circuitryEvery 7series FPGA has between 5 and 1,880 dual-port block RAMs, each storing 36Kb. Each block RAM has two completely independent ports that share nothing but the stored data.Synchronous OperationEach memory access, read or write, is controlled by the clock. All inputs, data, address, clock enables, and write enables are registered. Nothing happens without a clock. The input address is always clocked, retaining data until the next operation. An optional output data pipeline register allows higher clock rates at the cost of an extra cycle of latency.During a write operation, the data output can reflect either the previously stored data, the newly written data, or can remain unchanged.Programmable Data WidthEach port can be configured as 32K×1, 16K×2, 8K×4, 4K×9 (or8), 2K×18 (or16), 1K×36 (or32), or 512×72 (or64). The two ports can have different aspect ratios without any constraints.Each block RAM can be divided into two completely independent 18Kb block RAMs that can each be configured to any aspect ratio from 16K×1 to 512×36. Everything described previously for the full 36Kb block RAM also applies to each of the smaller 18Kb block RAMs.Only in simple dual-port (SDP) mode can data widths of greater than 18bits (18Kb RAM) or 36bits (36Kb RAM) be accessed. In this mode, one port is dedicated to read operation, the other to write operation. In SDP mode, one side (read or write) can be variable, while the other is fixed to 32/36 or 64/72.Both sides of the dual-port 36Kb RAM can be of variable width.Two adjacent 36Kb block RAMs can be configured as one cascaded 64K×1 dual-port RAM without any additional logic. Error Detection and CorrectionEach 64-bit-wide block RAM can generate, store, and utilize eight additional Hamming code bits and perform single-bit error correction and double-bit error detection (ECC) during the read process. The ECC logic can also be used when writing to or reading from external 64- to 72-bit-wide memories.FIFO ControllerThe built-in FIFO controller for single-clock (synchronous) or dual-clock (asynchronous or multirate) operation increments the internal addresses and provides four handshaking flags: full, empty, almost full, and almost empty. The almost full and almost empty flags are freely programmable. Similar to the block RAM, the FIFO width and depth are programmable, but the write and read ports always have identical width.First word fall-through mode presents the first-written word on the data output even before the first read operation. After the first word has been read, there is no difference between this mode and the standard mode.7Series FPGA Ordering InformationTable12 shows the speed and temperature grades available in the different device families. Some devices might not be available in every speed and temperature grade.Table 12:7 Series Speed Grade and Temperature RangesDevice Family DevicesSpeed Grade, Temperature Range, and Operating VoltageCommercial (C)0°C to +85°CExtended (E)0°C to +100°CIndustrial (I)–40°C to +100°CExpanded (Q)–40°C to +125°CSpartan-7All -2C (1.0V)-2I (1.0V)-1C (1.0V)-1I (1.0V)-1Q (1.0V)-1LI (0.95V)Artix-7All-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-1C (1.0V)-1I (1.0V)-1LI (0.95V)Kintex-7XC7K70T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-1C (1.0V)-1I (1.0V) XC7K160TXC7K325TXC7K355TXC7K410TXC7K420TXC7K480T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V or 0.9V)-2LI (0.95V)-1C (1.0V)-1I (1.0V)Virtex-7 TXC7V585T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7V2000T-2C (1.0V)-2GE (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V)Virtex-7 XTXC7VX330TXC7VX415TXC7VX485TXC7VX550TXC7VX690T-3E (1.0V)-2C (1.0V)-2I (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7VX980T-2C (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V) XC7VX1140T-2C (1.0V)-2GE (1.0V)-2LE (1.0V)-1C (1.0V)-1I (1.0V)Virtex-7 HT All -2C (1.0V)-2GE (1.0V)-2LE (1.0V) -1C (1.0V)。

Zynq-7000 SoC First Generation ArchitectureThe Zynq®-7000 family is based on the Xilinx SoC architecture. These products integrate a feature-rich dual-core or single-core ARM® Cortex™-A9 based processing system (PS) and 28nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces. Processing System (PS)ARM Cortex-A9 BasedApplication Processor Unit (APU)• 2.5 DMIPS/MHz per CPU•CPU frequency: Up to 1GHz•Coherent multiprocessor support•ARMv7-A architecture•TrustZone® security•Thumb®-2 instruction set•Jazelle® RCT execution Environment Architecture•NEON™ media-processing engine•Single and double precision Vector Floating Point Unit (VFPU)•CoreSight™ and Program Trace Macrocell (PTM)•Timer and Interrupts•Three watchdog timers•One global timer•Two triple-timer countersCaches•32KB Level1 4-way set-associative instruction and data caches (independent for each CPU)•512KB 8-way set-associative Level2 cache(shared between the CPUs)•Byte-parity supportOn-Chip Memory•On-chip boot ROM•256KB on-chip RAM (OCM)•Byte-parity supportExternal Memory Interfaces•Multiprotocol dynamic memory controller•16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2 memories•ECC support in 16-bit mode•1GB of address space using single rank of 8-, 16-, or 32-bit-wide memories•Static memory interfaces•8-bit SRAM data bus with up to 64MB support•Parallel NOR flash support•ONFI1.0 NAND flash support (1-bit ECC)•1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit) serial NOR flash8-Channel DMA Controller•Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and scatter-gather transaction supportI/O Peripherals and Interfaces•Two 10/100/1000 tri-speed Ethernet MAC peripherals with IEEE Std802.3 and IEEE Std1588 revision 2.0 support•Scatter-gather DMA capability•Recognition of 1588 rev. 2 PTP frames•GMII, RGMII, and SGMII interfaces•Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints •USB 2.0 compliant device IP core•Supports on-the-go, high-speed, full-speed, and low-speed modes•Intel EHCI compliant USB host•8-bit ULPI external PHY interface•Two full CAN 2.0B compliant CAN bus interfaces•CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standardcompliant•External PHY interface•Two SD/SDIO 2.0/MMC3.31 compliant controllers•Two full-duplex SPI ports with three peripheral chip selects•Two high-speed UARTs (up to 1Mb/s)•Two master and slave I2C interfaces•GPIO with four 32-bit banks, of which up to 54 bits can be used with the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits(up to two banks of 32b) connected to the Programmable Logic •Up to 54 flexible multiplexed I/O (MIO) for peripheral pin assignments Interconnect•High-bandwidth connectivity within PS and between PS and PL•ARM AMBA® AXI based•QoS support on critical masters for latency and bandwidth control Zynq-7000 SoC Data Sheet: OverviewDS190 (v1.11.1) July 2, 2018Product SpecificationClock ManagementSome of the key highlights of the clock management architecture include:•High-speed buffers and routing for low-skew clock distribution•Frequency synthesis and phase shifting•Low-jitter clock generation and jitter filteringEach device in the Zynq-7000 family has up to 8 clock management tiles (CMTs), each consisting of one mixed-mode clock manager (MMCM) and one phase-locked loop (PLL). See Table5.Table 5:MMCM Count per DeviceZynq Device MMCM PLLXC7Z007S22XC7Z012S33XC7Z014S44XC7Z01022XC7Z01533XC7Z02044XC7Z03055XC7Z03588XC7Z04588XC7Z10088Mixed-Mode Clock Manager and Phase-Locked LoopThe MMCM and PLL share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies and as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which speeds up and slows down depending on the input voltage it receives from the phase frequency detector (PFD).There are three sets of programmable frequency dividers: D, M, and O. The pre-divider D (programmable by configuration and afterwards via DRP) reduces the input frequency and feeds one input of the traditional PLL phase/frequency comparator. The feedback divider M (programmable by configuration and afterwards via DRP) acts as a multiplier because it divides the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the VCO within its specified frequency range. The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive one of the output dividers (six for the PLL, O0 to O5, and seven for the MMCM, O0 to O6), each programmable by configuration to divide by any integer from 1 to 128. The MMCM and PLL have three input-jitter filter options: Low-bandwidth mode, which has the best jitter attenuation;high-bandwidth mode, which has the best phase offset; and optimized mode, which allows the tools to find the best setting. MMCM Additional Programmable FeaturesThe MMCM can have a fractional counter in either the feedback path (acting as a multiplier) or in one output path. Fractional counters allow non-integer increments of 1/8 and can thus increase frequency synthesis capabilities by a factor of 8.The MMCM can also provide fixed or dynamic phase shift in small increments that depend on the VCO frequency. At1,600MHz, the phase-shift timing increment is 11.2ps.Clock DistributionEach device in the Zynq-7000 family provides six different types of clock lines (BUFG, BUFR, BUFIO, BUFH, BUFMR, and the high-performance clock) to address the different clocking requirements of high fanout, short propagation delay, and extremely low skew.Global Clock LinesIn each device, 32 global clock lines have the highest fanout and can reach every flip-flop clock, clock enable, and set/reset as well as many logic inputs. There are 12 global clock lines within any clock region driven by the horizontal clock buffers (BUFH). Each BUFH can be independently enabled/disabled, allowing for clocks to be turned off within a region, thereby offering fine-grain control over which clock regions consume power. Global clock lines can be driven by global clock buffers, which can also perform glitchless clock multiplexing and clock enable functions. Global clocks are often driven from the CMT, which can completely eliminate the basic clock distribution delay.Regional ClocksRegional clocks can drive all clock destinations in their region. A region is defined as any area that is 50 I/O and 50 CLB high and half the device wide. Each device in the Zynq-7000 family has between four and fourteen regions. There are four regional clock tracks in every region. Each regional clock buffer can be driven from either of four clock-capable input pins, and its frequency can optionally be divided by any integer from 1 to 8.I/O ClocksI/O clocks are especially fast and serve only I/O logic and serializer/deserializer (SerDes) circuits, as described in theI/O Logic section. The SoCs have a direct connection from the MMCM to the I/O for low-jitter, high-performance interfaces. Block RAMSome of the key features of the block RAM include:。

Designing with the CoreThis chapter includes guidelines and additional information to facilitate designing with the core.ClockingThe memory interface requires one MMCM, one TXPLL per I/O bank used by the memory interface, and two BUFGs. These clocking components are used to create the proper clock frequencies and phase shifts necessary for the proper operation of the memory interface.There are two TXPLLs per bank. If a bank is shared by two memory interfaces, both TXPLLs in that bank are used.Note:QDR II+ SRAM generates the appropriate clocking structure and no modifications to the RTL are supported.The QDR II+ SRAM tool generates the appropriate clocking structure for the desiredinterface. This structure must not be modified. The allowed clock configuration is asfollows:•Differential reference clock source connected to GCIO•GCIO to MMCM (located in center bank of memory interface)•MMCM to BUFG (located at center bank of memory interface) driving FPGA logic and all TXPLLs•MMCM to BUFG (located at center bank of memory interface) divide by two mode driving 1/2 rate FPGA logic•Clocking pair of the interface must be in the same SLR of memory interface for the SSI technology devicesProduct SpecificationStandardsThis core complies with the QDR II+ SRAM standard defined by the QDR Consortium. For more information on UltraScale™ architecture documents, see References, page826.PerformanceMaximum FrequenciesFor more information on the maximum frequencies, see the following documentation:•Kintex UltraScale FPGAs Data Sheet, DC and AC Switching Characteristics (DS892) [Ref2]•Virtex UltraScale FPGAs Data Sheet: DC and AC Switching Characteristics (DS893) [Ref3]•Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922) [Ref4]•Virtex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS923) [Ref5]•Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref6]•UltraScale Maximum Memory Performance Utility (XTP414) [Ref21]Resource UtilizationFor full details about performance and resource utilization, visit Performance and Resource Utilization.Chapter 27:Example Design Simulating the Example Design (Designs with Standard User Interface)The example design provides a synthesizable test bench to generate a fixed simple data pattern to the Memory Controller. This test bench consists of an IP wrapper and an example_tb that generates 16 writes and 16 reads. QDR-IV SRAM does not deliver the QDR-IV memory models. The memory model required for the simulation must be downloaded from the memory vendor’s website.The example design can be simulated using one of the methods in the following sections. Project-Based SimulationThis method can be used to simulate the example design using the Vivado Integrated Design Environment (IDE). Memory IP does not deliver the QDR-IV memory models. The memory model required for the simulation must be downloaded from the memory vendor website. The memory model file must be added in the example design using Add Sources option to run simulation.The Vivado simulator, Questa Advanced Simulator, IES, and VCS tools are used for QDR-IV IP verification at each software release. The Vivado simulation tool is used for QDR-IV IP verification from 2015.1 Vivado software release. The following subsections describe steps to run a project-based simulation using each supported simulator tool.。

SPI InterfacesTable 43:SPI Master Mode Interface Switching Characteristics (1)Symbol DescriptionMin Typ Max Units T DCMSPICLK SPI master mode clock duty cycle –50–%T MSPIDCK Input setup time for SPI {0,1}_MISO 2.00––ns T MSPICKD Input hold time for SPI {0,1}_MISO8.20––ns T MSPICKO Output delay for SPI {0,1}_MOSI and SPI {0,1}_SS –3.10– 3.90nsT MSPISSCLK Slave select asserted to first active clock edge 1––F SPI_REF_CLK cycles T MSPICLKSS Last active clock edge to slave select deasserted 0.5––F SPI_REF_CLK cyclesF MSPICLK SPI master mode device clock frequency ––50.00MHz F SPI_REF_CLK SPI reference clock frequency––200.00MHzNotes:1.Test conditions: LVCMOS33, slow slew rate, 8mA drive strength, 15pF loads.Figure 12:SPI Master (CPHA =0) Interface Timing DiagramFigure 13:SPI Master (CPHA =1) Interface Timing DiagramPL Performance CharacteristicsThis section provides the performance characteristics of some common functions and designs implemented in the PL. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the AC Switching Characteristics, page 15. In each table, the I/O bank type is either High Performance (HP) or High Range (HR).Table 53 provides the maximum data rates for applicable memory standards using the Zynq-7000SoC memory PHY. The final performance of the memory interface is determined through a complete design implemented in the Vivado or ISE Design Suite, following guidelines in the Zynq-7000 SoC and 7Series Devices Memory Interface Solutions User Guide (UG586).Table 52:PL Networking Applications Interface PerformancesDescriptionI/O Bank Type Speed GradeUnits -3E -2E/-2I/-2LI-1C/-1I -1Q/-1LQ SDR LVDS transmitter (using OSERDES; DATA_WIDTH =4 to 8)HR 710710625625Mb/s HP 710710625625Mb/s DDR LVDS transmitter (using OSERDES; DATA_WIDTH =4 to 14)HR 12501250950950Mb/s HP 1600140012501250Mb/s SDR LVDS receiver (SFI-4.1)(1)HR 710710625625Mb/s HP 710710625625Mb/s DDR LVDS receiver (SPI-4.2)(1)HR 12501250950950Mb/s HP1600140012501250Mb/sNotes:1.LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate deterministic performance.PS ConfigurationDDR Memory InterfacesTable 25:PS Reset/Power Supply Timing RequirementsSymbol DescriptionPS_CLK Frequency(MHz)Min Max Units T SLW (1)128KB CRC eFUSE disabled and PLL enabled.Default configuration301239ms 33.331240ms 601340ms 128KB CRC eFUSE disabled and PLL in bypass.30–3213ms 33.33–2713ms 60–925ms 128KB CRC eFUSE enabled and PLL enabled.(2)30–199ms 33.33–1612ms 60–325ms 128KB CRC eFUSE enabled and PLL in bypass.(2)30–830–788ms 33.33–746–705ms 60–408–374msNotes:1.Valid for power supply ramp times of less than 6ms. For ramp times longer than 6ms, see the BootROM Performance section of the Zynq-7000SoC Technical Reference Manual (UG585).2.If any PS and PL power supplies are tied together, observe the PS_POR_B assertion time requirement (T PSPOR ) in Table 24 and its accompanying note.Table 26:Processor Configuration Access Port Switching CharacteristicsSymbol DescriptionMin Typ Max Units F PCAPCKMaximum processor configuration access port (PCAP) frequency––100MHzTable 27:DDR3 Interface Switching Characteristics (1333Mb/s)(1)Symbol Description Min Max Units T DQVALID (2)Input data valid window 450–ps T DQDS (3)Output DQ to DQS skew 95–ps T DQDH (4)Output DQS to DQ skew 222–ps T DQSS Output clock to DQS skew–0.110.08T CK T CACK (5)Command/address output setup time with respect to CLK 465–ps T CKCA (6)Command/address output hold time with respect to CLK528–ps质量等级领域:宇航级IC 、特军级IC 、超军级IC 、普军级IC 、禁运IC 、工业级IC ，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以深圳市美光存储技术有限公司提供的参数为例，以下为XC7Z035-2FFG676I的详细参数，仅供参考。

UltraScale Architecture-Based FPGAs Memory IP v1.4PG150 January 21, 2021Chapter 4:Designing with the CoreEXTRA_CMD_DELAY ParameterDepending on the number of ranks, ECC mode, and DRAM latency configuration, PHY must be programmed to add latency on the DRAM command address bus. This provides enough pipeline stages in the PHY programmable logic to close timing and to process mcWrCAS . Added command latency is generally needed at very low CWL in single-rank configurations, or in multi-rank configurations. Enabling ECC might also require adding command latency, but this depends on whether your controller design (outside the PHY) depends on receiving the wrDataEn signal a system clock cycle early to allow for generating ECC check bits.The EXTRA_CMD_DELAY parameter is used to add one or two system clock cycles of delay on the DRAM command/address path. The parameter does not delay the mcWrCAS ormcRdCAS signals. This gives the PHY more time from the assertion of mcWrCAS or mcRdCAS to generate XIPHY control signals. To the PHY, an EXTRA_CMD_DELAY setting of one or two is the same as having a higher CWL or AL setting.Table 4-75 shows the required EXTRA_CMD_DELAY setting for various configurations of CWL, CL, and AL. CAL_WR_DQS_DQ "FULL""FULL"Flag for calibration, write DQS-to-DQ setting CAL_COMPLEX "FULL""SKIP", "FULL"Flag for calibration, complex pattern setting CAL_RD_VREF "SKIP""SKIP", "FULL"Flag for calibration, read V REF setting CAL_WR_VREF "SKIP""SKIP", "FULL"Flag for calibration, write V REF setting CAL_JITTER "FULL""FULL", "NONE"Reserved for verification. Speed up calibration simulation. Must be set to "FULL" for all hardware test cases.t200us 53305 decimal 0x3FFFF.. 1Wait period after BISC complete to DRAM reset_n deassertion in system clockst500us 133263 decimal 0x3FFFF.. 1Wait period after DRAM reset_n deassertion to CKE assertion in system clocks Table 4-74:PHY Only Parameters (Cont’d)Parameter Name Default ValueAllowable Values Description Table 4-75:EXTRA_CMD_DELAY Configuration SettingsDRAM ConfigurationRequired EXTRA_CMD_DELAY DRAM CAS Write Latency CWL DRAM CAS Latency CLDRAM Additive Latency MR1[4:3]Single-Rank without ECC Single-Rank with ECC or Multi-Rank 550125510155212UltraScale Architecture-Based FPGAs Memory IP v1.4PG150 January 21, 2021Chapter 4:Designing with the CoreTwo DDR3 32-bit interfaces can fit in three banks by using all of the pins in the banks. To fit the configuration in three banks for various scenarios, different Vivado IDE options can be selected (based on requirement). Various Vivado IDE options that lead to pin savings are listed as follows:•In data byte group, pins 1 and 12 are unused. Unused pins of the data byte group can be used for Address/Control pins if all Address/Control pins are allocated in the same bank.For example, if T3 byte group of Bank #2 is selected for data. Pins T3L_1 and T3U_12 are not used by data and these pins can be used for Address/Control if all Address/Control pins are allocated in Bank #2.•If DCI cascade is selected, the vrp pin can be used as normal a I/O.•Memory reset pin (reset_n pin) can be allocated anywhere as long as timing is met.•System clock pins can be allocated in different banks and must be within the same column of the memory interface banks selected.•By disabling the Enabling Chip Select Pin option in the Vivado IDE, it frees up a pin and the cs# ports are not generated.•By disabling the Data Mask option in Vivado IDE, it frees up a pin and the data mask (dm ) port is not generated.One of the configurations with two 32-bit DDR3 interfaces in three banks is given in Table 4-5 (it is valid for memory part of x8/x16). Two interface signals are separated by name c0_ and c1_. Example is given with interface-0 (c0) selected in banks 0 and 1 and interface-1 (c1) selected in banks 1 and 2. 1dqs0_n T0L_1N 1dqs0_p T0L_0PTable 4-5:Two 32-Bit DDR3 Interfaces Contained in Three Banks BankSignal Name Byte Group I/O Type 2c1_ddr3_we_n T3U_12–2c1_ddr3_ck_c[0]T3U_11N 2c1_ddr3_ck_t[0]T3U_10P 2c1_ddr3_cas_n T3U_9N 2c1_ddr3_ras_n T3U_8P 2c1_ddr3_ba[2]T3U_7N 2c1_ddr3_ba[1]T3U_6P 2c1_ddr3_ba[0]T3L_5N Table 4-4:16-Bit DDR3 Interface (x4 Part) Contained in One Bank (Cont’d)BankSignal Name Byte Group I/O Type。

Table 98:GTX Transceiver Receiver Switching CharacteristicsSymbol Description Min Typ Max Units F GTXRX Serial data rate0.500–F GTXMAX Gb/s T RXELECIDLE Time for RXELECIDLE to respond to loss or restoration of data–10–ns RX OOBVDPP OOB detect threshold peak-to-peak60–150mVRX SST Receiver spread-spectrumtracking(1)Modulated @ 33KHz–5000–0ppmRX RL Run length (CID)––512UIRX PPMTOL Data/REFCLK PPM offsettoleranceBit rates≤6.6Gb/s–1250–1250ppmBit rates >6.6Gb/s and≤8.0Gb/s–700–700ppmBit rates>8.0Gb/s–200–200ppmSJ Jitter Tolerance(2)JT_SJ12.5Sinusoidal jitter (QPLL)(3)12.5Gb/s0.3––UI JT_SJ11.18Sinusoidal jitter (QPLL)(3)11.18Gb/s0.3––UI JT_SJ10.32Sinusoidal jitter (QPLL)(3)10.32Gb/s0.3––UI JT_SJ9.95Sinusoidal jitter (QPLL)(3)9.95Gb/s0.3––UI JT_SJ9.8Sinusoidal jitter (QPLL)(3)9.8Gb/s0.3––UI JT_SJ8.0Sinusoidal jitter (QPLL)(3)8.0Gb/s0.44––UI JT_SJ6.6_QPLL Sinusoidal jitter (QPLL)(3) 6.6Gb/s0.48––UI JT_SJ6.6_CPLL Sinusoidal jitter (CPLL)(3) 6.6Gb/s0.44––UI JT_SJ5.0Sinusoidal jitter (CPLL)(3) 5.0Gb/s0.44––UI JT_SJ4.25Sinusoidal jitter (CPLL)(3) 4.25Gb/s0.44––UI JT_SJ3.75Sinusoidal jitter (CPLL)(3) 3.75Gb/s0.44––UI JT_SJ3.2Sinusoidal jitter (CPLL)(3) 3.2Gb/s(4)0.45––UI JT_SJ3.2L Sinusoidal jitter (CPLL)(3) 3.2Gb/s(5)0.45––UI JT_SJ2.5Sinusoidal jitter (CPLL)(3) 2.5Gb/s(6)0.5––UI JT_SJ1.25Sinusoidal jitter (CPLL)(3) 1.25Gb/s(7)0.5––UI JT_SJ500Sinusoidal jitter (CPLL)(3)500Mb/s0.4––UI SJ Jitter Tolerance with Stressed Eye(2)JT_TJSE3.2Total jitter with stressed eye(8)3.2Gb/s0.70––UI 6.6Gb/s0.70––UIJT_SJSE3.2Sinusoidal jitter with stressedeye(8)3.2Gb/s0.1––UI6.6Gb/s0.1––UINotes:ing RXOUT_DIV=1, 2, and 4.2.All jitter values are based on a bit error ratio of 1e–12.3.The frequency of the injected sinusoidal jitter is 10MHz.4.CPLL frequency at 3.2GHz and RXOUT_DIV=2.5.CPLL frequency at 1.6GHz and RXOUT_DIV=1.6.CPLL frequency at 2.5GHz and RXOUT_DIV=2.7.CPLL frequency at 2.5GHz and RXOUT_DIV=4.posite jitter with RX and LPM or DFE mode.GTX Transceiver Protocol Jitter CharacteristicsFor Table99 through Table104, the 7Series FPGAs GTX/GTH Transceivers User Guide (UG476) contains recommended settings for optimal usage of protocol specific characteristics.Table 99:Gigabit Ethernet Protocol CharacteristicsDescription Line Rate (Mb/s)Min Max Units Gigabit Ethernet Transmitter Jitter GenerationTotal transmitter jitter (T_TJ)1250–0.24UI Gigabit Ethernet Receiver High Frequency Jitter ToleranceTotal receiver jitter tolerance12500.749–UI Table 100:XAUI Protocol CharacteristicsDescription Line Rate (Mb/s)Min Max Units XAUI Transmitter Jitter GenerationTotal transmitter jitter (T_TJ)3125–0.35UI XAUI Receiver High Frequency Jitter ToleranceTotal receiver jitter tolerance31250.65–UITable 101:PCI Express Protocol Characteristics(1)Standard Description Line Rate (Mb/s)Min Max Units PCI Express Transmitter Jitter GenerationPCI Express Gen 1Total transmitter jitter2500–0.25UI PCI Express Gen 2Total transmitter jitter5000–0.25UIPCI Express Gen 3Total transmitter jitter uncorrelated8000–31.25ps Deterministic transmitter jitter uncorrelated–12psPCI Express Receiver High Frequency Jitter TolerancePCI Express Gen 1Total receiver jitter tolerance25000.65–UIPCI Express Gen 2(2)Receiver inherent timing error50000.40–UI Receiver inherent deterministic timing error0.30–UIPCI Express Gen 3Receiver sinusoidal jittertolerance0.03MHz–1.0MHz80001.00–UI1.0MHz–10MHz Note3–UI10MHz–100MHz0.10–UINotes:1.Tested per card electromechanical(CEM)methodology.ing common REFCLK.3.Between 1MHz and 10MHz the minimum sinusoidal jitter roll-off with a slope of 20dB/decade.。

Device ConfigurationZynq-7000 XC7Z020 SoC uses a multi-stage boot process that supports both a non-secure and a secure boot. The PS is the master of the boot and configuration process. For a secure boot, the PL must be powered on to enable the use of the security block located within the PL, which provides 256-bit AES and SHA decryption/authentication.The ZC702 board supports these configuration options:•PS Configuration: Quad SPI flash memory•PS Configuration: Processor System Boot from SD Card (J64)•PL Configuration: USB JTAG configuration port (Digilent module)•PL Configuration: Platform cable header J2 and flying lead header J58 JTAG configuration portsThe JTAG configuration option is selected by setting SW16 as shown in Table 1-2 and SW10 as described in Programmable Logic JTAG Programming Options for PL configuration details. SW10 is callout 23 in Figure 1-2.Note:For more information about Zynq-7000 SoC configuration settings, see the Zynq-7000 SoCTechnical Reference Manual (UG585) [Ref 2].Table 1-2:Switch SW16 Configuration Option Settings Boot ModeSW16.1SW16.2SW16.3SW16.4SW16.5JTAG mode (1)00000Independent JTAG mode 10000Quad SPI mode 00010SD mode00110MIO configuration pinMIO2MIO3MIO4MIO5MIO6Notes:1.Default switch settingThe configuration and Quad SPI section of the Zynq-7000 SoC Technical Reference Manual(UG585) [Ref 2] provides details on using the Quad-SPI flash memory.Figure 1-6 shows the connections of the linear Quad SPI flash memory on the ZC702 board. For more details, see the Micron N25Q128A11ESF40G data sheet at the Micron website [Ref 14].USB 2.0 ULPI Transceiver[Figure 1-2, callout 4]The ZC702 board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI Transceiver at U9 to support a USB connection to the host computer. A USB cable is supplied in the ZC702 Evaluation Kit (Standard-A connector to host computer, Mini-B connector to ZC702 board connector J1). The USB3320 is a high-speed USB 2.0 PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard defines the interface between the USB controller IP and the PHY device which drives the physical USB bus. Use of the ULPI standard reduces the interface pin count between the USB controller IP and the PHY device.PS_MIO3500F6QSPI_IO18DQ1J20.2PS_MIO2500A2QSPI_IO015DQ0J21.2PS_MIO1500A1QSPI_CS_B7S_BNANotes:Each three-pin MIO select header has pin 1 wired to VCCMIO and pin 3 wired to GND.Table 1-5:Quad SPI Flash Memory Connections to the XC7Z020 SoC (Cont’d)XC7Z020 (U1)Schematic Net Name Quad-SPI Flash Memory (U41)MIO SelectHeader Pin NameBankPin Number Pin Number Pin NameFigure 1-6:128Mb Quad-SPI Flash Memory (U41)USB ConnectorJ1Net Name Description USB3320 (U9)PinPin Name1VBUS USB_VBUS_SEL+5V from host system222D_N USB_D_N Bidirectional differential serial data (N-side)193D_P USB_D_P Bidirectional differential serial data (P-side)185GND GND Signal ground33The connections between the USB 2.0 PHY at U9 and the XC7Z020 SoC are listed inTable1-8.Table 1-8:USB 2.0 ULPI Transceiver Connections to the XC7Z020 SoCXC7Z020 (U1)Schematic Net Name USB3320 (U9) Pin Pin Name Bank Pin NumberPS_MIO36501A9USB_CLKOUT1PS_MIO31501F9USB_NXT2PS_MIO32501C7USB_DATA03PS_MIO33501G13USB_DATA14PS_MIO34501B12USB_DATA25PS_MIO35501F14USB_DATA36PS_MIO28501A12USB_DATA47PS_MIO37501B14USB_DATA59PS_MIO38501F13USB_DATA610PS_MIO39501C13USB_DATA713PS_MIO30501A11USB_STP29PS_MIO29501E8USB_DIR31PS_MIO7500D5USB_RESET_B_AND27 (through AND gate U62)。

Transition Schedule forSubstrate Supplier for Virtex-6and 7 Series FPGAs Flip ChipPackagesXTP385 (v2.0) March 30, 2015 FAQ: Implications of XCN14012OverviewTo ensure business continuity and enable high volume supply chain capabilities for all Virtex®-6 and selected7 series FPGAs product families, Xilinx is qualifying an additional substrate supplier, Unimicron Technology Corporation (UMTC) for flip chip ball grid area (FCBGA) packages.For Virtex-6 FPGAs, this change affects all standard and specification control document (SCD) XC Commercial (C) and Industrial (I) grade devices. Hi-Rel “XQ” devices are not affected by this PCN.For Artix®-7, Zynq®-7000 All Programmable, Virtex®-7 and Kintex®-7 in the SB, FB, FF, SBG, FBG and FFG packages, this change affects all standard and specification control document (SCD) XC Commercial (C) grade, Extended (E) grade and Industrial (I) grade devices. Virtex-7 in the FL, FLG, FH and FHG packages, and Automotive “XA” devices for 7 series FPGAs are not affected by this PCN. Kintex®-7Q, Virtex®-7Q and Zynq®-7000Q All Programmable Hi-Rel “XQ” FPGAs RF flip chip packages are affected (Refer to XCN14013).This additional supplier will adhere to the same performance, quality and reliability specifications that apply to all product families proven through extensive qualification and testing. As a result, there is no change in form, fit, function, or reliability with this substrate supplier addition.FAQsQ: What is the change?Xilinx is qualifying an additional substrate supplier, Unimicron Technology Corporation (UMTC) for flip chip ball grid area (FCBGA) packages for all Virtex-6 and selected 7 series FPGAs product families. UMTC is a reputable company supplying component substrate and system printed circuit board to many semiconductor customers and original equipment make (OEM) customers for over 10 years.Q: Why is Xilinx making this change?This change ensures business continuity and enables high volume supply chain capabilities for Xilinx product families.Q: Why adding Phase 3?As a result of the successful implementation for Xilinx FPGAs (Virtex-6 FPGAs and 7-series), we are expanding this program to include SoC (Zynq-7000 All Programmable) to this change.Q: Which products are affected?For Virtex-6 FPGAs, this change affects all standard and specification control document (SCD) XC Commercial (C) and Industrial (I) grade devices. Hi-Rel “XQ” devices in the FFG1156 package are not affected by this PCN.For Artix-7, Zynq-7000 All Programmable, Virtex-7 and Kintex-7 in the SB, FB, FF, SBG, FBG and FFG packages, this change affects all standard and specification control document (SCD) XC Commercial (C) grade, Extended (E) grade and Industrial (I) grade devices. Virtex-7 in the FL, FLG, FH and FHG packages, and Automotive “XA” devices XTP385 (v2.0) March 30, 2015FAQ: Transition Schedule for Substrate Supplier for Virtex-6 and 7 Series FPGAs Flip Chip PackagesXTP385 (v2.0) March 30, 2015for 7 series FPGAs are not affected by this PCN. Kintex-7Q, Virtex-7Q and Zynq-7000Q All Programmable Hi-Rel “XQ” FPGAs RF flip chip packages are affected (Refer to XCN14013).Affected device package-pin are listed in the Table 1, Table 2, Table 3, Table 4 and Table 5 below:FAQ: Transition Schedule for Substrate Supplier for Virtex-6 and 7 Series FPGAs Flip Chip PackagesXTP385 (v2.0) March 30, 2015FAQ: Transition Schedule for Substrate Supplier for Virtex-6 and 7 Series FPGAs Flip Chip PackagesXTP385 (v2.0) March 30, 2015Table 7: Phase 2 - Artix-7, Kintex-7 and Virtex-7 Devices Qualification Completion and Cross-ShipScheduleFAQ: Transition Schedule for Substrate Supplier for Virtex-6 and 7 Series FPGAs Flip Chip Packages Revision HistoryThe following table shows the revision history for this document:XTP385 (v2.0) March 30, 2015。

forces a storage element into the initialization state speci-fied for it in the configuration. BY forces it into the opposite state. Alternatively, these signals can be configured to oper-ate asynchronously. All of the control signals are indepen-dently invertible, and are shared by the two flip-flops within the slice.Additional LogicThe F5 multiplexer in each slice combines the function gen-erator outputs. This combination provides either a function generator that can implement any 5-input function, a 4:1 multiplexer, or selected functions of up to nine inputs. Similarly, the F6 multiplexer combines the outputs of all four function generators in the CLB by selecting one of the F5-multiplexer outputs. This permits the implementation of any 6-input function, an 8:1 multiplexer, or selected func-tions of up to 19 inputs.Each CLB has four direct feedthrough paths, two per slice. These paths provide extra data input lines or additional localrouting that does not consume logic resources. Arithmetic LogicDedicated carry logic provides fast arithmetic carry capabil-ity for high-speed arithmetic functions. The Virtex-E CLB supports two separate carry chains, one per Slice. The height of the carry chains is two bits per CLB.The arithmetic logic includes an XOR gate that allows a 2-bit full adder to be implemented within a slice. In addition, a dedicated AND gate improves the efficiency of multiplier implementation. The dedicated carry path can also be used to cascade function generators for implementing wide logic functions.BUFTsEach Virtex-E CLB contains two 3-state drivers (B UFTs) that can drive on-chip buses. See Dedicated Routing. Each Virtex-E BUFT has an independent 3-state control pin and an independent input pin.Block SelectRAMVirtex-E FPGAs incorporate large block SelectRAM memo-ries. These complement the Distributed SelectRAM memo-ries that provide shallow RAM structures implemented in CLBs.Block SelectRAM memory blocks are organized in columns, starting at the left (column 0) and right outside edges and inserted every 12 CLB columns (see notes for smaller devices). Each memory block is four CLBs high, and each memory column extends the full height of the chip, immedi-ately adjacent (to the right, except for column 0) of the CLB column locations indicated in T able3.Table4 shows the amount of block SelectRAM memory that is available in each Virtex-E device.As illustrated in Figure6, each block SelectRAM cell is a fully synchronous dual-ported (True Dual Port) 4096-bit RAM with independent control signals for each port. The data widths of the two ports can be configured indepen-dently, providing built-in bus-width conversion.Table 3: CLB/Block RAM Column Locations XCVDevice/Col.01224364860728496108120138156 50E Columns 0, 6, 18, & 24100E Columns 0, 12, 18, & 30200E Columns 0, 12, 30, & 42300E√√√√400E√√√√600E√√√√√√1000E√√√√√√1600E√√√√√√√√2000E√√√√√√√√2600E√√√√√√√√3200E√√√√√√√√Table 4: Virtex-E Block SelectRAM AmountsVirtex-E Device# of Blocks Block SelectRAM Bits XCV50E1665,536XCV100E2081,920XCV200E28114,688XCV300E32131,072XCV400E40163,840XCV600E72294,912XCV1000E96393,216XCV1600E144589,824XCV2000E160655,360XCV2600E184753,664XCV3200E208851,968DLL Clock Tolerance, Jitter, and Phase InformationAll DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock mirror configuration and matched drivers.CLKDLLHF CLKDLLMin Max Min MaxDescription Symbol FUnitsCLKINInput Clock Period Tolerance T IPTOL- 1.0- 1.0ns Input Clock Jitter Tolerance (Cycle to Cycle)T IJITCC-±150-±300ps Time Required for DLL to Acquire Lock(6)T LOCK>60 MHz-20-20μs50 - 60 MHz---25μs40 - 50 MHz---50μs30 - 40 MHz---90μs25 - 30 MHz---120μs Output Jitter (cycle-to-cycle) for any DLL Clock Output(1)T OJITCC±60±60ps Phase Offset between CLKIN and CLKO(2)T PHIO±100±100ps Phase Offset between Clock Outputs on the DLL(3)T PHOO±140±140ps Maximum Phase Difference between CLKIN and CLKO(4)T PHIOM±160±160ps Maximum Phase Difference between Clock Outputs on the DLL(5)T PHOOM±200±200ps Notes:1.Output Jitter is cycle-to-cycle jitter measured on the DLL output clock and is based on a maximum tap delay resolution, excludinginput clock jitter.2.Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,excluding Output Jitter and input clock jitter.3.Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLLoutputs, excluding Output Jitter and input clock jitter.4.Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).5.Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLLclock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter). 6.Add 30% to the value for industrial grade parts.。

About ASCII Package FilesThe ASCII files for each package include a comma-separated-values (CSV) version and a text version optimized for a browser or text editor. Each of the files consists of the following:•Device/Package name (FPGA Family—Device—Package), date and time of creation •Eight columns containing data for each pin:CPGA196 (Spartan-7 FPGAs)Wire-Bond Chip-Scale BGA (0.5mm Pitch)Figure 4-1:CPGA196 Wire-Bond Chip-Scale BGA Package Specifications for Spartan-7 FPGAsFT/FTG256 (Artix-7 FPGAs) Wire-Bond Fine-Pitch Thin BGA (1.0mm Pitch)SB484, SBG484, and SBV484 (Artix-7 FPGAs)Flip-Chip Lidless BGA (0.8mm Pitch)Figure 4-11:SB484, SBG484, and SBV484 Flip-Chip Lidless BGA Package Specifications for Artix-7 FPGAsChapter 5:Thermal Specifications A parallel effort to ensure optimized package electrical return paths produces the added benefit of enhanced power and ground plane arrangement in the packages. A boost in copper density on the planes improves the overall thermal conductivity through the laminate. In addition, the extra dense and distributed via fields in the package increase the vertical thermal conductivity. These packages offer up to 20% lower θJB compared to previous flip-chip packages.System Level Heat Sink SolutionsTo complete a comprehensive thermal management strategy, an overall thermal budget that includes custom or OEM heat sink solutions depends on the physical and mechanical constraints of the system. A heat-sink solution, managed by the system-level designer, should be tailored to the design and specific system constraints. This includes understanding the inherent device capabilities for delivering heat to the surface.。

Designing with the Targeted Reference Design PlatformThe TRD acts as a framework for system designers to derive extensions or modify designs.This chapter outlines various ways for a user to evaluate, modify, and re-run the TRD. Thesuggested modifications are grouped under these categories:•Software-only modifications are made by modifying software components only(drivers, demo parameters, and so on.). The design does not need to bere-implemented.•Hardware-only modifications are made by modifying hardware components only. Thedesign must be re-implemented through the Vivado® design tool. For example, toadd or replace IP blocks, The user must ensure the new blocks can communicate withthe existing interfaces in the framework. The user is also responsible to make sure thatthe new IP does not break the functionality of the existing framework.All of these use models are fully supported by the framework, provided that themodifications do not require the supported IP components to operate outside the scope oftheir specified functionality.This chapter provides examples to illustrate some of these use models. While some aresimple modifications to the design, others involve replacement or addition of new IP. Thenew IP could come from Xilinx (and its partners) or from the customer's internal IPactivities.Software-Only ModificationsChapter 4:Performance EstimationTransaction OverheadACKOverheadCommentMRD for C2S Desc = 20/4096 = 0.625/1288/4096 =0.25/128One descriptor fetch from C2S enginefor 4KB data (TRN-TX); 20B of TLPoverhead and 8 bytes DLLPoverheadCPLD for C2S Desc = 20+32/4096 = 1.625/1288/4096=0.25/128Descriptor reception by C2S engine(TRN-RX). CPLD Header is 20 bytes,and the C2S Desc data is 32 bytes.MWR for C2S buffer = 20/1288/128MPS = 128B; Buffer write from C2Sengine (TRN-TX)MWR for C2S Desc update = 20+12/4096 = 1/1288/4096 =0.25/128Descriptor update from C2S engine(TRN-TX). MWR header is 20 bytes,and the C2S Desc update data is 12bytes.Theoretical EstimateThe S2C DMA engine (which deals with data transmission that is, reading data from system memory) first does a buffer descriptor fetch. Using the buffer address in thedescriptor, it issues memory read requests and receives data from system memory through completions. When the actual payload is transferred from the system, it sends a memory write to update the buffer descriptor. Table 4-2 shows the overhead incurred during data transfer in the S2C direction.For every 128 bytes of data sent from system to card, the overhead on the downstream link (italicized text ) is 50.125bytes.% Overhead = 50.125/128 + 50.125 = 28.14%The throughput per PCIe lane is 5Gb/s, but because of 8B/10B encoding, the throughput comes down to 4Gb/s.Maximum theoretical throughput per lane for Transmit = (100 – 28.14)/100 x 4 = 2.86Gb/sMaximum theoretical throughput for a x4 Gen2 or x8 Gen1 link for Transmit = 11.49Gb/s.For transmit (S2C), the effective throughput is 11.4G/s and for receive (C2S) it is 13.6G/s.The throughput numbers are theoretical and could go down further due other factors. •The transaction interface of PCIe is 128-bits wide. The data sent is not always 128-bit aligned and this could cause some reduction in throughput.•Changes in MPS, MRRS, RCB, buffer descriptor size also have significant impact on the throughput.•If bidirectional traffic is enabled then overhead incurred is more reducing throughput further•Software overhead/latencies also contribute to reduction in throughput.Table 4-2:PCI Express Performance Estimation with DMA in the S2C DirectionTransaction Overhead ACK Overhead CommentMRD for S2CDesc=20/4096=0.625/1288/4096 = 0.25/128Descriptor fetch from S2C engine (TRN-TX)CPLD for S2CDesc=20+32/4096=1.625/1288/4096 = 0.25/128Descriptor reception by S2C engine (TRN-RX). CPLD Header is 20 bytes and the S2C Desc data is 32 bytes.MRD for S2C Buffer = 20/1288/128Buffer fetch from S2C engine (TRN-TX). MRRS=128BCPLD for S2C buffer = 20/64 = 40/1288/64=16/128Buffer reception by S2C engine (TRN-RX). Because RCB=64B, 2completions are received for every 128 byte read requestMWR for S2CDesc=20+4/4096=0.75/1288/4096=0.25/128Descriptor update from S2C engine (TRN-TX). MWR Header is 20 bytes and the S2C Desc update data is 12 bytes.Chapter 5:Designing with the Targeted Reference Design PlatformHardware-Only ModificationsThis section describes architecture changes to the functionality of the platform. Thesechanges include adding or deleting IP having similar interfaces used in the framework.The user can connect any other IP similar to the Aurora core and use the same drivers andtest the design.Appendix A:Register DescriptionsChannel Specific RegistersThe registers described in this section are present in all channels. The address of theregister is offset from BAR0 (Table A-1) + the register offset.Engine Control (0x0004)Table A-3:DMA Engine Control RegisterBit Field Mode DefaultValueDescription0Interrupt Enable RW0Enables interrupt generation1Interrupt Active RW1C0Interrupt active is set whenever an interrupt event occurs. Write '1' to clear.2Descriptor Complete RW1C0Interrupt active was asserted due to completion of descriptor. This is asserted when a descriptor with interrupt on completion bit set is seen.3Descriptor Alignment Error RW1C0This causes interrupt when a descriptor address is unaligned, and that DMA operation is aborted.4Descriptor Fetch Error RW1C0This causes interrupt when a descriptor fetch errors, that is, completion status is not successful.5SW_Abort_Error RW1C0This is asserted when a DMA operation is aborted by software.8DMA Enable RW0Enables the DMA engine. After enabled, the engine compares the next descriptor pointer and software descriptor pointer to begin execution.10DMA_Running RO0Indicates DMA in operation.11DMA_Waiting RO0Indicates DMA waiting on software to provide more descriptors.14DMA_Reset_Request RW0Issues a request to user logic connected to DMA to abort outstanding operation and prepare for reset. This is cleared when user acknowledges the reset request.15DMA_Reset RW0Assertion of this bit resets the DMA engine and issues a reset to user logic.。

AC701 Evaluation Board FeaturesOverviewThe AC701 evaluation board for the Artix®-7 FPGA provides a hardware environment fordeveloping and evaluating designs targeting the Artix-7 XC7A200T-2FBG676C FPGA. The AC701board provides features common to many embedded processing systems, including a DDR3SODIMM memory, an 4-lane PCI Express® interface, a tri-mode Ethernet PHY, general purpose I/O, and a UART interface. Other features can be added by using an FPGA mezzanine card (FMC)attached to the VITA-57 FPGA mezzanine connector provided on the board. A high pin count(HPC) FMC connector is provided. See AC701 Board Features for a complete list of features. Thedetails for each feature are described in Feature Descriptions.Feature DescriptionsArtix-7 FPGA[Figure 1-2, callout 1]The AC701 board is populated with the Artix-7 XC7A200T-2FBG676C FPGA.For further information on Artix-7 FPGAs, see 7 Series FPGAs Overview (DS180) [Ref 2].FPGA ConfigurationThe AC701 board supports two of the five 7 series FPGA configuration modes:•Master SPI flash memory using the onboard Quad SPI flash memory•JTAG using a standard-A to micro-B USB cable for connecting the host PC to the AC701board configuration port or by J4 Platform Cable USB/Parallel Cable IV flat cable connectorEach configuration interface corresponds to one or more configuration modes and bus widths as listed in Table 1-2. The mode switches M2, M1, and M0 are on SW1 positions 1, 2, and 3 respectively, as shown in Figure 1-3.The default mode setting is M[2:0] = 001, which selects Master SPI flash memory at board power-on. See Configuration Options for more information about the mode switch SW1.35U3, U4GTP transceiver clock multiplexersMicrel SY89544UMG30Notes:1.Jumper header locations are identified in Default Jumper Settings in Appendix A .Table 1-1: AC701 Board Component Descriptions (Cont’d)CalloutReferenceDesignator Component Description NotesSchematic 0381502Page NumberFigure 1-3: SW1 Default SettingsTable 1-2: AC701 Board FPGA Configuration ModesConfigurationModeSW1 DIP switch Settings (M[2:0])Bus Width CCLK Direction Master SPI flash memory 001x1, x2, x4Output JTAG101x1Not applicableChapter 1: AC701 Evaluation Board FeaturesFigure 1-5: 256 Mb Quad SPI Flash MemoryFeature DescriptionsU1 FPGA Pin Schematic Net Name J7 PinAE16FPGA_PROG_B1 Array N14FLASH_D32P14FLASH_D23J3.2QSPI_CS_B4R14FLASH_D05R15FLASH_D16H13FPGA_CCLK7NA GND8NA VCC3V39Chapter 1: AC701 Evaluation Board FeaturesGTP Transceiver Clock Multiplexer[Figure 1-2, callout 35]The AC701 board provides flexible GTP Quad 213 MGTREFCLK options through the use of external multiplexer (MUX) components U3 and U4 to service the GTP Quad 213 SFP, FMC, and SMA MGT interfaces.FPGA U1 MGT Bank 213 has two clock inputs, MGTREFCLK0 and MGTREFCLK1. Each clock input is driven by a series capacitor coupled clock sourced from a SY89544UMG 4-to-1 multiplexer.Each multiplexer has a clock source at three of its four inputs; the fourth input is not connected.The diagram for the GTP Quad 213 clock multiplexer circuit is shown in Figure 1-14.Table 1-9 lists the MGT sources for U3 and U4. See Table 1-10 and Table 1-11 for details.Figure 1-14: AC701 Board GTP 213 U3 and U4 MUX InputsTable 1-9: MGT Clock Multiplexer U3 and U4 Clock SourcesClock Name ReferenceDescription125 MHz clock generator U2ICS844021 Crystal-to-LVDS Clock Generator (ICS). See U3 IN0: 125 MHz Clock Generator .Jitter attenuated clock U24Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs). See U3/U4 IN1: Jitter Attenuated Clock .FMC HPC GBT CLK0and CLK1J30FMC_HPC_GBTCLK0_M2C_C_P/N at U3; FMC_HPC_GBTCLK1_M2C_C_P/N at U4; See U3/U4 IN2: FMC HPC GBT Clocks .GTP SMA REFCLK (differential pair)J25SMA_MGT_REFCLK_P (net name). See U4 IN0: GTP Transceiver SMA Clock Input .J26SMA_MGT_REFCLK_N (net name). See U4 IN0: GTP Transceiver SMA Clock Input .。

7Series FPGAs Data Sheet: Overview DS180 (v2.6) February 27, 2018Product SpecificationMax. Capability Spartan-7Artix-7Kintex-7Virtex-7Logic Cells102K215K478K1,955KBlock RAM(1) 4.2Mb13Mb34Mb68MbDSP Slices 1607401,9203,600DSP Performance(2)176 GMAC/s929GMAC/s2,845GMAC/s5,335GMAC/s MicroBlaze CPU(3)260 DMIPs303 DMIPs438 DMIPs441 DMIPs Transceivers–163296Transceiver Speed– 6.6Gb/s12.5Gb/s28.05Gb/sSerial Bandwidth–211Gb/s800Gb/s2,784Gb/sPCIe Interface–x4 Gen2x8 Gen2x8 Gen3Memory Interface800Mb/s1,066Mb/s1,866Mb/s1,866Mb/sI/O Pins400500500 1,200I/O Voltage 1.2V–3.3V 1.2V–3.3V 1.2V–3.3V 1.2V–3.3VPackage Options Low-Cost, Wire-Bond Low-Cost, Wire-Bond,Bare-Die Flip-Chip Bare-Die Flip-Chip and High-Performance Flip-ChipHighest PerformanceFlip-ChipNotes:1.Additional memory available in the form of distributed RAM.2.Peak DSP performance numbers are based on symmetrical filter implementation.3.Peak MicroBlaze CPU performance numbers based on microcontroller preset.I/O Electrical CharacteristicsSingle-ended outputs use a conventional CMOS push/pull output structure driving High towards V CCO or Low towards ground, and can be put into a high-Z state. The system designer can specify the slew rate and the output strength. The input is always active but is usually ignored while the output is active. Each pin can optionally have a weak pull-up or a weak pull-down resistor.Most signal pin pairs can be configured as differential input pairs or output pairs. Differential input pin pairs can optionally be terminated with a 100Ω internal resistor. All 7series devices support differential standards beyond LVDS: RSDS, BLVDS, differential SSTL, and differential HSTL.Each of the I/Os supports memory I/O standards, such as single-ended and differential HSTL as well as single-ended SSTL and differential SSTL. The SSTL I/O standard can support data rates of up to 1,866Mb/s for DDR3 interfacing applications. 3-State Digitally Controlled Impedance and Low Power I/O FeaturesThe 3-state Digitally Controlled Impedance (T_DCI) can control the output drive impedance (series termination) or can provide parallel termination of an input signal to V CCO or split (Thevenin) termination to V CCO/2. This allows users to eliminate off-chip termination for signals using T_DCI. In addition to board space savings, the termination automatically turns off when in output mode or when 3-stated, saving considerable power compared to off-chip termination. The I/Os also have low power modes for IBUF and IDELAY to provide further power savings, especially when used to implement memory interfaces.I/O LogicInput and Output DelayAll inputs and outputs can be configured as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and outputs. Any input and some outputs can be individually delayed by up to 32 increments of 78ps, 52ps, or 39ps each. Such delays are implemented as IDELAY and ODELAY. The number of delay steps can be set by configuration and can also be incremented or decremented while in use.LC tank or, in the case of the GTZ, a single LC tank architecture to allow the ideal blend of flexibility and performance while enabling IP portability across the family members. The different 7series family members offer different top-end data rates. The GTP operates up to 6.6Gb/s, the GTX operates up to 12.5Gb/s, the GTH operates up to 13.1Gb/s, and the GTZ operates up to 28.05Gb/s. Lower data rates can be achieved using FPGA logic-based oversampling. The serial transmitter and receiver are independent circuits that use an advanced PLL architecture to multiply the reference frequency input by certain programmable numbers up to 100 to become the bit-serial data clock. Each transceiver has a large number of user-definable features and parameters. All of these can be defined during device configuration, and many can also be modified during operation.TransmitterThe transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 16, 20, 32, 40, 64, or 80. Additionally, the GTZ transmitter supports up to 160 bit data widths. This allows the designer to trade-off datapath width for timing margin in high-performance designs. These transmitter outputs drive the PC board with a single-channel differential output signal. TXOUTCLK is the appropriately divided serial data clock and can be used directly to register the parallel data coming from the internal logic. The incoming parallel data is fed through an optional FIFO and has additional hardware support for the 8B/10B, 64B/66B, or 64B/67B encoding schemes to provide a sufficient number of transitions. The bit-serial output signal drives two package pins with differential signals. This output signal pair has programmable signal swing as well as programmable pre- and post-emphasis to compensate for PC board losses and other interconnect characteristics. For shorter channels, the swing can be reduced to reduce power consumption.ReceiverThe receiver is fundamentally a serial-to-parallel converter, changing the incoming bit-serial differential signal into a parallel stream of words, each 16, 20, 32, 40, 64, or 80 bits. Additionally, the GTZ receiver supports up to 160 bit data widths. This allows the FPGA designer to trade-off internal datapath width versus logic timing margin.The receiver takes the incoming differential data stream, feeds it through programmable linear and decision feedback equalizers (to compensate for PC board and other interconnect characteristics), and uses the reference clock input to initiate clock recognition. There is no need for a separate clock line. The data pattern uses non-return-to-zero (NRZ) encoding and optionally guarantees sufficient data transitions by using the selected encoding scheme. Parallel data is then transferred into the FPGA logic using the RXUSRCLK clock. For short channels, the transceivers offers a special low power mode (LPM) to reduce power consumption by approximately 30%.Out-of-Band SignalingThe transceivers provide out-of-band (OOB) signaling, often used to send low-speed signals from the transmitter to the receiver while high-speed serial data transmission is not active. This is typically done when the link is in a powered-down state or has not yet been initialized. This benefits PCI Express and SATA/SAS applications.Integrated Interface Blocks for PCI Express DesignsHighlights of the integrated blocks for PCI Express include:•Compliant to the PCI Express Base Specification 2.1 or 3.0 (depending of family) with Endpoint and Root Port capability•Supports Gen1 (2.5Gb/s), Gen2 (5Gb/s), and Gen3 (8Gb/s) depending on device family•Advanced configuration options, Advanced Error Reporting (AER), and End-to-End CRC (ECRC) Advanced Error Reporting and ECRC features•Multiple-function and single root I/O virtualization (SR-IOV) support enabled through soft-logic wrappers or embedded in the integrated block depending on familyAll Artix-7, Kintex-7, and Virtex-7 devices include at least one integrated block for PCI Express technology that can be configured as an Endpoint or Root Port, compliant to the PCI Express Base Specification Revision 2.1 or 3.0. The Root Port can be used to build the basis for a compatible Root Complex, to allow custom FPGA-to-FPGA communication via the PCI Express protocol, and to attach ASSP Endpoint devices, such as Ethernet Controllers or Fibre Channel HBAs, to the FPGA. This block is highly configurable to system design requirements and can operate 1, 2, 4, or 8 lanes at the 2.5 Gb/s, 5.0 Gb/s, and 8.0Gb/s data rates. For high-performance applications, advanced buffering techniques of the block offer a flexibleRevision HistoryThe following table shows the revision history for this document:Date Version Description of Revisions06/21/10 1.0Initial Xilinx release.07/30/10 1.1Added SHA-256 to authentication information. Updated Table5, Table7, Virtex-7 FPGA Device-Package Combinations and Maximum I/Os table (Virtex-7 T devices), and Table9 with ball pitchinformation and voltage bank information. Updated DSP and Logic Slice information in Table8.Updated Low-Power Gigabit Transceivers.09/24/10 1.2In General Description, updated 4.7TMACS DSP to 5.0TMACS DSP. In Table1, added Note 1;updated Peak DSP Performance for Kintex-7 and Virtex-7 families. In Table4, updated CMTinformation for XC7A175T and XC7A355T. In Table6, replaced XC7K120T with XC7K160T andreplaced XC7K230T with XC7K325T—and updated corresponding information. Also addedXC7K355T, XC7K420T, and XC7K480T. In Table7,replaced XC7K230T with XC7K325T. In Table8,updated XC7V450T Logic Cell, CLB, block RAM, and PCI information; updated XC7VX415T andXC7VX690T PCI information; updated XC7V1500T, and XC7V2000T block RAM information; andreplaced XC7VX605T with XC7VX575T, replaced XC7VX895T with XC7VX850T, and replacedXC7VX910T with XC7VX865T—and updated corresponding information. Updated Digital SignalProcessing — DSP Slice with operating speed of 640MHz.Removed specific transceiver type fromOut-of-Band Signaling. In Virtex-7 FPGA Device-Package Combinations and Maximum I/Os table(Virtex-7 T devices), replaced XC7VX605T with XC7VX575T and added table notes 2 and 3. InTable9, removed the FFG784 package for the XC7VX485T device; replaced XC7VX605T withXC7VX575T; replaced XC7VX895T with XC7VX850T; and replaced XC7VX910T with XC7VX865T.10/20/10 1.3In Table7, replaced XC7K120T with XC7K160T. Updated Digital Signal Processing — DSP Slice.11/17/10 1.4Updated maximum I/O bandwidth to 3.1 Tb/s in General Description. Updated Peak Transceiver Speedfor Virtex-7 FPGAs in Summary of 7Series FPGA Features and in Table1. Updated Peak DSPPerformance values in Table1 and Digital Signal Processing — DSP Slice. In Table7, updatedXC7K70T I/O information. In Table8, added XC7VH290T, XC7VH580T, and XC7VH870T devices andupdated total I/O banks information for the XC7V585T, XC7V855T, XC7V1500T, and XC7VX865Tdevices. In Table9, updated XC7VX415T, XC7VX485T, XC7VX690T, XC7VX850T, and XC7VX865Tdevice information. Added Table11. Updated Low-Power Gigabit Transceivers information, includingthe addition of the GTZ transceivers.02/22/11 1.5Updated Summary of 7Series FPGA Features and the Low-Power Gigabit Transceivers highlights andsection. In Table1, updated Kintex-7 FPGA, Artix-7 FPGA information. In Table4, updated XC7A175T.Also, updated XC7A355T.Added three Artix-7 FPGA packages to Table5: SBG325, SBG484, andFBG485, changed package from FGG784 to FBG784, and updated package information forXC7A175T and XC7A355T devices. In Table6, updated XC7K160T and added three devices:XC7K355T, XC7K420T, and XC7K480T. In Table7, updated XC7K70T package information and addedthree devices: XC7K355T, XC7K420T, and XC7K480T. In Table8, added note 1 (EasyPath FPGAs)and updated note 7 to include GTZ transceivers. In Virtex-7 FPGA Device-Package Combinations andMaximum I/Os table (Virtex-7 T devices), added two Virtex-7 FPGA packages: FHG1157 andFHG1761, and updated XC7V1500T (no FFG1157) and XC7V2000T (no FFG1761) packageinformation and removed the associated notes. Added CLBs, Slices, and LUTs. Updated Input/Output.Added EasyPath-7 FPGAs.03/28/11 1.6Updated G eneral Description, Summary of 7Series FPG A Features, Table1, Table4, Table5, Table6,Table7, Table8, Table9 (combined Virtex-7 T and XT devices in one table), and Table11. Updated theLow-Power Gigabit Transceivers highlights and section. Updated Block RAM, Integrated InterfaceBlocks for PCI Express Designs, Configuration, Encryption, Readback, and Partial Reconfiguration,XADC (Analog-to-Digital Converter), 7Series FPGA Ordering Information, and EasyPath-7 FPGAs.07/06/11 1.7Updated G eneral Description, Summary of 7Series FPG A Features, Table1, Table4, Table6, Table8,Table9 and Table11. Added Table10. Added Stacked Silicon Interconnect (SSI) Technology. UpdatedTransmitter, Configuration, and XADC (Analog-to-Digital Converter). Updated Figure1.09/13/11 1.8Updated General Description, Table1, Table4, Table5, Table8, CLBs, Slices, and LUTs,Configuration, and 7Series FPGA Ordering Information.01/15/12 1.9Updated General Description, Table1, Table4, Table5, Table6, Table7, Table8, Table10, Table11,Block RAM, Digital Signal Processing — DSP Slice, Low-Power Gigabit Transceivers, IntegratedInterface Blocks for PCI Express Designs, Configuration, EasyPath-7 FPGAs, and 7Series FPGAOrdering Information.。

Table 1-2 lists the 21 dedicated I/O pins.Serial Transceiver Channels by Device/PackageSpartan-7 FPGAs do not contain serial transceivers. Table 1-3 lists the quantity of GTP serial transceiver channels for the Artix-7 FPGAs.Table 1-2:7Series FPGAs I/O Pins in the Dedicated Configuration Bank (Bank0)DXP_0VCCBATT_0INIT_B_0M0_0TDO_0TDI_0GNDADC_0(1)DXN_0DONE_0VN_0M1_0TCK_0VREFN_0VCCADC_0(1)PROGRAM_B_0CCLK_0VP_0M2_0TMS_0VREFP_0CFGBVS_0Notes:1.In SSI technology devices, GNDADC and VCCADC do not have an _0 in the pin name.Table 1-3:Serial Transceiver Channels (GTPs) by Device/Package (Artix-7 FPGAs)DeviceGTP Channels by PackageCPG 236CPG 238CSG 324CSG 325FTG 256SBG SBV 484FGG 484FGG 676FBG FBV 484FBG FBV 676FFG FFV 1156RS 484RB 484RB 676XA7A12T –2–2––––––––––XC7A15T 2040–4–––––––XC7A25T –2–4–––––––––XC7A35T 2–040–4–––––––XC7A50T 2–040–4–––––––XC7A75T ––0–0–48––––––XC7A100T ––0–0–48––––––XC7A200T –––––4––4816–––XA7A12T –2–2––––––––––XA7A15T 2–040–4–––––––XA7A25T –2–4–––––––––XA7A35T 2–04––––––––––XA7A50T 2–04––––––––––XA7A75T ––0–––4–––––––XA7A100T ––0–––4–––––––XQ7A50T –––4––4–––––––XQ7A100T ––0–––4–––––––XQ7A200T–––––––––––448DeviceGTX Channels by PackageFBG484FBV484FBG676FBV676FBG900FBV900FFG676FFV676FFG900FFV900FFG901FFV901FFG1156FFV1156RF676RF900XC7K70T48–––––––XC7K160T48–8–––––XC7K325T–816816––––XC7K355T–––––24–––XC7K410T–816816––––XC7K420T–––––2832––XC7K480T–––––2832––XA7K160T–––8–––––XQ7K325T–––––––816 XQ7K410T–––––––816Device FFG1157FFG1761FLG1925FHG1761RF1157RF1761 XC7V585T2036––––XC7V2000T––1636––XQ7V585T––––2036Die Level Bank Numbering OverviewBanking and Clocking Summary•The center clocking backbone contains all vertical clock tracks and clock buffer connectivity.•The CMT backbone contains all vertical CMT connectivity and is located in the CMT column.•Not all banks are bonded out in every part/package combination.•GTP/GTX/GTH columns summary°One GT Quad=Four transceivers=Four GTPE2 or GTXE2 or GTHE2 primitives.°Not all GT Quads are bonded out in every package.•I/O banks summary°Each bank has four pairs of clock capable (CC) inputs for four differential or fourXC7A200T and XQ7A200T BanksFigure1-10 shows the I/O and transceiver banks.SBG484, SBV484, and RS484 Packages•HR I/O bank 13 is partially bonded out.•HR I/O banks 12, 32, 33, and 36 are not bonded out.•The GTP Quads 113, 116, and 213 are not bonded out.FBG484, FBV484, and RB484 Packages•HR I/O bank 13 is partially bonded out.•HR I/O banks 12, 32, 33, and 36 are not bonded out.•The GTP Quads 113, 116, and 213 are not bonded out.FBG676, FBV676, and RB676 Packages•HR I/O banks 32 and 36 are not bonded out.•The GTP Quads 113 and 116 are not bonded out.FFG1156 and FFV1156 Package (XC7A200T only)All HR I/O banks and the GTP Quads are fully bonded out in this package.Figure 1-10:XC7A200T and XQ7A200T Banks。

Getting Started with the ZC706 PCIe Targeted Reference DesignIntroductionThe Zynq®-7000 PCIe® Targeted Reference Design (TRD) expands the Zynq-7000 SoCZC702 Base Targeted Reference Design User Guide (UG925) [Ref3] by adding PCI Express® communication with a PCIe host system at PCIe x4 Gen2 speed. In the ZC702 Base TRD, the input of the video processing pipeline is generated by a test pattern generator in the FPGA logic. In this design, the input of the video processing pipeline is generated by anapplication on the PCIe host computer at 1080p60 resolution and transmitted to the ZC706 board through PCIe. The data is processed by video pipeline and passed back to the PCIe host system through PCIe. As the full 1080p60 video stream only takes up around 4Gb/s, an additional data generator and a checker are implemented and connected to channel 1 of PCIe DMA, showcasing the maximum PCIe x4 Gen2 bandwidth achieved by the hardware.The Zynq-7000 PCIe TRD demonstrates the following components working together:•PCIe Endpoint (x4 Gen2)•High speed serial transceivers•High speed multichannel DMA interfacing to PCIe Endpoint•Zynq-7000 Processing System (PS)•Video DMA (VDMA) and Sobel filtering•HDMI based display controller质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XC7Z045-1FBG676C的详细参数，仅供参考IntroductionFigure 3-1:Zynq-7000 PCIe TRD Block DiagramKey ComponentsHardware Test SetupProgramming the ZC706BoardProgramming the ZC706BoardThe XC7Z045 SoC is configured from a bitstream in a 2x128Mb Quad-SPI flash memory. This bitstream must first be loaded in the Quad-SPI flash memory from the SD card plugged into J30 on the ZC706board.Files for configuring the Zynq-7000 PCIe TRD are compiled in zc706_pcie_trd.bin which contains the zynq_fsbl.elf bitstream and u-boot.elf bitstream along with the Linux kernel, Linux file system image files, and Linux device tree binary files.Extracting the Project FilesThe Zynq-7000 PCIe Targeted Reference Design files are located inrdf0287-zc706-pcie-trd-2014-3.zip This file is available for download from the ZC706 Evaluation Kit Documentation webpage.To extract the files:1.Download rdf0287-zc706-pcie-trd-2014-3.zip to a working directory on thecontrol computer.2.Unzip the files contained in rdf0287-zc706-pcie-trd-2014-3.zip. Programming the SD CardOn the control computer:1.Plug the SD card into the SD card receptacle.2.Navigate to therdf0287-zc706-pcie-trd-2014-3/ready_to_test/prog_qspi directory and copy the entire content to the SD card.The BOOT.BIN file enables the PS to boot in the SD boot mode. Thezc706_pcie_trd.bin file contains the TRD bitstream. The remaining files arerequired for Linux boot-up.3.Unmount and remove the SD card from the computer and insert it into the SD cardreceptacle on the ZC706board (Figure3-2).。