VHDL源代码

第4 章用VHDL 程序实现常用逻辑电路4.1组合逻辑电路设计4.1.1基本逻辑门library ieee;use iee.std_logic_1164.all;entity jbm isport(a,b: in bit;f1,f2,f3,f4,f5,f: out bit);end jbm;architecture a of jbm isbeginf1<=a and b; --构成与门f2<=a or b; --构成或门f<=not a; --构成非门f3<=a nand b; --构成与非门f4<=a nor b; --构成异或门f5<=not(axor b); --构成异或非门即同门end;4.1.2三态门library ieee;use ieee.std_logic_1164.all;entity tri_s isport(enable: in std_logic;datain: in std_logic_vector(7 downto 0);dataout: out std_logic_vector(7 downto0));end tri_s;architecture bhv of tri_s isbeginprocess(enable,datain)beginif enable='1' thendataout<=datain;elsedataout<="ZZZZZZZZ";end if;end process;end bhv;4.1.33-8 译码器library ieee;use ieee.std_logic_1164.all;entity decoder3_8 isport(a,b,c,g1,g2a,g2b: in std_logic;y: out std_logic_vector(7 downto 0));end decoder3_8;architecture a of decoder3_8 issignal dz:std_logic_vector(2 downto 0);begindz<=c&b&a;process (dz,g1,g2a,g2b)beginif(g1='1'and g2a='0'and g2b='0')thencase dz iswhen "111"=> y<="01111111";when others=>y<="XXXXXXXX";end case;elseend if;end process;4.1.4优先编码器library ieee;use ieee.std_logic_1164.allentity coder isport(din: in std_logic_vector(0 to 7);output: out std_logic_vector(0 to 2));end coder;architecture behave of coder issignal sint: std_logic_vevtor(4 downto 0);beginprocess(din)beginif (din(7)='0') thenoutput <= "000" ;elsif (din(6)='0') thenoutput <= "100" ;elsif (din(5)='0') thenoutput <= "010" ;elsif (din(4)='0') thenoutput <= "110" ;elsif (din(3)='0') thenoutput <= "001" ;elsif (din(2)='0') thenoutput <= "101" ;elsif (din(1)='0') thenoutput <= "011" ;elseoutput <= "111" ;end if;end process;end behav;4.1.57 段码译码器library ieee;use ieee.std_logic_1164.allentity decl7s isport (a: in std_logic_vector (3 downto 0);led7s: out std_logic_vector(6 downto 0));end decl7s;architecture behave of decl7s isbeginprocess(a)begincase a iswhen "0000" => led7s <= "0111111" ;when "0001" => led7s <= "0000110" ;when "0010" => led7s <= "1011011" ;when "0011" => led7s <= "1001111" ;when "0100" => led7s <= "1100110" ;when "0101" => led7s <= "1101101" ;when "0110" => led7s <= "1111101" ;when "0111" => led7s <= "0000111" ;when "1000" => led7s <= "1111111" ;when "1001" => led7s <= "1101111" ;when "1010" => led7s <= "1110111" ;when "1011" => led7s <= "1111100" ;when "1100" => led7s <= "0111001" ;when "1101" => led7s <= "1011110" ;when "1110" => led7s <= "1111001" ;when "1111" => led7s <= "1110001" ;when others => null;end case;end process;end behave;4.1.6二-十进制BCD 译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity bcdymq isport(din : in integer range 15 downto 0;a,b : out integer range 9 downto 0);end;architecture fpq1 of bcdymq isbeginp1: process(din)beginif din<10 thena< =din;b< =0;elsea< =din-10;b< =1;end if;end process p1;end;4.1.7多位加（减）法器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity jianfaqi isport(a,b : in std_logic_vector(0 to 3);c0: in std_logic;c1: out std_logic;d : out std_logic_vector(0 to 3));end;architecture a of jianfaqi isbeginprocessbeginif a>b+c0 thend<=a-(b+c0);c1<='0';elsec1<='1';d<=("10000")-(b+c0-a);end if;end process ;end ;4.2时序逻辑电路设计4.2.1触发器RS 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity rsff isport(r,s,clk:in std_logic;q,qb:buffer std_logic);end rsff;architecture rsff_art of rsff issignal q_s,qb_s:std_logic;beginprocess(clk,r,s)beginif (clk'event and clk='1') thenif (s='1' and r='0') thenq_s<='0' ;qb_s<='1' ;elsif (s='0' and r='1') thenq_s <= '1' ;qb_s <= '0' ;elsif (s='0' and r='0') thenq_s <= q_s;qb_s <= qb_s;end if;end if;q_s <= q_s;qb_s <= qb_s;end process;end rsff_art;同步复位D 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity syndff isport(d,clk,reset:in std_logic;q,qb:out std_logic);end syndff;architecture dff_art of syndff isbeginprocess(clk)beginif (clk'event and clk='1') thenif (reset='0') thenq<='0';qb<='1';elseq<=d;qb<=not q;end if;end if;end process;end dff_art;JK 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity asynjkff isport(j,k,clk,set.reset:in std_logic;q,qb:out std_logic);end asynjkff;architecture jkff_art of asynjkff issingal q_s,qb_s:std_logic;beginprocess(clk,set,reset)beginif (set='0' and reset='1' ) thenq_s<='1';qb_s<='0';elsif (set='1' and reset='0' ) thenq_s<='0';qb_s<='1';elsif (clk'event and clk='1') thenif (j='0' and k='1' ) thenq_s<='0';qb_s<='1';elsif (j='1' and k='0' ) thenq_s<='1';qb_s<='0';elsif (j='1' and k='1' ) thenq_s<=not q_s;qb_s<=not qb_s;end if;end if;q<= q_s;qb<= qb_s;end process;end jkff_art;T 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity tff isport(t,clk: in std_logic;q: out std_logic);end;architecture tff_art of tff issignal q_temp: std_logic;beginp1:process(clk)beginif rising_edge(clk) thenif t='1' then --当T=1 时T 触发器具有2 分频的功能q_temp<=not q_temp;elseq_temp<=q_temp;end if;end if;q<=q_temp;end process;q<=q_temp;end tff_art;4.2.2计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 ISport( clk: in std_logic;q: out std_logic_vector(3 downto 0));end cnt4;architecture behave of cnt4 issignal q1: std_logic_vector(3 downto 0);beginprocess(clk)beginif (clk'event and clk = '1') thenq1<=q1+1;end if;end process;q<=q1;end behave;一般计数器设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 isport( clk,rst,en,updown: in std_logic;cq: out std_logic_vector(3 downto 0));end cnt10;architecture behave of cnt10 isbeginprocess(clk,rst,en,updown)variable cqi:std_logic_vector(3 downto 0);beginif rst='1' thencqi:=(others=>'0'); --计数器异步复位elsif (clk'event and clk = '1') then --检测时钟上升沿if en='1'then --检测是否允许计数（同步使能）if updown='0'thenif cqi<9 thencqi:=cqi+1; --允许计数,检测是否小于9elsecqi:=(others=>'0'); --大于9，计数值清零end if;elseif cqi>0 thencqi:=cqi-1; --检测是否大于0elsecqi:=(others=>'1'); ---否则，计数值置1end if;end if;end if;end if;cq<=cqi; --将计数值向端口输出end process;end behave;4.2.3分频器library ieee;use std_logic_1164.all;use std_logic_unsigned.all;entity freq1 isport(clk: in std_logic;d: in std_logic_vector(7 downto 0);fout: out std_logic);end;architecture one of dvf issignal full: std_logic;beginp_reg:process(clk)variable cnt8: std_logic_vector(7 downto 0);beginif clk'event and clk='1'then --检测时钟上升沿if cnt8='''' thencnt8:=d; --当CNT8 计数计满时，输入数据D 被同步预置给计数器CNT8full<='1'; --同时使溢出标志信号FULL 输出为高电平elsecnt8:=cnt8+1; --否则继续作加1 计数full<='0'; --且输出溢出标志信号FULL 为低电平end if;end if;end process p_reg;p_div:process(full)variable cnt2: std_logic;beginif full'event and full='1' thencnt2:=not cnt2; --如果溢出标志信号FULL 为高电平，T 触发器输出取反if cnt2='1'thenfout<='1';elsefout<='0';end if;end if;end process p_div;end;4.2.4移位寄存器library ieee;use ieee.std_logic_1164.all;entity shift isport(clk,c0: in std_logic; --时钟和进位输入md: in std_logic_vector(2 downto 0); --移位模式控制字d:in std_logic_vector(7 downto 0); --待加载移位的数据qb:out std_logic_vector(7 downto 0); --移位数据输出cn: outstd_logic); --进位输出end;architecture behave of shift issignal reg: std_logic_vector(7 downto 0);signal cy: std_logic;beginprocess(clk,md,c0)beginif clk'event and clk='1' thencase md iswhen "001" => reg (0) <= c0 ;reg (7 downto 1) <= reg (6 downto 0);cy <= reg (7); --带进位循环左移when "010" => reg (0) <= reg (7);reg (7 downto 1) <= reg (6 downto 0); --自循环左移when "011" => reg (7) <= reg (0);reg (6 downto 0) <= reg (7 downto 1); --自循环右移when "100" => reg (7) <= C0 ;reg (6 downto 0) <= reg (7 downto 1);cy <= reg (0); --带进位循环右移when "101" => reg (7 downto 0) <= d(7 downto 0); --加载待移数when others => reg<= reg ; cy<= cy ; --保持end case;end if;end process;qb(7 downto 0) <= reg (7 downto 0); cn <= cy; --移位后输出end behav;4.3状态机逻辑电路设计4.3.1一般状态机设计library ieee;use ieee.std_logic_1164.all;entity s_machine isport ( clk,reset : in std_logic;state_inputs : in std_logic_vector(0 to1);comb_outputs : out integer range 0 to 15 );end s_machine;architecture behv of s_machine istype fsm_st is (s0, s1, s2, s3); --数据类型定义，状态符号化signal current_state, next_state: fsm_st; --将现态和次态定义为新的数据类型beginreg: process(reset,clk) --主控时序进程beginif reset = '1' thencurrent_state <= s0; --检测异步复位信号elsif clk='1' and clk'event thencurrent_state <= next_state;end if;end process;com:process(current_state, state_inputs) --主控组合进程begincase current_state iswhen s0 => comb_outputs<= 5;if state_inputs = "00" thennext_state<=s0;elsenext_state<=s1;end if;when s1 => comb_outputs<= 8;if state_inputs = "00" thennext_state<=s1;elsenext_state<=s2;end if;when s2 => comb_outputs<= 12;if state_inputs = "11" thennext_state <= s0;elsenext_state <= s3;end if;when s3 => comb_outputs <= 14;if state_inputs = "11" thennext_state <= s3;elsenext_state <= s0;end if;end case;end process;end behv;4.3.2状态机的应用library ieee;use ieee.std_logic_1164.all;entity asm_led isport(clk,clr : in std_logic;led1,led2,led3:out std_logic);end;architecture a of asm_led istype states is (s0,s1,s2,s3,s4,s5); --对状态机的状态声明signal q: std_logic_vector( 0 to 2);signal state : states;beginp1: process(clk,clr)beginif(clr='0')thenstate<=s0;elsif (clk'event and clk='1') thencase state iswhen s0=> state <=s1;when s1=> state <=s2;when s2=> state <=s3;when s3=> state <=s4;when s4=> state <=s5;when s5=> state <=s0;when others => state<=s0;end case;end if;end process p1;p2: process (clr,state)beginif(clr='0') thenled1<='0';led2<='0';led3<='0';elsecase state iswhen s0=> led1<='1';led2<='0';led3<='0';when s1=> led1<='0';led2<='1';led3<='0';when s2=> led1<='0';led2<='1';led3<='0';when s3=> led1<='0';led2<='0';led3<='1';when s4=> led1<='0';led2<='0';led3<='1';when s5=> led1<='0';led2<='0';led3<='1';when others => null;end case;end if;end process p2;end ;第6 章EDA 仿真技术应用实例6.1 带使能和片选端的16：4 线优先编码器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity pencoder isport(d:in std_logic_vector(7 downto 0);ei:in std_logic; --ei:enable inputgs,eo:out bit; --gs:chip select output;eo:enable outputq2,q1,q0:out std_logic);end pencoder;architecture encoder of pencoder isbeginprocess(d)beginif(d(0)='0' and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(1)='0' and ei='0')thenq2<='1';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(2)='0' and ei='0')thenq2<='1';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(3)='0' and ei='0')thenq2<='1';q1<='0';q0<='0';gs<='0';eo<='1';elsif(d(4)='0' and ei='0')thenq2<='0';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(5)='0' and ei='0')thenq2<='0';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(6)='0' and ei='0')thenq2<='0';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(7)='0' and ei='0')then --d7 prioty encoderq2<='0';q1<='0';q0<='0';gs<='0';eo<='1';elsif(ei='1')thenq2<='1';q1<='0';q0<='1';gs<='1';eo<='1';'0')thenq2<='1';q1<='1';q0<='1';gs<='1';eo<='0';end if;end process;end encoder;6.27 段显示译码器设计译码器设计源代码：library ieee;use ieee.std_logic_1164.all;entity decoder47 isport(lt,ibr,ib_ybr:in bit;a: in std_logic_vector(3 downto 0);y:out std_logic_vector(6 downto 0));end decoder47;architecture art of decoder47 isbeginprocess(lt,ibr,ib_ybr,a)variable s: std_logic_vector(3 downto 0);begins:=a(3)&a(2)&a(1)&a(0);if lt='0' and ib_ybr='1' theny<="1111111"; --检查七段显示管是否正常elsif ibr='0' and a="0000" theny<="0000000";elsecase s iswhen"0000"=>y<="1111110"; --7Ewhen"0001"=>y<="0110000"; --30when"0010"=>y<="1101101"; --6Dwhen"0011"=>y<="1111001"; --79when"0100"=>y<="0110011"; --33when"0101"=>y<="1011011"; --5Bwhen"0110"=>y<="0011111"; --5Fwhen"0111"=>y<="1110000"; --70when"1000"=>y<="1111111"; --7Ewhen"1001"=>y<="1110011"; --7Bwhen"1010"=>y<="0001101"; --0Dwhen"1011"=>y<="0011001"; --19when"1100"=>y<="0100011"; --23when"1101"=>y<="1001011"; --4Bwhen"1110"=>y<="0001111"; --0Fwhen"1111"=>y<="0000000";end case;end if;end process;end art;6.3带异步清零端的12 位二进制全加器设计子模块源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end adder4b;architecture art of adder4b issignal sint:std_logic_vector(4 downto 0);signal aa,bb:std_logic_vector(4 downto 0);beginprocess(clr)beginif clr='1'thensint<="00000";elseaa<='0'&a;bb<='0'&b;sint<=aa+bb+cin;end if;s<=sint(3 downto 0);cout<=sint(4);end process;end art;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder12b isport(clr,cin: in std_logic;a,b: in std_logic_vector(11 downto 0);s: out std_logic_vector(11 downto 0);cout:out std_logic);end adder12b;architecture art of adder12b iscomponent adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end component;signal carry_out1:std_logic;signal carry_out2:std_logic;beginu1:adder4b port map(clr=>clr,cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),s=>s(3 downto 0),cout=>carry_out1);u2:adder4b port map(clr=>clr,cin=>carry_out1,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>carry_out2);u3:adder4b port map(clr=>clr,cin=>carry_out2,a=>a(11 downto 8),b=>b(11 downto 8),s=>s(11 downto 8),cout=>cout);end art;6.4带异步清零/置位端的JK 触发器设计带异步清零/置位端的JK 触发器源程序如下：library ieee;use ieee.std_logic_1164.all;entity jkff_logic isport(j,k,clk,clr,set:in std_logic;q:out std_logic);end jkff_logic;architecture art of jkff_logic issignal q_s:std_logic;beginprocess(clk,clr,set,j,k)beginif set='0' thenq_s<='1'; --异步置位elsif clr='1' thenq<='0'; --异步复位elsif clk'event and clk='1' thenif (j='0') and (k='1') thenq_s<='0';elsif(j='1') and (k='0') thenq_s<='1';elsif(j='1') and (k='1') thenq_s<=not q_s;end if;end if;q<=q_s;end process;end art;6.5 4 位锁存器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity latch1b isport(d: in std_logic;ena: in std_logic; --使能端q: out std_logic);end latch1b;architecture art of latch1b isbeginprocess(d,ena)beginif ena='1' thenq<=d;end if;end process;end art;元件声明程序包设计源代码：library ieee;use ieee.std_logic_1164.all;package my_package iscomponent latch1port(d:in std_logic;ena:in std_logic;q: out std_logic);end component;end;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use work.my_package.all; --使用用户自定义的程序包entity latch4d isport(d: in std_logic_vector(3 downto 0);oen: in bit;q:out std_logic_vector(3 downto 0));end latch4d;architecture one of latch4d issignal sig_save:std_logic_vector(3 downto 0);begingetlatch:for n in 0 to 3 generate --用for_generate 语句循环例化4 个1 位锁存器latchx:latch1 port map(d(n),g,sig_save(n)); --关联end generate;q<=sig_save when oen='0'else"ZZZZ";end one;6.632 进制多样型计数器设计（1）32 进制同步加法计数器源程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_plus isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_plus issignal d0,d1:std_logic_vector(3 downto 0); --d0 代表个位，d1 代表十位beginprocess(clk,clr,)beginif clr='1'thend1<=(others=>'0');d0<="0000"; --同步清零elsif clk'event and clk='1' thenif(d1=3 and d0=1)thend1<="0000";d0<="0000"; --计数到32 时清零elsif(d0=1) thend0<="0000";d1<=d1+1;elsed0<=d0+1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（2）32 进制同步减法计数器源程序32 进制同步减法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_sub isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_sub issignal d0,d1:std_logic_vector(3 downto 0); --d0 代表个位，d1 代表十位beginprocess(clk,clr)beginif clr='1' thend1<="0000";d0<="0000"; --异步清零elsif clk'event and clk='1' thenif(d1=0 and d0=0) thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;32 进制同步可逆计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_reversible isport(clk,clr,s:in std_logic; --s=1 加法计数，s=0 减法计数dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_reversible issignal d0,d1:std_logic_vector(3 downto 0); --d0 代表个位，d1 代表十位beginprocess(clk,clr,s)beginif clr='1'thend1<="0000";d0<="0000"; --异步清零elsif (clk'event and clk='1' )thenif s='1' thenif(d1=3 and d0=1) thend1<="0000";d0<="0000"; --计数到31 时清零elsif(d0=1) thend0<="0000";d1<=d1+1;else d0<=d0+1;end if;elsif s='0' thenif(d1=0 and d0=0)thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（4）32 进制异步加法计数器源程序32 进制异步加法计数器源程序如下：①子模块D 触发器源程序设计。

将8421BCD转换为余3码源代码：Library ieee;Use ieee.std_logic_1164.all;Entity bcd isPort(a:in std_logic_vector(3 downto 0);y:out std_logic_vector(3 downto 0));End;Architecture rtl of bcd isBeginProcess(a)BeginCase a isWhen"0000"=>y<="0011";When"0001"=>y<="0100";When"0010"=>y<="0101";When"0011"=>y<="0110";When"0100"=>y<="0111";When"0101"=>y<="1000";When"0110"=>y<="1001";When"0111"=>y<="1010";When"1000"=>y<="1011";When"1001"=>y<="1100";When others=>y<="ZZZZ";End case;End process;End;仿真图形：（仿真结果均有延时，大约20ns）四输入表决器源代码：Library ieee;Use ieee.std_logic_1164.all;Entity bjq isPort(i:in std_logic_vector(3 downto 0);f:out std_logic);End;Architecture nm2 of bjq isBeginProcess(i)Begincase i isWhen"0000"=>f<='0';When"0001"=>f<='0';When"0010"=>f<='0';When"0011"=>f<='0';When"0100"=>f<='0';When"0101"=>f<='0';When"0110"=>f<='0';When"0111"=>f<='1';When"1000"=>f<='0';When"1001"=>f<='0';When"1010"=>f<='0';When"1011"=>f<='1';When"1100"=>f<='0';When"1101"=>f<='1';When"1110"=>f<='1';When"1111"=>f<='1';When others=>f<='Z';End case;End process;End;仿真图形：2位二进制相乘电路源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity multi isport(A,B:in std_logic_vector(1 downto 0);F:out std_logic_vector(3 downto 0));end;architecture bhv of multi isbeginprocess(A,B)beginif(A="01" and B="01" )thenF<="0001";elsif(A="01" and B="10")thenF<="0010";elsif(A="01" and B="11")thenF<="0011";elsif(A="10" and B="01")thenF<="0010";elsif(A="10" and B="10")thenF<="0100";elsif(A="10" and B="11")thenF<="0110";elsif(A="11" and B="01")thenF<="0011";elsif(A="11" and B="10")thenF<="0110";elsif(A="11" and B="11")thenF<="1001";elseF<="0000";end if;end process;end;仿真图形：一位二进制全减器源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity subtracter isport(A,B,Ci:in std_logic;F,Co:out std_logic);end;architecture bhv of subtracter isbeginprocess(A,B,Ci)beginif(A='0' and B='0' and Ci='0')thenF<='0';Co<='0';elsif(A='0' and B='0' and Ci='1')thenF<='1';Co<='1';elsif(A='0' and B='1' and Ci='0')thenF<='1';Co<='1';elsif(A='0' and B='1' and Ci='1')thenF<='0';Co<='1';elsif(A='1' and B='0' and Ci='0')thenF<='1';Co<='0';elsif(A='1' and B='0' and Ci='1')thenF<='0';Co<='0';elsif(A='1' and B='1' and Ci='0')thenF<='0';Co<='0';elseF<='1';Co<='1';end if;end process;end;仿真图形：开关控制电路源代码：Library ieee;Use ieee.std_logic_1164.all;Entity switch_control isPort(a,b,c:in std_logic;y:out std_logic);End;Architecture nm5 of switch_control isBeginProcess(a,b,c);V ariable comb:std_logic_vector(2 downto 0);BeginComb:=a&b&c;Case comb isWhen"000"=>y<='0';When"001"=>y<='1';When"011"=>y<='0';When"010"=>y<='1';When"110"=>y<='0';When"111"=>y<='1';When"101"=>y<='0';When"100"=>y<='1';When others=>y<='X';End case;End process;End;仿真图形：。

第4章用VHDL程序实现常用逻辑电路4.1 组合逻辑电路设计4.1.1 基本逻辑门library ieee;use iee.std_logic_1164.all;entity jbm isport(a,b: in bit;f1,f2,f3,f4,f5,f: out bit);end jbm;architecture a of jbm isbeginf1<=a and b; --构成与门f2<=a or b; --构成或门f<=not a; --构成非门f3<=a nand b; --构成与非门f4<=a nor b; --构成异或门f5<=not(a xor b); --构成异或非门即同门end;4.1.2 三态门library ieee;use ieee.std_logic_1164.all;entity tri_s isport(enable: in std_logic;datain: in std_logic_vector(7 downto 0);dataout: out std_logic_vector(7 downto0));end tri_s;architecture bhv of tri_s isbeginprocess(enable,datain)beginif enable='1' thendataout<=datain;elsedataout<="ZZZZZZZZ";end if;end process;end bhv;4.1.3 3-8译码器library ieee;use ieee.std_logic_1164.all;entity decoder3_8 isport(a,b,c,g1,g2a,g2b: in std_logic;y: out std_logic_vector(7 downto 0));end decoder3_8;architecture a of decoder3_8 issignal dz:std_logic_vector(2 downto 0);begindz<=c&b&a;process (dz,g1,g2a,g2b)beginif(g1='1'and g2a='0'and g2b='0')thencase dz iswhen "000"=> y<="11111110";when "001"=> y<="11111101";when "010"=> y<="11111011";when "011"=> y<="11110111";when "100"=> y<="11101111";when "101"=> y<="11011111";when "110"=> y<="10111111";when "111"=> y<="01111111";when others=>y<="XXXXXXXX";end case;elsey<="11111111";end if;end process;4.1.4 优先编码器library ieee;use ieee.std_logic_1164.allentity coder isport(din: in std_logic_vector(0 to 7);output: out std_logic_vector(0 to 2));end coder;architecture behave of coder issignal sint: std_logic_vevtor(4 downto 0);beginprocess(din)beginif (din(7)='0') thenoutput <= "000" ;elsif (din(6)='0') thenoutput <= "100" ;elsif (din(5)='0') thenoutput <= "010" ;elsif (din(4)='0') thenoutput <= "110" ;elsif (din(3)='0') thenoutput <= "001" ;elsif (din(2)='0') thenoutput <= "101" ;elsif (din(1)='0') thenoutput <= "011" ;elseoutput <= "111" ;end if;end process;end behav;4.1.5 7段码译码器library ieee;use ieee.std_logic_1164.allentity decl7s isport (a: in std_logic_vector (3 downto 0);led7s: out std_logic_vector(6 downto 0));end decl7s;architecture behave of decl7s isbeginprocess(a)begincase a iswhen "0000" => led7s <= "0111111" ;when "0001" => led7s <= "0000110" ;when "0010" => led7s <= "1011011" ;when "0011" => led7s <= "1001111" ;when "0100" => led7s <= "1100110" ;when "0101" => led7s <= "1101101" ;when "0110" => led7s <= "1111101" ;when "0111" => led7s <= "0000111" ;when "1000" => led7s <= "1111111" ;when "1001" => led7s <= "1101111" ;when "1010" => led7s <= "1110111" ;when "1011" => led7s <= "1111100" ;when "1100" => led7s <= "0111001" ;when "1101" => led7s <= "1011110" ;when "1110" => led7s <= "1111001" ;when "1111" => led7s <= "1110001" ;when others => null;end case;end process;end behave;4.1.6二-十进制BCD译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity bcdymq isport(din : in integer range 15 downto 0;a,b : out integer range 9 downto 0);end;architecture fpq1 of bcdymq isbeginp1: process(din)beginif din<10 thena< =din;b< =0;elsea< =din-10;end if;end process p1;end;4.1.7 多位加（减）法器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity jianfaqi isport(a,b : in std_logic_vector(0 to 3);c0: in std_logic;c1: out std_logic;d : out std_logic_vector(0 to 3));end;architecture a of jianfaqi isbeginprocessbeginif a>b+c0 thend<=a-(b+c0);c1<='0';elsec1<='1';d<=("10000")-(b+c0-a);end if;end process ;end ;4.2 时序逻辑电路设计4.2.1 触发器RS触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity rsff isport(r,s,clk:in std_logic;q,qb:buffer std_logic);end rsff;architecture rsff_art of rsff issignal q_s,qb_s:std_logic;beginprocess(clk,r,s)beginif (clk'event and clk='1') thenif (s='1' and r='0') thenq_s<='0' ;qb_s<='1' ;elsif (s='0' and r='1') thenq_s <= '1' ;qb_s <= '0' ;elsif (s='0' and r='0') thenq_s <= q_s;qb_s <= qb_s;end if;q_s <= q_s;qb_s <= qb_s;end process;end rsff_art;同步复位D触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity syndff isport(d,clk,reset:in std_logic;q,qb:out std_logic);end syndff;architecture dff_art of syndff isbeginprocess(clk)beginif (clk'event and clk='1') thenif (reset='0') thenq<='0';qb<='1';elseq<=d;qb<=not q;end if;end if;end process;end dff_art;JK触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity asynjkff isport(j,k,clk,set.reset:in std_logic;q,qb:out std_logic);end asynjkff;architecture jkff_art of asynjkff issingal q_s,qb_s:std_logic;beginprocess(clk,set,reset)beginif (set='0' and reset='1' ) thenq_s<='1';qb_s<='0';elsif (set='1' and reset='0' ) thenq_s<='0';qb_s<='1';elsif (clk'event and clk='1') thenif (j='0' and k='1' ) thenq_s<='0';qb_s<='1';elsif (j='1' and k='0' ) thenq_s<='1';qb_s<='0';elsif (j='1' and k='1' ) thenq_s<=not q_s;qb_s<=not qb_s;end if;end if;q<= q_s;qb<= qb_s;end process;end jkff_art;T触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity tff isport(t,clk: in std_logic;q: out std_logic);end;architecture tff_art of tff issignal q_temp: std_logic;beginp1:process(clk)beginif rising_edge(clk) thenif t='1' then --当T=1时T触发器具有2分频的功能q_temp<=not q_temp;elseq_temp<=q_temp;end if;end if;q<=q_temp;end process;q<=q_temp;end tff_art;4.2.2计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 ISport( clk: in std_logic;q: out std_logic_vector(3 downto 0));end cnt4;architecture behave of cnt4 issignal q1: std_logic_vector(3 downto 0);beginprocess(clk)beginif (clk'event and clk = '1') thenq1<=q1+1;end if;end process;q<=q1;一般计数器设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 isport( clk,rst,en,updown: in std_logic;cq: out std_logic_vector(3 downto 0));end cnt10;architecture behave of cnt10 isbeginprocess(clk,rst,en,updown)variable cqi:std_logic_vector(3 downto 0);beginif rst='1' thencqi:=(others=>'0'); --计数器异步复位elsif (clk'event and clk = '1') then --检测时钟上升沿if en='1'then --检测是否允许计数（同步使能）if updown='0'thenif cqi<9 thencqi:=cqi+1; --允许计数,检测是否小于9elsecqi:=(others=>'0'); --大于9，计数值清零end if;elseif cqi>0 thencqi:=cqi-1; --检测是否大于0elsecqi:=(others=>'1'); ---否则，计数值置1end if;end if;end if;end if;cq<=cqi; --将计数值向端口输出end process;end behave;4.2.3 分频器library ieee;use std_logic_1164.all;use std_logic_unsigned.all;entity freq1 isport(clk: in std_logic;d: in std_logic_vector(7 downto 0);fout: out std_logic);end;architecture one of dvf issignal full: std_logic;beginp_reg:process(clk)variable cnt8: std_logic_vector(7 downto 0);if clk'event and clk='1'then --检测时钟上升沿if cnt8=''11111111'' thencnt8:=d; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8full<='1';--同时使溢出标志信号FULL输出为高电平elsecnt8:=cnt8+1;--否则继续作加1计数full<='0'; --且输出溢出标志信号FULL为低电平end if;end if;end process p_reg;p_div:process(full)variable cnt2: std_logic;beginif full'event and full='1' thencnt2:=not cnt2; --如果溢出标志信号FULL为高电平，T触发器输出取反if cnt2='1'thenfout<='1';elsefout<='0';end if;end if;end process p_div;end;4.2.4 移位寄存器library ieee;use ieee.std_logic_1164.all;entity shift isport(clk,c0: in std_logic;--时钟和进位输入md: in std_logic_vector(2 downto 0);--移位模式控制字d: in std_logic_vector(7 downto 0);--待加载移位的数据qb: out std_logic_vector(7 downto 0);--移位数据输出cn: out std_logic);--进位输出end;architecture behave of shift issignal reg: std_logic_vector(7 downto 0);signal cy: std_logic;beginprocess(clk,md,c0)beginif clk'event and clk='1' thencase md iswhen "001" => reg (0) <= c0 ;reg (7 downto 1) <= reg (6 downto 0);cy <= reg (7); --带进位循环左移when "010" => reg (0) <= reg (7);reg (7 downto 1) <= reg (6 downto 0); --自循环左移when "011" => reg (7) <= reg (0);reg (6 downto 0) <= reg (7 downto 1); --自循环右移when "100" => reg (7) <= C0 ;reg (6 downto 0) <= reg (7 downto 1);cy <= reg (0); --带进位循环右移when "101" => reg (7 downto 0) <= d(7 downto 0); --加载待移数when others => reg<= reg ; cy<= cy ; --保持end case;end if;end process;qb(7 downto 0) <= reg (7 downto 0); cn <= cy; --移位后输出end behav;4.3 状态机逻辑电路设计4.3.1 一般状态机设计library ieee;use ieee.std_logic_1164.all;entity s_machine isport ( clk,reset : in std_logic;state_inputs : in std_logic_vector(0 to1);comb_outputs : out integer range 0 to 15 );end s_machine;architecture behv of s_machine istype fsm_st is (s0, s1, s2, s3); --数据类型定义，状态符号化signal current_state, next_state: fsm_st; --将现态和次态定义为新的数据类型beginreg: process(reset,clk) --主控时序进程beginif reset = '1' thencurrent_state <= s0; --检测异步复位信号elsif clk='1' and clk'event thencurrent_state <= next_state;end if;end process;com:process(current_state, state_inputs) --主控组合进程begincase current_state iswhen s0 => comb_outputs<= 5;if state_inputs = "00" thennext_state<=s0;elsenext_state<=s1;end if;when s1 => comb_outputs<= 8;if state_inputs = "00" thennext_state<=s1;elsenext_state<=s2;end if;when s2 => comb_outputs<= 12;if state_inputs = "11" thennext_state <= s0;elsenext_state <= s3;end if;when s3 => comb_outputs <= 14;if state_inputs = "11" thennext_state <= s3;elsenext_state <= s0;end if;end case;end process;end behv;4.3.2状态机的应用library ieee;use ieee.std_logic_1164.all;entity asm_led isport(clk,clr : in std_logic;led1,led2,led3:out std_logic);end;architecture a of asm_led istype states is (s0,s1,s2,s3,s4,s5); --对状态机的状态声明signal q: std_logic_vector( 0 to 2);signal state : states;beginp1: process(clk,clr)beginif(clr='0')thenstate<=s0;elsif (clk'event and clk='1') thencase state iswhen s0=> state <=s1;when s1=> state <=s2;when s2=> state <=s3;when s3=> state <=s4;when s4=> state <=s5;when s5=> state <=s0;when others => state<=s0;end case;end if;end process p1;p2: process (clr,state)beginif(clr='0') thenled1<='0';led2<='0';led3<='0';elsecase state iswhen s0=> led1<='1';led2<='0';led3<='0';when s1=> led1<='0';led2<='1';led3<='0';when s2=> led1<='0';led2<='1';led3<='0';when s3=> led1<='0';led2<='0';led3<='1';when s4=> led1<='0';led2<='0';led3<='1';when s5=> led1<='0';led2<='0';led3<='1';when others => null;end case;end if;end process p2;end ;第6章EDA仿真技术应用实例6.1带使能和片选端的16：4线优先编码器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity pencoder isport(d:in std_logic_vector(7 downto 0);ei:in std_logic; --ei:enable inputgs,eo:out bit; --gs:chip select output;eo:enable outputq2,q1,q0:out std_logic);end pencoder;architecture encoder of pencoder isbeginprocess(d)beginif(d(0)='0' and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(1)='0' and ei='0')thenq2<='1';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(2)='0' and ei='0')thenq2<='1';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(3)='0' and ei='0')thenq2<='1';q1<='0';q0<='0';gs<='0';eo<='1';elsif(d(4)='0' and ei='0')thenq2<='0';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(5)='0' and ei='0')thenq2<='0';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(6)='0' and ei='0')thenq2<='0';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(7)='0' and ei='0')then --d7 prioty encoderq2<='0';q1<='0';q0<='0';gs<='0';eo<='1';elsif(ei='1')thenq2<='1';q1<='0';q0<='1';gs<='1';eo<='1';elsif(d="11111111" and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='1';eo<='0';end if;end process;end encoder;6.27段显示译码器设计译码器设计源代码：library ieee;use ieee.std_logic_1164.all;entity decoder47 isport(lt,ibr,ib_ybr:in bit;a: in std_logic_vector(3 downto 0);y:out std_logic_vector(6 downto 0));end decoder47;architecture art of decoder47 isbeginprocess(lt,ibr,ib_ybr,a)variable s: std_logic_vector(3 downto 0);begins:=a(3)&a(2)&a(1)&a(0);if lt='0' and ib_ybr='1' theny<="1111111"; --检查七段显示管是否正常elsif ibr='0' and a="0000" theny<="0000000";elsecase s iswhen"0000"=>y<="1111110"; --7Ewhen"0001"=>y<="0110000"; --30when"0010"=>y<="1101101"; --6Dwhen"0011"=>y<="1111001"; --79when"0100"=>y<="0110011"; --33when"0101"=>y<="1011011"; --5Bwhen"0110"=>y<="0011111"; --5Fwhen"0111"=>y<="1110000"; --70when"1000"=>y<="1111111"; --7Ewhen"1001"=>y<="1110011"; --7Bwhen"1010"=>y<="0001101"; --0Dwhen"1011"=>y<="0011001"; --19when"1100"=>y<="0100011"; --23when"1101"=>y<="1001011"; --4Bwhen"1110"=>y<="0001111"; --0Fwhen"1111"=>y<="0000000";end case;end if;end process;end art;6.3带异步清零端的12位二进制全加器设计子模块源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end adder4b;architecture art of adder4b issignal sint:std_logic_vector(4 downto 0);signal aa,bb:std_logic_vector(4 downto 0);beginprocess(clr)beginif clr='1'thensint<="00000";elseaa<='0'&a;bb<='0'&b;sint<=aa+bb+cin;end if;s<=sint(3 downto 0);cout<=sint(4);end process;end art;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder12b isport(clr,cin: in std_logic;a,b: in std_logic_vector(11 downto 0);s: out std_logic_vector(11 downto 0);cout:out std_logic);end adder12b;architecture art of adder12b iscomponent adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end component;signal carry_out1:std_logic;signal carry_out2:std_logic;beginu1:adder4b port map(clr=>clr,cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),s=>s(3 downto 0),cout=>carry_out1);u2:adder4b port map(clr=>clr,cin=>carry_out1,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>carry_out2);u3:adder4b port map(clr=>clr,cin=>carry_out2,a=>a(11 downto 8),b=>b(11 downto 8),s=>s(11 downto 8),cout=>cout);end art;6.4 带异步清零/置位端的JK触发器设计带异步清零/置位端的JK触发器源程序如下：library ieee;use ieee.std_logic_1164.all;entity jkff_logic isport(j,k,clk,clr,set:in std_logic;q:out std_logic);end jkff_logic;architecture art of jkff_logic issignal q_s:std_logic;beginprocess(clk,clr,set,j,k)beginif set='0' thenq_s<='1'; --异步置位elsif clr='1' thenq<='0'; --异步复位elsif clk'event and clk='1' thenif (j='0') and (k='1') thenq_s<='0';elsif(j='1') and (k='0') thenq_s<='1';elsif(j='1') and (k='1') thenq_s<=not q_s;end if;end if;q<=q_s;end process;end art;6.5 4位锁存器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity latch1b isport(d: in std_logic;ena: in std_logic; --使能端q: out std_logic);end latch1b;architecture art of latch1b isbeginprocess(d,ena)beginif ena='1' thenq<=d;end if;end process;end art;元件声明程序包设计源代码：library ieee;use ieee.std_logic_1164.all;package my_package iscomponent latch1port(d:in std_logic;ena:in std_logic;q: out std_logic);end component;end;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use work.my_package.all; --使用用户自定义的程序包entity latch4d isport(d: in std_logic_vector(3 downto 0);oen: in bit;q:out std_logic_vector(3 downto 0));end latch4d;architecture one of latch4d issignal sig_save:std_logic_vector(3 downto 0);begingetlatch:for n in 0 to 3 generate --用for_generate语句循环例化4个1位锁存器latchx:latch1 port map(d(n),g,sig_save(n)); --关联end generate;q<=sig_save when oen='0'else"ZZZZ";end one;6.6 32进制多样型计数器设计（1）32进制同步加法计数器源程序32进制同步加法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_plus isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_plus issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr,)beginif clr='1'thend1<=(others=>'0');d0<="0000"; --同步清零elsif clk'event and clk='1' thenif(d1=3 and d0=1)thend1<="0000";d0<="0000"; --计数到32时清零elsif(d0=1) thend0<="0000";d1<=d1+1;elsed0<=d0+1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（2）32进制同步减法计数器源程序32进制同步减法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_sub isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_sub issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr)beginif clr='1' thend1<="0000";d0<="0000"; --异步清零elsif clk'event and clk='1' thenif(d1=0 and d0=0) thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（3）32进制同步可逆计数器源程序32进制同步可逆计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_reversible isport(clk,clr,s:in std_logic; --s=1加法计数，s=0减法计数dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_reversible issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr,s)beginif clr='1'thend1<="0000";d0<="0000"; --异步清零elsif (clk'event and clk='1' )thenif s='1' thenif(d1=3 and d0=1) thend1<="0000";d0<="0000"; --计数到31时清零elsif(d0=1) thend0<="0000";d1<=d1+1;else d0<=d0+1;end if;elsif s='0' thenif(d1=0 and d0=0)thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（4）32进制异步加法计数器源程序32进制异步加法计数器源程序如下：①子模块D触发器源程序设计。

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity clock isport (clk,clr,a,c,e,f,g:in std_logic;led_sel:out std_logic_vector( 2 downto 0);led:out std_logic_vector( 0 to 6);p:in std_logic_vector( 3 downto 0);b:in std_logic_vector(1 downto 0);d:out std_logic );end entity clock;architecture bhv of clock issignal m: integer range 0 to 999;signal hou1,hou0,min1,min0,sec1,sec0,s2:std_logic_vector(3 downto 0);signal rhou1,rhou0,rmin1,rmin0,rsec1,rsec0:std_logic_vector(3 downto 0);signal s1: std_logic_vector(2 downto 0);signal clk1,clk2,d1,d2:std_logic;signal n : integer range 0 to 1;beginp1:process(clk) --二分频beginif (rising_edge(clk)) thenif n=1 then n<=0;clk2<='1';else n<=n+1; clk2<='0';end if;end if ;end process;p2:process(clk)beginif (rising_edge(clk)) thenif m=999 then m<=0;clk1<='1';else m<=m+1; clk1<='0';end if;end if ;end process P2;p3: process(clk1,clr) ---时间设置beginif (clr='1') then sec0<="0000";sec1<="0000";min0<="0000";min1<="0000";hou0<="0000";hou1<="0000";elsif rising_edge(clk1) thenif a='1' then --校时if b="00" then hou1<=p;elsif b="01" then hou0<=p;elsif b="10" then min1<=p;elsif b="11" then min0<=p;end if;end if;if sec0>="1001" thensec0<="0000";if sec1>="0101" thensec1<="0000";if min0>="1001" thenmin0<="0000";if min1>="0101" thenmin1<="0000";if g='0'thenif hou1<"0010" thenif hou0="1001" thenhou0<="0000";hou1<=hou1+1 ;else hou0<=hou0+1;elsif hou1="0010" and hou0="0011" thenhou1<="0000";hou0<="0000";else hou0<=hou0+1;end if ;end if;if g='1'thenif hou1<"0001" thenif hou0="1001" thenhou0<="0000";hou1<=hou1+1 ;else hou0<=hou0+1;end if;elsif hou1="0001" and hou0="0001" thenhou1<="0000";hou0<="0000";else hou0<=hou0+1;end if ;end if;else min1<=min1+1;end if;else min0<=min0+1;else sec1<=sec1+1;end if;else sec0<=sec0+1;end if;end if ;end process P3;p4:process(clk) --数码管选通beginif(rising_edge (clk)) thenif s1="111" thens1<="000";else s1<=s1+1;end if;end if;-- led_sel<=s1;end process;p5:process(s1,f) ---闹铃显示beginif f='0'thencase s1 iswhen "000"=>s2<=sec0;led_sel<="000";when "001"=>s2<=sec1;led_sel<="001";when "010"=>s2<=min0;led_sel<="010";when "011"=>s2<=min1;led_sel<="011";when "100"=>s2<=hou0;led_sel<="100";when "101"=>s2<=hou1;led_sel<="101";when others=>null;end case;elsif f='1' thencase s1 iswhen "010"=>s2<=rmin0;led_sel<="010";when "011"=>s2<=rmin1;led_sel<="011";when "100"=>s2<=rhou0;led_sel<="100";when "101"=>s2<=rhou1;led_sel<="101";when others=>null;end case;end if;end process;p6:process(s2) --七段译码器beginif(s1<6) thencase s2 iswhen "0000"=>led<="0111111"; when "0001"=>led<="0000110"; when "0010"=>led<="1011011"; when "0011"=>led<="1001111"; when "0100"=>led<="1100110"; when "0101"=>led<="1101101"; when "0110"=>led<="1111101"; when "0111"=>led<="0000111"; when "1000"=>led<="1111111"; when "1001"=>led<="1101111"; when others=>null;end case ;else led<="0000000";end if;end process;p7:process(clk1,c) --整点报时beginif (rising_edge(clk))thenif c='1' thenif (min1="0101" and min0="1001" and sec1="0101") then if(sec0="0000"or sec0="0010" or sec0="0100" orsec0="0110" or sec0="1000")thend1<='1'and clk2;else d1<='0';end if;elsif (min1="0000" and min0="0000" and sec0="0000" andsec1="0000") thend1<='1';else d1<='0';end if ;end if ;end if ;end process;p8:process(clk,e) ---闹铃设置beginif (rising_edge(clk))thenif e='1' thenif b="000"then rhou1<=p;elsif b="001"then rhou0<=p;elsif b="010"then rmin1<=p;elsif b="011"then rmin0<=p;end if;end if;end if;end process;p9:process(clk) ---闹铃比较beginif(rising_edge(clk))thenif e='1'thenif(rhou1=hou1 and rhou0=hou0 and rmin1=min1 and rmin0=min0)then if(sec0="0001"or sec0="0010" or sec0="0011" orsec0="0011" or sec0="0100" )thend2<='1'and clk2;else d2<='0';end if;else d2<='0';end if;end if;end if;end process;d<=d1 or d2;end architecture bhv;。

八、源代码及注释--电子节拍器--分频器组模块dividers源代码--分频器组模块通过对50MHz的外部时钟进行分频，--产生其他模块所需的各种时钟频率并输出，--有60Hz、5000Hz、3000Hz、1500Hz、1000Hz，分别用5个进程实现。

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity dividers is --定义实体dividersport(clk : in std_logic; --外部时钟输入clk_out60: out std_logic; --60Hz频率输出clk_out5000 : out std_logic; --5000Hz频率输出clk_out3000 : out std_logic; --3000Hz频率输出clk_out1500 : out std_logic; --1500Hz频率输出clk_out1000 : out std_logic); --1000Hz频率输出end dividers;architecture div of dividers issignal tmp5000 : integer range 0 to 4999; --分频得5000hz 的计数器大小signal tmp3000 : integer range 0 to 8332; --3000hz 3x10^9=50x10^6x60 use 3000hz signal tmp1500 : integer range 0 to 16665; --1500hzsignal tmp1000 : integer range 0 to 49999; --1000hzsignal tmp60 : integer range 0 to 416666; --60hzsignal clktmp5000 : std_logic; --分频得5000hz 的时钟信号signal clktmp3000 : std_logic;signal clktmp1500 : std_logic;signal clktmp1000 : std_logic;signal clktmp60 : std_logic;beginp5000: process(clk) --分频得5000hz 的分频器进程beginif clk'event and clk='1' then --对50MHz进行10000分频得5000hz 的频率if tmp5000=4999 then --达到5000hz 的计数器大小时归零tmp5000<=0;clktmp5000<=not clktmp5000; --5000hz 的时钟信号翻转一次elsetmp5000<=tmp5000+1; ----未达到5000hz 的计数器模值时计数器加一end if;end if;end process p5000; --分频得5000hz 的分频器进程结束p1500: process(clk) --以下各分频器原理同上beginif clk'event and clk='1' thenif tmp1500=16665 thentmp1500<=0;clktmp1500<=not clktmp1500;elsetmp1500<=tmp1500+1;end if;end if;end process p1500;p1000: process(clk)beginif clk'event and clk='1' thenif tmp1000=49999 thentmp1000<=0;clktmp1000<=not clktmp1000;elsetmp1000<=tmp1000+1;end if;end if;end process p1000;p3000: process(clk)beginif clk'event and clk='1' thenif tmp3000=8332 thentmp3000<=0;clktmp3000<=not clktmp3000;elsetmp3000<=tmp3000+1;end if;end if;end process p3000;p60: process(clk)beginif clk'event and clk='1' thenif tmp60=416666 thentmp60<=0;clktmp60<=not clktmp60;elsetmp60<=tmp60+1;end if;end if;end process p60;clk_out5000 <= clktmp5000; --输出分频得到的5000hz 频率clk_out3000 <= clktmp3000;clk_out1500 <= clktmp1500;clk_out1000 <= clktmp1000;clk_out60 <= clktmp60;end div; ———————————————————————————————————————--电子节拍器--速度设置模块set_speed源代码--速度设置模块实现速度在40至120内连续可调library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity set_speed isport(clk60 : in std_logic; --分频器60hz时钟输入vadd : in std_logic; --加按键输入vdec : in std_logic; --减按键输入clear : in std_logic; --置位键输入beat_v : out std_logic_vector(6 downto 0); --速度输出v_out0 : out std_logic_vector(3 downto 0); --速度个位二进制输出（对应0号数码管）v_out1 : out std_logic_vector(3 downto 0); --速度十位二进制输出（对应1号数码管）v_out2 : out std_logic_vector(3 downto 0)); --速度百位二进制输出（对应2号数码管）end set_speed;architecture set of set_speed issignal cn : integer range 40 to 120; --速度记录信号signal change_a : std_logic; --加按键输入按下记录信号signal change_d : std_logic; --减按键输入按下记录信号signal count_add : integer:=0; --加按键输入按下时长记录信号signal count_dec : integer:=0; --减按键输入按下时长记录信号signal a10 : integer range 0 to 99; --速度减去百位的数的记录信号signal a0 : integer range 0 to 9; --速度个位记录信号signal a1 : integer range 0 to 9; --速度十位记录信号signal a2 : integer range 0 to 1; --速度百位记录信号beginprocess(clk60,vadd,vdec)beginif clk60'event and clk60='1' thenif (vadd='1') then --若加键按下change_a<='1'; --加按键输入按下记录信号置1count_add<=count_add+1; --加按键输入按下时长记录信号加1if (count_add>60 and cn<=115) then --加按键输入按下时长记录信号大于60--即加按键按下时长大于1s（长按）--若速度小于115cn<=cn+5; --则速度连加5count_add<=count_add-60; --同时加按键输入按下时长记录信号减60 elsif (count_add>60 and cn>115) then --若速度大于115cn<=120; --速度只能增加到设置的上限120count_add<=0; --加按键输入按下时长记录信号置0change_a<='0'; --加按键输入按下记录信号置0end if;elsif (vdec='1') then --原理同加按键change_d<='1';count_dec<=count_dec+1;if (count_dec>60 and cn>=45) thencn<=cn-5;count_dec<=count_dec-60;elsif (count_dec>60 and cn<45) thencn<=40;count_dec<=0;change_d<='0';end if;elsif(vadd='0' and vdec='0') then --检测到无键按下时if (change_a='1' and count_add<60 and cn<120 ) then --若加键按下--且加按键输入按下时长记录信号小于60（短按）--且速度小于120cn<=cn+1; --则速度加1count_add<=0;change_a<='0';elsif (change_a='1' and count_add>=60 ) then --若加键长按count_add<=0;change_a<='0';if (cn<=115 ) then --原理同上cn<=cn+5;elsif (cn>115 ) thencn<=120;end if;elsif (change_d='1' and count_dec<60 and cn>40 ) then --原理同加按键cn<=cn-1;count_dec<=0;change_d<='0';elsif (change_d='1' and count_dec>=60 ) thencount_dec<=0;change_d<='0';if (cn>=45 ) thencn<=cn-5;elsif (cn<45 ) thencn<=40;end if;end if;end if;if clear ='1' then --实现置位功能cn<=80;count_add<=0;count_dec<=0;end if;if cn>=100 thena2<=1;a10<=cn-100;elsea2<=0;a10<=cn;end if;a1<= a10/10;a0<= a10-a1*10;end if;end process;v_out2<=conv_std_logic_vector(a2,4); --将速度的百位（十进制）转换为二进制后输出v_out1<=conv_std_logic_vector(a1,4);v_out0<=conv_std_logic_vector(a0,4);beat_v<=conv_std_logic_vector(cn,7); --将速度（十进制）转换为二进制后输出end set;--电子节拍器--节拍型选择模块set_rhythm源代码--节拍型选择模块可设置的节拍有1/4、2/4、3/4、4/4、3/8、6/8可选，--通过sel 按键选择，送到2个数码管显示，并把选好的节拍型输出到相关模块。

VHDL代码[例1.4.26] 2输入与门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY and2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END and2; ARCHITECTURE one OF and2 IS BEGINy<= a and b;END one;[例2.5.1] 2输入与非门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END nand2; ARCHITECTURE one OF nand2 IS BEGINy<= a nand b;END one;[例2.5.2] 2输入或门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END or2;ARCHITECTURE one OF or2 IS BEGINy<= a or b;END one;[例2.5.3]非门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY hnot ISPORT(a : IN STD_LOGIC;y: OUT STD_LOGIC);END hnot; ARCHITECTURE one OF hnot IS BEGINy<= not a;END one;[例2.5.4] 2输入异或门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY xor2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END xor2; ARCHITECTURE one OF xor2 IS BEGINy<= a xor b;END one;[例3.8.1] 3线-8线译码器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY decoder38 ISPORT(a : IN STD_LOGIC_VECTOR(2 DOWNTO 0); y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END decoder38;ARCHITECTURE one OF decoder38 ISBEGINPROCESS (a)BEGINCASE a ISWHEN "000" => y<= "00000001";WHEN "001" => y<= "00000010";WHEN "010" => y<= "00000100";WHEN "011" => y<= "00001000";WHEN "100" => y<= "00010000";WHEN "101" => y<= "00100000";WHEN "110" => y<= "01000000";WHEN "111" => y<= "10000000";WHEN OTHERS =>null ;END CASE;END PROCESS;END one;[例3.8.2] 8线-3线优先编码器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY encoder83 ISPORT( d : IN STD_LOGIC_VECTOR(7 DOWNTO 0); encode: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END encoder83;ARCHITECTURE one OF encoder83 ISBEGINencode <= "111" when d(7) = '1' else "110" when d(6) = '1' else"101" when d(5) = '1' else"100" when d(4) = '1' else"011" when d(3) = '1' else"010" when d(2) = '1' else"001" when d(1) = '1' else"000" when d(0) = '1' ;END one;[例3.8.3] 4选1数据选择器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux41 isPORT (a,b,c,d : IN STD_LOGIC;s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);z : OUT STD_LOGIC);END mux41;ARCHITECTURE one OF mux41 ISBEGINPROCESS (s ,a,b,c,d)BEGINCASE s ISWHEN "00" => z<= a;WHEN "01" => z<= b;WHEN "10" => z<= c;WHEN "11" => z<= d;WHEN OTHERS =>z<= 'x';END CASE;END PROCESS;END one;[例4.8.1] 同步复位D触发器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY d_ff isPORT (d,clk,reset : IN STD_LOGIC;q : OUT STD_LOGIC);END d_ff;ARCHITECTURE one OF d_ff IS BEGINPROCESS (clk)BEGINIF clk'EVENT AND clk='1' THENIF reset='1' THENQ<='0';ELSE q<=d;END IF;END IF;END PROCESS;END one;[例4.8.2] 边沿JK 触发器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY jk_ff isPORT (j,k,clk : IN STD_LOGIC;q, qn : OUT STD_LOGIC);END jk_ff;ARCHITECTURE one OF jk_ff IS SIGNAL q_s : STD_LOGIC; BEGINPROCESS (j,k,clk)BEGINIF clk'EVENT AND clk='1' THENIF J='0' AND k='0' THENq_s<= q_s;ELSIF J='0' AND k='1' THENq_s<='0';ELSIF J='1' AND k='0' THENq_s<='1';ELSIF J='1' AND k='1' THENq_s<=NOT q_s;END IF;END IF;END PROCESS;q<=q_s;qn<=not q_s;END one;[例5.6.1] 十进制计数器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count10 isPORT (cp : IN STD_LOGIC;q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END count10;ARCHITECTURE one OF count10 ISSIGNAL count :STD_LOGIC_VECTOR(3 DOWNTO 0) ; BEGINPROCESS (cp)BEGINIF cp'EVENT AND cp='1' THENIF count <="1001" THENcount <="0000";ELSE count <= count +1;END IF;END IF;END PROCESS;q<= count;END one;[例5.6.2] 4位基本寄存器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY registerb isPORT (cp,reset : IN STD_LOGIC;data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END registerb;ARCHITECTURE one OF registerb ISBEGINPROCESS (cp)BEGINIF cp'EVENT AND cp='1' THEN IF reset='1' THENq<="0000";ELSEq<= data;END IF;END IF;END PROCESS;END one;。

（写的有点简陋，见谅哈,各位~~）VHDL时序设计逻辑电路设计（一）四位二进制减计数器（摘自网上）library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count1 isport(ci:in std_logic; --计数信号reset: in std_logic; --异步复位load: in std_logic; --同步置数clk: in std_logic;d : in std_logic_vector(3 downto 0); --置数值q : buffer std_logic_vector(3 downto 0);co: out std_logic --计数溢出标志);end count1;architecture behave of count1 isbeginprocess(clk,reset)beginif(reset='0') thenq<="0000";elsif(clk'event and clk='1') thenif(load='1') thenq<=d;elsif(ci='1') thenif(q=0) thenq<="1111";co<='1';elseq<=q-1;co<='0';end if;end if;end if;end process;end behave;VHDL时序设计逻辑电路设计（二）（一）带异步复位的4位能自动启动环形计数器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY HUANXINGJISHU ISPORT(clk,rs:IN STD_LOGIC;countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END HUANXINGJISHU;ARCHITECTURE behave OF HUANXINGJISHU ISSIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(rs,clk)BEGINIF rs='0' THEN Q<="0011";ELSIF(clk'event AND clk='1') THENCASE Q ISWHEN"0000"=>Q<="0001";WHEN"0001"=>Q<="0010";WHEN"0010"=>Q<="0100";WHEN"0011"=>Q<="0110";WHEN"0100"=>Q<="1000";WHEN"0101"=>Q<="1010";WHEN"0110"=>Q<="1100";WHEN"0111"=>Q<="1110";WHEN"1000"=>Q<="0001";WHEN"1001"=>Q<="0010";WHEN"1010"=>Q<="0100";WHEN"1011"=>Q<="0110";WHEN"1100"=>Q<="1000";WHEN"1101"=>Q<="1010";WHEN"1110"=>Q<="1100";WHEN"1111"=>Q<="1110";WHEN OTHERS =>Q<="0000";END CASE;END IF;END PROCESS;countout<=Q;END behave;（二）带异步复位的4位能自启动扭形计数器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY NIUHUAIJISHU ISPORT(clk,rs:IN STD_LOGIC;countout:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END NIUHUAIJISHU ;ARCHITECTURE behave OF NIUHUAIJISHU ISSIGNAL Q:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGINPROCESS(rs,clk)BEGINIF rs='0' THEN Q<="0100";ELSIF(clk'event AND clk='1') THENCASE Q ISWHEN"0000"=>Q<="0001";WHEN"0001"=>Q<="0011";WHEN"0010"=>Q<="0101";WHEN"0011"=>Q<="0111";WHEN"0100"=>Q<="1001";WHEN"0101"=>Q<="1011";WHEN"0110"=>Q<="1101";WHEN"0111"=>Q<="1111";WHEN"1000"=>Q<="0000";WHEN"1001"=>Q<="0010";WHEN"1010"=>Q<="0101";WHEN"1011"=>Q<="0111";WHEN"1100"=>Q<="1000";WHEN"1101"=>Q<="1010";WHEN"1110"=>Q<="1100";WHEN"1111"=>Q<="1110";WHEN OTHERS =>Q<="0000";END CASE;END IF;END PROCESS;countout<=Q;END behave;VHDL时序逻辑电路设计（三）（一）带控制端的8位二进制寄存器：先生成一VHDL file文件，编译以下底层的D触发器文件：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY DCHUFAQI ISPORT (d,clk:IN STD_LOGIC;q:OUT STD_LOGIC);END DCHUFAQI;ARCHITECTURE one OF DCHUFAQI ISBEGINPROCESSBEGINW AIT UNTIL clk='1';q<=d;END PROCESS ;END one;再在同一工程下生成一VHDL文件，源代码如下：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY JICUNQI ISPORT(d: IN STD_LOGIC_VECTOR (7 DOWNTO 0);oe,clk: IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END JICUNQI;ARCHITECTURE struc OF JICUNQI ISCOMPONENT DCHUFAQIPORT(d,clk:IN STD_LOGIC;q: OUT STD_LOGIC);END COMPONENT;SIGNAL temp:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS(clk,oe)BEGINIF oe='1' THENq<="ZZZZZZZZ";ELSEq<=temp;END IF;END PROCESS;u0:DCHUFAQI PORT MAP(d(0),clk,temp(0));u1:DCHUFAQI PORT MAP(d(1),clk,temp(1));u2:DCHUFAQI PORT MAP(d(2),clk,temp(2));u3:DCHUFAQI PORT MAP(d(3),clk,temp(3));u4:DCHUFAQI PORT MAP(d(4),clk,temp(4));u5:DCHUFAQI PORT MAP(d(5),clk,temp(5));u6:DCHUFAQI PORT MAP(d(6),clk,temp(6));u7:DCHUFAQI PORT MAP(d(7),clk,temp(7));END struc;（二）带控制端的8位二进制锁存器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SUOCUNQI ISPORT(d:IN STD_LOGIC_VECTOR(7 DOWNTO 0);oe,clk:IN STD_LOGIC;q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END SUOCUNQI;ARCHITECTURE struc OF SUOCUNQI ISSIGNAL temp:STD_LOGIC_VECTOR(7 DOWNTO 0); BEGINPROCESS(clk,oe)BEGINIF oe='0' THENIF clk='1' THENtemp<=d;END IF;ELSEtemp<="ZZZZZZZZ";END IF;q<=temp;END PROCESS;END struc;。

分频器的VHDL代码在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。

我们知道，在硬件电路设计中时钟信号是最重要的信号之一。

下面我们介绍分频器的VHDL 描述，在源代码中完成对时钟信号CLK 的 2 分频，4 分频，8 分频，16 分频。

这也是最简单的分频电路，只需要一个计数器即可。

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY clkdiv ISPORT(clk : IN STD_LOGIC;clk_div2 : OUT STD_LOGIC;clk_div4 : OUT STD_LOGIC;clk_div8 : OUT STD_LOGIC;clk_div16 : OUT STD_LOGIC);END clk_div;ARCHITECTURE rtl OF clk_div ISSIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(clk)BEGINIF (clk"event AND clk=" 1" ) THENIF(count=” 1111” ) THENCount <= (OTHERS =>" 0" );ELSECount <= count +1;END IF ;END IF ;END PROCESS;clk_div2 <= count(0);clk_div4 <= count(1);clk_div8 <= count(2);clk_div16 <= count(3);END rtl;对于分频倍数不是 2 的整数次幂的情况，我们只需要对源代码中的计数器进行一下计数控制就可以了，如下面源代码描述一个对时钟信号进行 6 分频的分频器。

ies的.vh编译
首先，要编译VHDL代码，你需要安装一个VHDL编译器。

常见
的VHDL编译器包括ModelSim，Xilinx ISE，Altera Quartus等。

这些编译器通常会将VHDL代码转换为可在FPGA或ASIC芯片上实现
的逻辑网表或者门级网表。

编译VHDL代码的过程通常包括以下步骤：
1. 编写VHDL源代码文件，通常以.vhdl或者.vh为扩展名。

2. 打开VHDL编译器的IDE或者使用命令行工具，导入你的VHDL代码文件。

3. 在IDE中设置编译选项，例如目标FPGA型号、时钟频率等。

4. 执行编译命令，编译器会对VHDL代码进行语法分析、综合
和布线等操作，最终生成一个可在目标芯片上实现的二进制文件。

在编译过程中，编译器会检查代码中的语法错误、逻辑错误和
时序问题，并生成相应的报告。

如果代码中存在错误，编译器会提
示你进行修正。

总的来说，VHDL代码的编译是将高级的硬件描述语言转换为可以在特定硬件平台上实现的低级逻辑表示的过程。

通过编译，我们可以验证代码的正确性，并最终将其加载到FPGA或ASIC芯片上。

希望这个回答能够帮助你更好地理解“ies的.vh编译”。

4m分频library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity div4 isport<clk_in : in std_logic;clk_out : out std_logic>;end;architecture a of div4 issignal cnt : integer range 0 to 6;signal clk_tmp : std_logic;beginprocess<clk_in>beginif <clk_in'event and clk_in='1'> thenif cnt=6 thencnt<=0;clk_tmp<= not clk_tmp;elsecnt<=cnt+1;end if;end if;end process;clk_out<=clk_tmp;end;4分频library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity div4m isport<clk_in : in std_logic;clk_out : out std_logic>;end;architecture a of div4m issignal cnt : integer range 0 to 6249999;signal clk_tmp : std_logic;beginprocess<clk_in>beginif <clk_in'event and clk_in='1'> thenif cnt=6249999 thencnt<=0;clk_tmp<= not clk_tmp;elsecnt<=cnt+1;end if;end if;end process;clk_out<=clk_tmp;end;speakerLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY Speaker ISPORT<CK4MHZ:IN STD_LOGIC;YINFU:IN INTEGER RANGE 0 TO 21;SP:OUT STD_LOGIC>;END Speaker;ARCHITECTURE cnt OF Speaker ISSIGNAL count:INTEGER :=0;SIGNAL F,TWO:STD_LOGIC;BEGINPROCESS<YINFU,CK4MHZ>BEGINIF<CK4MHZ'EVENT AND CK4MHZ = '1'> THEN IF<YINFU = 0> THEN F<='0';ELSIF<YINFU =1> THEN count <=count +1;IF<count<7644>THEN F <='0';ELSE F <='1';count <=0; END IF;ELSIF<YINFU = 2> THEN count<=count +1;IF<count<6810>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 3> THEN count<=count +1;IF<count<6068>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 4> THEN count<=count +1;IF<count<5726>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 5> THEN count<=count +1;IF<count<5102>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 6> THEN count<=count +1;IF<count<4546>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 7> THEN count<=count +1;IF<count<4050>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 8> THEN count<=count +1;IF<count<3822>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 9> THEN count<=count +1;IF<count<3406>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 10> THEN count<=count +1;IF<count<3034>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 11> THEN count<=count +1;IF<count<2864>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 12> THEN count<=count +1;IF<count<2552>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 13> THEN count<=count +1;IF<count<2272>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 14> THEN count<=count +1;IF<count<2024>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 15> THEN count<=count +1;IF<count<1912>THEN F<='0';ELSE F<='1';count <=0;ELSIF<YINFU = 16> THEN count<=count +1;IF<count<1702>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 17> THEN count<=count +1;IF<count<1516>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 18> THEN count<=count +1;IF<count<1432>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 19> THEN count<=count +1;IF<count<1276>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 20> THEN count<=count +1;IF<count<1136>THEN F<='0';ELSE F<='1';count <=0; END IF;ELSIF<YINFU = 21> THEN count<=count +1;IF<count<1012>THEN F<='0';ELSE F<='1';count <=0; END IF;END IF;END IF;END PROCESS;PROCESS<F>IF<F'EVENT AND F = '1'> THEN ---输出之前的二分频TWO <=NOT TWO;END IF;SP <=TWO;END PROCESS;END cnt;YinfuLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY yinfu ISPORT<CK4HZ:IN STD_LOGIC;YF:OUT INTEGER RANGE 0 TO 21>;END yinfu;ARCHITECTURE NAME OF yinfu ISSIGNAL COUNT:INTEGER:=0;BEGINPROCESS<ck4HZ>BEGINIF<ck4HZ'EVENT AND ck4HZ='1'> THENIF<COUNT <101> THEN COUNT <=COUNT+1;ELSE COUNT<=0; END IF;END IF;. END PROCESS;PROCESS<COUNT>BEGINCASE COUNT ISWHEN 00 => YF <=0;WHEN 01 => YF <= 0;WHEN 02 => YF <=13;WHEN 03 => YF <=14;WHEN 04 => YF <=15;WHEN 05 => YF <=15;WHEN 06 => YF <=15;WHEN 07 => YF <=15;WHEN 08 => YF <=15;WHEN 09 => YF <=15;WHEN 10 => YF <=15;WHEN 11 => YF <=14;WHEN 12 => YF <=14;WHEN 13 => YF <=17;WHEN 14 => YF <=17;WHEN 15 => YF <=17;WHEN 16 => YF <=17;WHEN 17 => YF <=20;WHEN 19 => YF <=20; WHEN 20 => YF <=20; WHEN 21 => YF <=0; WHEN 22 => YF <=19; WHEN 23 => YF <=19; WHEN 24 => YF <=18; WHEN 25 => YF <=19; WHEN 26 => YF <=15; WHEN 27 => YF <=15; WHEN 28 => YF <=15; WHEN 29 => YF <=18; WHEN 30 => YF <=18; WHEN 31 => YF <= 18; WHEN 32 => YF <=17; WHEN 33 => YF <=17; WHEN 34 => YF <=17; WHEN 35 => YF <=17; WHEN 36 => YF <=16; WHEN 37 => YF <=16; WHEN 38 => YF <=16; WHEN 39 => YF <=16;WHEN 41 => YF <=14; WHEN 42 => YF <=14; WHEN 43 => YF <=15; WHEN 44 => YF <=15; WHEN 45 => YF <=15; WHEN 46 => YF <=14; WHEN 47 => YF <=14; WHEN 48 => YF <=13; WHEN 49 => YF <=14; WHEN 50 => YF <=15; WHEN 51 => YF <=15; WHEN 52 => YF <=15; WHEN 53 => YF <=15; WHEN 54 => YF <=15; WHEN 55 => YF <=15; WHEN 56 => YF <=15; WHEN 57 => YF <=15; WHEN 58 => YF <=14; WHEN 59 => YF <=14; WHEN 60 => YF <=17; WHEN 61 => YF <= 17;WHEN 63 => YF <=20; WHEN 64 => YF <=20; WHEN 65 => YF <=20; WHEN 66 => YF <=20; WHEN 67 => YF <=0; WHEN 68 => YF <=19; WHEN 69 => YF <=19; WHEN 70 => YF <=18; WHEN 71 => YF <=19; WHEN 72 => YF <=19; WHEN 73 => YF <=19; WHEN 74 => YF <=15; WHEN 75 => YF <=15; WHEN 76 => YF <=15; WHEN 77 => YF <=15; WHEN 78 => YF <=18; WHEN 79 => YF <=18; WHEN 80 => YF <=18; WHEN 81 => YF <=18; WHEN 82 => YF <=19; WHEN 83 => YF <=19;WHEN 85 => YF <=18; WHEN 86 => YF <=17; WHEN 87 => YF <=17; WHEN 88 => YF <=16; WHEN 89 => YF <=16; WHEN 90 => YF <=15; WHEN 91 => YF <= 15; WHEN 92 => YF <=14; WHEN 93 => YF <=14; WHEN 94 => YF <=13; WHEN 95 => YF <=13; WHEN 96 => YF <=13; WHEN 97 => YF <=13; WHEN 98 => YF <=0; WHEN 99 => YF <=0; WHEN 100 => YF <=6; WHEN 101 => YF <=6; WHEN OTHERS => NULL; END CASE;END PROCESS;END NAME;.Yinfu1LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY yinfu1 ISPORT<CK4HZ:IN STD_LOGIC;YF:OUT INTEGER RANGE 0 TO 21>;END yinfu1;ARCHITECTURE NAME OF yinfu1 ISSIGNAL COUNT:INTEGER:=0;BEGINPROCESS<ck4HZ>BEGINIF<ck4HZ'EVENT AND ck4HZ='1'> THENIF<COUNT <118> THEN COUNT <=COUNT+1;ELSE COUNT<=0; END IF;END IF;END PROCESS;PROCESS<COUNT>BEGINCASE COUNT ISWHEN 00 => YF <=6;WHEN 01 => YF <= 6;WHEN 02 => YF <=6;WHEN 04 => YF <=6; WHEN 05 => YF <=6; WHEN 06 => YF <=6; WHEN 07 => YF <=6; WHEN 08 => YF <=8; WHEN 09 => YF <=9; WHEN 10 => YF <=10; WHEN 11 => YF <=12; WHEN 12 => YF <=15; WHEN 13 => YF <=15; WHEN 14 => YF <=15; WHEN 15 => YF <=15; WHEN 16 => YF <=15; WHEN 17 => YF <=15; WHEN 18 => YF <=15; WHEN 19 => YF <=15; WHEN 20 => YF <=15; WHEN 21 => YF <=15; WHEN 22 => YF <=15; WHEN 23 => YF <=15; WHEN 24 => YF <=10;WHEN 26 => YF <=12; WHEN 27 => YF <=12; WHEN 28 => YF <=15; WHEN 29 => YF <=16; WHEN 30 => YF <=17; WHEN 31 => YF <= 17; WHEN 32 => YF <=17; WHEN 33 => YF <=17; WHEN 34 => YF <=18; WHEN 35 => YF <=18; WHEN 36 => YF <=18; WHEN 37 => YF <=18; WHEN 38 => YF <=18; WHEN 39 => YF <=18; WHEN 40 => YF <=18; WHEN 41 => YF <=18; WHEN 42 => YF <=10; WHEN 43 => YF <=12; WHEN 44 => YF <=15; WHEN 45 => YF <=16; WHEN 46 => YF <=15;WHEN 48 => YF <=15; WHEN 49 => YF <=15; WHEN 50 => YF <=14; WHEN 51 => YF <=15; WHEN 52 => YF <=16; WHEN 53 => YF <=18; WHEN 54 => YF <=16; WHEN 55 => YF <=12; WHEN 56 => YF <=13; WHEN 57 => YF <=14; WHEN 58 => YF <=10; WHEN 59 => YF <=11; WHEN 60 => YF <=9; WHEN 61 => YF <= 9; WHEN 62 => YF <=10; WHEN 63 => YF <=10; WHEN 64 => YF <=10; WHEN 65 => YF <=10; WHEN 66 => YF <=6; WHEN 67 => YF <=6; WHEN 68 => YF <=6;WHEN 70 => YF <=6; WHEN 71 => YF <=6; WHEN 72 => YF <=6; WHEN 73 => YF <=8; WHEN 74 => YF <=9; WHEN 75 => YF <=10; WHEN 76 => YF <=12; WHEN 77 => YF <=15; WHEN 78 => YF <=15; WHEN 79 => YF <=15; WHEN 80 => YF <=15; WHEN 81 => YF <=15; WHEN 82 => YF <=15; WHEN 83 => YF <=15; WHEN 84 => YF <=15; WHEN 85 => YF <=10; WHEN 86 => YF <=12; WHEN 87 => YF <=15; WHEN 88 => YF <=16; WHEN 89 => YF <=15; WHEN 90 => YF <=15;WHEN 92 => YF <=15; WHEN 93 => YF <=18; WHEN 94 => YF <=18; WHEN 95 => YF <=18; WHEN 96 => YF <=18; WHEN 97 => YF <=10; WHEN 98 => YF <=12; WHEN 99 => YF <=15; WHEN 100 => YF <=16; WHEN 101 => YF <=15; WHEN 102 => YF <=15; WHEN 103 => YF <=15; WHEN 104 => YF <=15; WHEN 105 => YF <=14; WHEN 106 => YF <=14; WHEN 107 => YF <=14; WHEN 108 => YF <=15; WHEN 109 => YF <=16; WHEN 110 => YF <=17; WHEN 111 => YF <=17; WHEN 112 => YF <=17;WHEN 114 => YF <=8;WHEN 115 => YF <=7;WHEN 116 => YF <=7;WHEN 117 => YF <=6;WHEN 118 => YF <=6;WHEN OTHERS => NULL;END CASE;END PROCESS;END NAME;Yinfu2LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY yinfu2 ISPORT<CK4HZ:IN STD_LOGIC; YF:OUT INTEGER RANGE 0 TO 21>; END yinfu2; ARCHITECTURE NAME OF yinfu2 IS SIGNAL COUNT:INTEGER:=0; BEGINPROCESS<ck4HZ>BEGIN.IF<ck4HZ'EVENT AND ck4HZ='1'> THENIF<COUNT <30> THEN COUNT <=COUNT+1;ELSE COUNT<=0; END IF;END IF;END PROCESS;PROCESS<COUNT>BEGINCASE COUNT ISWHEN 00 => YF <=13;WHEN 01 => YF <= 15;WHEN 02 => YF <=15;WHEN 03 => YF <=15;WHEN 04 => YF <=0;WHEN 05 => YF <=13;WHEN 06 => YF <=15;WHEN 07 => YF <=15;WHEN 08 => YF <=15;WHEN 09 => YF <=15;WHEN 10 => YF <=15;WHEN 11 => YF <=0;WHEN 12 => YF <=0;WHEN 13 => YF <=0;WHEN 14 => YF <=0;WHEN 16 => YF <=13; WHEN 17 => YF <=15; WHEN 18 => YF <=15; WHEN 19 => YF <=15; WHEN 20 => YF <=15; WHEN 21 => YF <=15; WHEN 22 => YF <=10; WHEN 23 => YF <=15; WHEN 24 => YF <=15; WHEN 25 => YF <=13; WHEN 26 => YF <=13; WHEN 27 => YF <=13; WHEN 28 => YF <=13; WHEN 29 => YF <=13; WHEN 30 => YF <=13; WHEN 31 => YF <= 15; WHEN 32 => YF <=13; WHEN 33 => YF <=18; WHEN 34 => YF <=18; WHEN 35 => YF <=18; WHEN 36 => YF <=18;WHEN 38 => YF <=0; WHEN 39 => YF <=17; WHEN 40 => YF <=16; WHEN 41 => YF <=17; WHEN 42 => YF <=17; WHEN 43 => YF <=17; WHEN 44 => YF <=17; WHEN 45 => YF <=0; WHEN 46 => YF <=0; WHEN 47 => YF <=0; WHEN 48 => YF <=0; WHEN 49 => YF <=16; WHEN 50 => YF <=15; WHEN 51 => YF <=16; WHEN 52 => YF <=16; WHEN 53 => YF <=16; WHEN 54 => YF <=16; WHEN 55 => YF <=16; WHEN 56 => YF <=16; WHEN 57 => YF <=0; WHEN 58 => YF <=17;WHEN 60 => YF <=18; WHEN 61 => YF <= 18; WHEN 62 => YF <=18; WHEN 63 => YF <=18; WHEN 64 => YF <=0; WHEN 65 => YF <=0; WHEN 66 => YF <=17; WHEN 67 => YF <=16; WHEN 68 => YF <=21; WHEN 69 => YF <=0; WHEN 70 => YF <=20; WHEN 71 => YF <=19; WHEN 72 => YF <=20; WHEN 73 => YF <=20; WHEN 74 => YF <=20; WHEN 75 => YF <=20; WHEN 76 => YF <=0; WHEN 77 => YF <=19; WHEN 78 => YF <=18; WHEN 79 => YF <=19; WHEN 80 => YF <=19;WHEN 82 => YF <=0; WHEN 83 => YF <=18; WHEN 84 => YF <=17; WHEN 85 => YF <=17; WHEN 86 => YF <=18; WHEN 87 => YF <=16; WHEN 88 => YF <=16; WHEN 89 => YF <=16; WHEN 90 => YF <=16; WHEN 91 => YF <= 16; WHEN 92 => YF <=0; WHEN 93 => YF <=14; WHEN 94 => YF <=14; WHEN 95 => YF <=18; WHEN 96 => YF <=18; WHEN 97 => YF <=21; WHEN 98 => YF <=21; WHEN 99 => YF <=12; WHEN 100 => YF <=12; WHEN 101 => YF <=12; WHEN 102 => YF <=12;WHEN 104 => YF <=0; WHEN 105 => YF <=16; WHEN 106 => YF <=16; WHEN 107 => YF <=19; WHEN 108 => YF <=19; WHEN 109 => YF <=21; WHEN 110 => YF <=21; WHEN 111 => YF <=19; WHEN 112 => YF <=19; WHEN 113 => YF <=15; WHEN 114 => YF <=15; WHEN 115 => YF <=6; WHEN 116 => YF <=6; WHEN 117 => YF <=6; WHEN 118 => YF <=6; WHEN 119 => YF <=0; WHEN 120 => YF <=6; WHEN 121 => YF <=8; WHEN 122 => YF <=8; WHEN 123 => YF <=8; WHEN 124 => YF <=8;WHEN 126 => YF <=8; WHEN 127 => YF <=0; WHEN 128 => YF <=6; WHEN 129 => YF <=8; WHEN 130 => YF <=8; WHEN 131 => YF <=8; WHEN 132 => YF <=8; WHEN 133 => YF <=8; WHEN 134 => YF <=0; WHEN 135 => YF <=8; WHEN 136 => YF <=6; WHEN 137 => YF <=8; WHEN 138 => YF <=8; WHEN 139 => YF <=8; WHEN 140 => YF <=8; WHEN 141 => YF <=8; WHEN 142 => YF <=6; WHEN 143 => YF <=6; WHEN 144 => YF <=6; WHEN 145 => YF <=6; WHEN 146 => YF <=6;WHEN 148 => YF <=8; WHEN 149 => YF <=6; WHEN 150 => YF <=11; WHEN 151 => YF <=11; WHEN 152 => YF <=11; WHEN 153 => YF <=11; WHEN 154 => YF <=11; WHEN 155 => YF <=0; WHEN 156 => YF <=10; WHEN 157 => YF <=9; WHEN 158 => YF <=10; WHEN 159 => YF <=10; WHEN 160 => YF <=10; WHEN 161 => YF <=10; WHEN 162 => YF <=0; WHEN 163 => YF <=8; WHEN 164 => YF <=8; WHEN 165 => YF <=9; WHEN 166 => YF <=8; WHEN 167 => YF <=9; WHEN 168 => YF <=9;WHEN 169 => YF <=9;WHEN 170 => YF <=9;WHEN 171 => YF <=9;WHEN 172 => YF <=9;WHEN 173 => YF <=9;WHEN 174 => YF <=10;WHEN 175 => YF <=10;WHEN OTHERS => NULL;END CASE;END PROCESS;END NAME;100进制计数器LIBRARY ieee ;USE ieee.std_logic_1164.All ;USE ieee.std_logic_unsigned.ALL ;ENTITY count100 ISPORT<clk:IN std_logic;q:OUT std_logic_vector<6 DOWNTO 0>;co:OUT std_logic>;END count100;ARCHITECTURE bhv of count100 ISSIGNAL cq:std_logic_vector<6 DOWNTO 0>;BEGINPROCESS<clk>BEGINIF <clk'event AND clk='1'> THENIF <cq="1100100"> THEN cq<="0000000";ELSE cq<=cq+1;END IF ;END IF ;q<=cq;END PROCESS ;END bhv;。

VHDL Quartus 循环LED彩灯控制器源代码--设计一个循环彩灯控制器--该控制器控制红，绿，黄三个发光二极管循环发亮--要求红发光管亮2秒，绿亮3秒，黄亮1秒。

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ASM_LED ISPORT(CLR: IN STD_LOGIC;--清零控制输入CLK: IN STD_LOGIC;--时钟输入LED1:OUT STD_LOGIC;--LED1输出LED2:OUT STD_LOGIC;--LED2输出LED3:OUT STD_LOGIC);--LED3输出END ASM_LED;--实体名称可以省略---------------------------------------------ARCHITECTURE A OF ASM_LED ISTYPE STATE_TYPE IS (S0,S1,S2,S3,S4,S5,S6);--枚举类型，SIGNAL PRESENT_STATE,NEXT_STATE: STATE_TYPE;--定义信号BEGIN----------------------------------P1:PROCESS(CLK,CLR)--进程1，判断时钟端与清零端，从而得到当前状态BEGIN--开始IF CLR='1' THEN --如果清零端有效PRESENT_STATE<=S0;--当前状态就为S0ELSIF CLK'EVENT AND CLK='1' THEN--如果有上升沿到来PRESENT_STATE<=NEXT_STATE;--当前状态就变为下一个状态END IF;END PROCESS P1;---------------------------------------P2:PROCESS(CLK,PRESENT_STATE)--进程2，BEGINCASE PRESENT_STATE ISWHEN S0=>NEXT_STATE<=S1;WHEN S1=>NEXT_STATE<=S2;WHEN S2=>NEXT_STATE<=S3;WHEN S3=>NEXT_STATE<=S4;WHEN S4=>NEXT_STATE<=S5;WHEN S5=>NEXT_STATE<=S6;WHEN S6=>NEXT_STATE<=S1;END CASE;END PROCESS P2;--------------------------------------P3:PROCESS(CLR,PRESENT_STATE)--进程3BEGINIF CLR='1' THEN--如果清零端有效LED1<='0';LED2<='0';LED3<='0';--把灯全部清零ELSECASE PRESENT_STATE ISWHEN S0=>LED1<='0';LED2<='0';LED3<='0';--第一个状态WHEN S1=>LED1<='1';LED2<='0';LED3<='0';--LED1(黄色发光管点亮1秒）WHEN S2=>LED1<='0';LED2<='1';LED3<='0';--LED2(红色发光管点亮2秒）WHEN S3=>LED1<='0';LED2<='1';LED3<='0';--重复1次，所以总共是2秒WHEN S4=>LED1<='0';LED2<='0';LED3<='1';--LED3(绿色发光管点亮3秒)WHEN S5=>LED1<='0';LED2<='0';LED3<='1';--重复1次，所以总共是2秒WHEN S6=>LED1<='0';LED2<='0';LED3<='1';--再重复1次，所以总共是3秒END CASE;END IF;END PROCESS P3;END A;。

十五计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fiveteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END fiveteencout;ARCHITECTURE counter OF fiveteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1110") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十四计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fourteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END fourteencout;ARCHITECTURE counter OF fourteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1101") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1');-- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1');--WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1');--WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十三计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY thireteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END thireteencout;ARCHITECTURE counter OF thireteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1100") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1');--WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1');--WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十二计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY twelvecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END twelvecout;ARCHITECTURE counter OF twelvecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1011") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1');--WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十一计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY elevencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END elevencout;ARCHITECTURE counter OF elevencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1010") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY count ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END count;ARCHITECTURE counter OF count ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1001") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;九计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY ninecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0)); END ninecout;ARCHITECTURE counter OF ninecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1000") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;八计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY eightcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(2 downto 0)); END eightcout;ARCHITECTURE counter OF eightcout ISSIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="111") THENcount_int<="000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1');-- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1');--WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1');--WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;六计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY sixcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(2 downto 0));END sixcout;ARCHITECTURE counter OF sixcout IS SIGNAL count_int:std_logic_vector(0 to 2); BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="101") THENcount_int<="000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1');-- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1');--WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1');--WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;四计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fourcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(1 downto 0)); END fourcout;ARCHITECTURE counter OF fourcout ISSIGNAL count_int:std_logic_vector(0 to 1);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="11") THENcount_int<="00";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;Welcome !!! 欢迎您的下载，资料仅供参考！。

交通灯控制器的设计智能交通灯控制器的源程序如下：library ieee;use ieee.std_logic_1164.all;entity traffic_control isport( clk: in std_logic;sense0,sense1: in std_logic; --分别为东西路和南北路车辆指示器counter: out integer range 0 to 44;r0,y0,g0: out std_logic; --r0，y0，g0为南北路的红、黄、绿灯r1,y1,g1:out std_logic); --r1，y1，g1为东西路的红、黄、绿灯end;architecture art of traffic_control2 issignal state:std_logic_vector(1 downto 0);signal cnt:integer range 0 to 44;beginprocess(clk)variable nclr,en:bit; --nclr为倒计时计数器清零端，en为计数器使能端beginif clk'event and clk='1' thenif nclr='0' thencnt<=0; --同步清零elsif en='0'thencnt<=cnt; --计数器停止计数elsecnt<=cnt+1; --计数器值增加end if;case state iswhen "00"=>r0<='1';y0<='0';g0<='0';r1<='0';y1<='0';g1<='1';if(sense0 and sense1)='1' then --东西道和南北道都有车if cnt=44 thenstate<="01";nclr:='0';en:='0';elsestate<="00";nclr:='1';en:='1';end if;elsif(sense0 and (not sense1))='1' then --东西道有车，南北道无车state<="01";nclr:='0';en:='0';elsestate<="00";nclr:='1';en:='1';end if;when "01"=>r0<='1';y0<='0';g0<='0';r1<='0';y1<='1';g1<='0';if cnt=5 thenstate<="10";nclr:='0';en:='0';elsestate<="01";nclr:='1';en:='1';end if;when "10"=>r0<='0';y0<='0';g0<='1';r1<='1';y1<='0';g1<='0';if(sense0 and sense1)='1' then --东西道和南北道都有车if cnt=29 thenstate<="11";nclr:='0';en:='0';elsestate<="10";nclr:='1';en:='1';end if;elsif sense0 ='0' then --东西道有车，南北道无车state<="11";nclr:='0';en:='0';elsestate<="10";nclr:='1';en:='1';end if;when "11"=>r0<='1';y0<='1';g0<='0';r1<='1';y1<='0';g1<='0';if cnt=5 thenstate<="00";nclr:='0';en:='0';elsestate<="11";nclr:='1';en:='1';end if;end case;end if;end process;counter<=cnt;end art;。

---------------------------------------Title:交通灯控制器----Author:Pan Hongtao ----Data: 2006-10-1 ---------------------------------------library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;--------------------------------------------------------------------entity exp18 isport( Clk : in std_logic; --时钟输入Rst : in std_logic; --复位输入R1,R2 : out std_logic; --红灯输出Y1,Y2 : out std_logic; --黄灯输出G1,G2 : out std_logic; --绿灯输出Display : out std_logic_vector(6 downto 0); --七段码管显示输出SEG_SEL : buffer std_logic_vector(2 downto 0) --七段码管扫描驱动);end exp18;--------------------------------------------------------------------architecture behave of exp18 issignal Disp_Temp : integer range 0 to 15;signal Disp_Decode : std_logic_vector(6 downto 0);signal SEC1,SEC10 : integer range 0 to 9;signal Direction : integer range 0 to 15;signal Clk_Count1 : std_logic_vector(9 downto 0); --产生0.5Hz时钟的分频计数器signal Clk1Hz : std_logic;signal Dir_Flag : std_logic; --方向标志beginprocess(Clk)beginif(Clk'event and Clk='1') thenif(Clk_Count1<1000) thenClk_Count1<=Clk_Count1+1;elseClk_Count1<="0000000001";end if;end if;end process;Clk1Hz<=Clk_Count1(9);process(Clk1Hz,Rst)beginif(Rst='0') thenSEC1<=0;SEC10<=2;Dir_Flag<='0';elsif(Clk1Hz'event and Clk1Hz='1') thenif(SEC1=0) thenSEC1<=9;if(SEC10=0) thenSEC10<=1;elseSEC10<=SEC10-1;end if;elseSEC1<=SEC1-1;end if;if(SEC1=0 and SEC10=0) thenDir_Flag<=not Dir_Flag;end if;end if;end process;process(Clk1Hz,Rst)beginif(Rst='0') thenR1<='1';G1<='0';R2<='1';G2<='0';else --正常运行if(SEC10>0 or SEC1>3) thenif(Dir_Flag='0') then --横向通行R1<='0';G1<='1';R2<='1';G2<='0';elseR1<='1';G1<='0';R2<='0';G2<='1';end if;elseif(Dir_Flag='0') then --横向通行R1<='0';G1<='0';R2<='1';G2<='0';elseR1<='1';G1<='0';R2<='0';G2<='0';end if;end if;end if;end process;process(Clk1Hz)beginif(SEC10>0 or SEC1>3) thenY1<='0';Y2<='0';elsif(Dir_Flag='0') thenY1<=Clk1Hz;Y2<='0';elseY1<='0';Y2<=Clk1Hz;end if;end process;process(Dir_Flag)beginif(Dir_Flag='0') then --横向Direction<=10;else --纵向Direction<=11;end if;end process;process(SEG_SEL)begincase (SEG_SEL+1) iswhen "000"=>Disp_Temp<=Direction;when "001"=>Disp_Temp<=Direction;when "010"=>Disp_Temp<=SEC10;when "011"=>Disp_Temp<=SEC1;when "100"=>Disp_Temp<=Direction;when "101"=>Disp_Temp<=Direction;when "110"=>Disp_Temp<=SEC10;when "111"=>Disp_Temp<=SEC1;end case;end process;process(Clk)beginif(Clk'event and Clk='1') then --扫描累加SEG_SEL<=SEG_SEL+1;Display<=Disp_Decode;end if;end process;process(Disp_Temp) --显示转换begincase Disp_Temp iswhen 0=>Disp_Decode<="0111111"; --'0'when 1=>Disp_Decode<="0000110"; --'1'when 2=>Disp_Decode<="1011011"; --'2'when 3=>Disp_Decode<="1001111"; --'3'when 4=>Disp_Decode<="1100110"; --'4'when 5=>Disp_Decode<="1101101"; --'5'when 6=>Disp_Decode<="1111101"; --'6'when 7=>Disp_Decode<="0000111"; --'7'when 8=>Disp_Decode<="1111111"; --'8'when 9=>Disp_Decode<="1101111"; --'9'when 10=>Disp_Decode<="1001000"; --'='when 11=>Disp_Decode<="0010100"; --'||'when others=>Disp_Decode<="0000000"; --全灭end case;end process;end behave;。