2位2进制计数器vhdl代码

将8421BCD转换为余3码源代码：Library ieee;Use ieee.std_logic_1164.all;Entity bcd isPort(a:in std_logic_vector(3 downto 0);y:out std_logic_vector(3 downto 0));End;Architecture rtl of bcd isBeginProcess(a)BeginCase a isWhen"0000"=>y<="0011";When"0001"=>y<="0100";When"0010"=>y<="0101";When"0011"=>y<="0110";When"0100"=>y<="0111";When"0101"=>y<="1000";When"0110"=>y<="1001";When"0111"=>y<="1010";When"1000"=>y<="1011";When"1001"=>y<="1100";When others=>y<="ZZZZ";End case;End process;End;仿真图形：（仿真结果均有延时，大约20ns）四输入表决器源代码：Library ieee;Use ieee.std_logic_1164.all;Entity bjq isPort(i:in std_logic_vector(3 downto 0);f:out std_logic);End;Architecture nm2 of bjq isBeginProcess(i)Begincase i isWhen"0000"=>f<='0';When"0001"=>f<='0';When"0010"=>f<='0';When"0011"=>f<='0';When"0100"=>f<='0';When"0101"=>f<='0';When"0110"=>f<='0';When"0111"=>f<='1';When"1000"=>f<='0';When"1001"=>f<='0';When"1010"=>f<='0';When"1011"=>f<='1';When"1100"=>f<='0';When"1101"=>f<='1';When"1110"=>f<='1';When"1111"=>f<='1';When others=>f<='Z';End case;End process;End;仿真图形：2位二进制相乘电路源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity multi isport(A,B:in std_logic_vector(1 downto 0);F:out std_logic_vector(3 downto 0));end;architecture bhv of multi isbeginprocess(A,B)beginif(A="01" and B="01" )thenF<="0001";elsif(A="01" and B="10")thenF<="0010";elsif(A="01" and B="11")thenF<="0011";elsif(A="10" and B="01")thenF<="0010";elsif(A="10" and B="10")thenF<="0100";elsif(A="10" and B="11")thenF<="0110";elsif(A="11" and B="01")thenF<="0011";elsif(A="11" and B="10")thenF<="0110";elsif(A="11" and B="11")thenF<="1001";elseF<="0000";end if;end process;end;仿真图形：一位二进制全减器源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity subtracter isport(A,B,Ci:in std_logic;F,Co:out std_logic);end;architecture bhv of subtracter isbeginprocess(A,B,Ci)beginif(A='0' and B='0' and Ci='0')thenF<='0';Co<='0';elsif(A='0' and B='0' and Ci='1')thenF<='1';Co<='1';elsif(A='0' and B='1' and Ci='0')thenF<='1';Co<='1';elsif(A='0' and B='1' and Ci='1')thenF<='0';Co<='1';elsif(A='1' and B='0' and Ci='0')thenF<='1';Co<='0';elsif(A='1' and B='0' and Ci='1')thenF<='0';Co<='0';elsif(A='1' and B='1' and Ci='0')thenF<='0';Co<='0';elseF<='1';Co<='1';end if;end process;end;仿真图形：开关控制电路源代码：Library ieee;Use ieee.std_logic_1164.all;Entity switch_control isPort(a,b,c:in std_logic;y:out std_logic);End;Architecture nm5 of switch_control isBeginProcess(a,b,c);V ariable comb:std_logic_vector(2 downto 0);BeginComb:=a&b&c;Case comb isWhen"000"=>y<='0';When"001"=>y<='1';When"011"=>y<='0';When"010"=>y<='1';When"110"=>y<='0';When"111"=>y<='1';When"101"=>y<='0';When"100"=>y<='1';When others=>y<='X';End case;End process;End;仿真图形：。

期刊论文—EDA课程设计题目：计数器的VHDL设计与实现学生姓名：李雷学生学号：09专业班级：计算机科学与技术0902班指导老师：方恺晴计数器的VHDL设计与实现摘要：介绍了各种基本计数器的组成及其工作原理，重点研究了可变模计数器的设计与实现，在对现有的可变模计数器的研究基础上,在Quartus 开发环境中，用VHDL语言设计一种功能更加强大的可变模计数器，它具有清零、置数、使能控制、可逆计数和可变模等功能，并且对传统的可变模计数器的计数失控问题进行研究,最终设计出一种没有计数失控缺陷的可变模计数器，并通过波形仿真和EPF10K20TI144—4系列实验箱，验证了其各项设计功能。

结果表明该设计正确．功能完整。

运行稳定.关键词：VHDL；计数器；可变模计数;可逆计数VHDL Design and Realization of CounterAbstract：This paper analyzes all kinds of basic counter and its working principle， focus on the counter variable mode of design and implementation。

In the environment of Quartus based on research of the existing module—alterable counter，a module—alterable counter with more functions，such as clear，set，enable control，reversible count，module—alterable count and so on,which is designedwith VHDL．By researching the problem of losing control existed in traditional module—alterable counter。

vhdl语言100例程序以下是100个关于VHDL语言的程序示例：1. 用VHDL编写一个计数器模块2. 用VHDL编写一个SR-Latch模块3. 用VHDL编写一个JK-Flip Flop模块4. 用VHDL编写一个D-Flip Flop模块5. 用VHDL编写一个T-Flip Flop模块6. 用VHDL编写一个复位计数器模块7. 用VHDL编写一个移位寄存器模块8. 用VHDL编写一个状态机模块9. 用VHDL编写一个MUX模块10. 用VHDL编写一个DeMUX模块11. 用VHDL编写一个加法器模块12. 用VHDL编写一个减法器模块13. 用VHDL编写一个乘法器模块14. 用VHDL编写一个除法器模块15. 用VHDL编写一个比较器模块16. 用VHDL编写一个位逻辑模块17. 用VHDL编写一个字逻辑模块18. 用VHDL编写一个数据选择器模块19. 用VHDL编写一个FIFO队列模块20. 用VHDL编写一个LIFO栈模块21. 用VHDL编写一个流水线模块22. 用VHDL编写一个中断控制器模块23. 用VHDL编写一个时钟分频器模块24. 用VHDL编写一个IO控制器模块25. 用VHDL编写一个SPI通信控制器模块26. 用VHDL编写一个I2C通信控制器模块27. 用VHDL编写一个UART通信控制器模块28. 用VHDL编写一个哈希函数模块29. 用VHDL编写一个随机数产生器模块30. 用VHDL编写一个CRC校验器模块31. 用VHDL编写一个AES加密算法模块32. 用VHDL编写一个DES加密算法模块33. 用VHDL编写一个SHA加密算法模块34. 用VHDL编写一个MD5加密算法模块35. 用VHDL编写一个RSA加密算法模块36. 用VHDL编写一个卷积滤波器模块37. 用VHDL编写一个峰值检测器模块38. 用VHDL编写一个平滑滤波器模块39. 用VHDL编写一个中值滤波器模块40. 用VHDL编写一个微处理器模块41. 用VHDL编写一个信号发生器模块42. 用VHDL编写一个信号采集器模块43. 用VHDL编写一个频率计算器模块44. 用VHDL编写一个相位计算器模块45. 用VHDL编写一个时序分析器模块46. 用VHDL编写一个正弦波产生器模块47. 用VHDL编写一个余弦波产生器模块48. 用VHDL编写一个数字滤波器模块49. 用VHDL编写一个数字信号处理器模块50. 用VHDL编写一个数字识别模块51. 用VHDL编写一个自动售货机模块52. 用VHDL编写一个二进制加法器模块53. 用VHDL编写一个二进制减法器模块54. 用VHDL编写一个二进制乘法器模块55. 用VHDL编写一个二进制除法器模块56. 用VHDL编写一个自然对数模块57. 用VHDL编写一个指数函数模块58. 用VHDL编写一个三角函数模块59. 用VHDL编写一个高斯滤波器模块60. 用VHDL编写一个激光传感器模块61. 用VHDL编写一个超声波传感器模块62. 用VHDL编写一个光电传感器模块63. 用VHDL编写一个温度传感器模块64. 用VHDL编写一个气压传感器模块65. 用VHDL编写一个陀螺仪模块67. 用VHDL编写一个电流传感器模块68. 用VHDL编写一个电容传感器模块69. 用VHDL编写一个磁场传感器模块70. 用VHDL编写一个通信电缆模块71. 用VHDL编写一个电源控制器模块72. 用VHDL编写一个电机控制器模块73. 用VHDL编写一个汽车控制器模块74. 用VHDL编写一个飞机控制器模块75. 用VHDL编写一个摄像头模块76. 用VHDL编写一个音频控制器模块77. 用VHDL编写一个扬声器控制器模块78. 用VHDL编写一个拨号器模块79. 用VHDL编写一个振动控制器模块80. 用VHDL编写一个压力控制器模块81. 用VHDL编写一个过滤器模块82. 用VHDL编写一个微波发射模块84. 用VHDL编写一个智能电表模块85. 用VHDL编写一个闹钟模块86. 用VHDL编写一个计时器模块87. 用VHDL编写一个时间戳模块88. 用VHDL编写一个脉冲宽度模块89. 用VHDL编写一个电路仿真模块90. 用VHDL编写一个电路控制模块91. 用VHDL编写一个电路测试模块92. 用VHDL编写一个电路优化模块93. 用VHDL编写一个电路布局模块94. 用VHDL编写一个电路验证模块95. 用VHDL编写一个数字信号发生器模块96. 用VHDL编写一个数字信号反演器模块97. 用VHDL编写一个数字信号滤波器模块98. 用VHDL编写一个数字信号加速器模块99. 用VHDL编写一个数字信号降噪器模块100. 用VHDL编写一个数字信号解调器模块VHDL语言是一种硬件描述语言，它用于描述数字电路和系统。

LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY cal1 ISPORT (inclk: IN STD_LOGIC;--num: IN STD_LOGIC_VECTOR(9 DOWNTO 0);--plus: IN STD_LOGIC; --加法按键--subt: IN STD_LOGIC; --减法按键--mult: IN STD_LOGIC; --乘法按键--mdiv: IN STD_LOGIC; --除法按键--equal: IN STD_LOGIC; --等号键--c: IN STD_LOGIC; --清零键num1: out STD_LOGIC_VECTOR(3 DOWNTO 0);--colnum2: in STD_LOGIC_VECTOR(3 DOWNTO 0);--row fan--onum1,onum2,onum3,onum4,onum5,onum6: OUT STD_LOGIC_VECTOR(0 TO 6);CAT: OUT STD_LOGIC_VECTOR(5 DOWNTO 0); --选通端，用6个数码管。

最左侧数码管表示正负，从-99999到99999DIGITAL:OUT STD_LOGIC_VECTOR(6 DOWNTO 0) --控制数码管显示不同的数字); --3个7段译码显示管END cal1;ARCHITECTURE behave OF cal1 IS--TYPE state IS (takenum,tenthousand,thousand,hundred,ten,one);SIGNAL result1: integer range -99999 to 99999; --分位显示的暂存器SIGNAL flag: STD_LOGIC; --是否是第一次输入数字的标志符SIGNAL f1: STD_LOGIC; --是否开始输入第二个数字的标志--SIGNAL viewstep: state;SIGNAL acc: integer range 0 to 99; --存放第一个数字的累加器SIGNAL reg: integer range 0 to 99; --存放第二个以及以后数字的寄存器SIGNAL keep:integer range -99999 to 99999; --存放显示数字的寄存器SIGNAL ans: integer range -99999 to 99999; --存放各步计算结果的寄存器--SIGNAL dans: STD_LOGIC_VECTOR(3 DOWNTO 0); --存放除法结果的寄存器SIGNAL numbuff: integer range 0 to 15; --输入数字缓冲SIGNAL vf: STD_LOGIC; --表示是否最后结果--SIGNAL strdiv: STD_LOGIC; --除法计算开始的信号SIGNAL numclk: STD_LOGIC; --将数字从缓存放入累加器或寄存器SIGNAL clear: STD_LOGIC; --清除累加器中的信号SIGNAL inplus: STD_LOGIC; --同步加信号SIGNAL insubt: STD_LOGIC; --同步减信号SIGNAL inmult: STD_LOGIC; --同步乘信号--SIGNAL inmdiv: STD_LOGIC; --同步除信号SIGNAL inequal: STD_LOGIC; --同步等于信号--SIGNAL view1,view2,view3,view4,view5: STD_LOGIC_VECTOR(3 DOWNTO 0); --分位的显示SIGNAL cou: STD_LOGIC_VECTOR(1 DOWNTO 0); --用力记忆是第几次--计算的信号SIGNAL clk_gg: STD_LOGIC_VECTOR(11 DOWNTO 0); --用于产生分频时钟的信号--SIGNAL CNT : INTEGER RANGE 0 TO 50000;--分频用SIGNAL clk: STD_LOGIC; --分频后的时钟信号--signal ko : integer range 0 to 15;SIGNAL CAT0:INTEGER RANGE 0 TO 10; --数码管显示5位数，共有5个CAT选通端SIGNAL CAT1:INTEGER RANGE 0 TO 10;SIGNAL CAT2:INTEGER RANGE 0 TO 10;SIGNAL CAT3:INTEGER RANGE 0 TO 10;SIGNAL CAT4:INTEGER RANGE 0 TO 10;TYPE TIME_TYPE IS (T1,T2,T3,T4,T5,T6);SIGNAL TIME1:TIME_TYPE;--COMPONENT numdecoder IS --引用数字按键的译码电路--PORT ( reset: IN STD_LOGIC;--inclk: IN STD_LOGIC;--innum: IN STD_LOGIC_VECTOR(9 DOWNTO 0);--outnum: BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);--outflag: OUT STD_LOGIC );--END COMPONENT;component keyboard ISPORT(--clk:in std_logic; ---时钟信号--row_scan :out STD_LOGIC_vector(3 downto 0); ---行扫描输出信号--col_scan :in std_logic_vector(3 downto 0);---列扫描输入信号--key_output :out std_logic_vector(3 downto 0);--key_down :out std_logic;--keyout :out integer range 0 to 15;--SYS_CLK : in std_logic;-- KEY_ROW : in std_logic_vector(3 downto 0); --4*4键盘扫描4输入--KEY_COL : out std_logic_vector(3 downto 0); --4*4键盘扫描4输出--KEY_DATA : out std_logic_vector(3 downto 0); --输出键值，-- KEY_READY : out std_logicKEY_CLK : in std_logic;KEY_ROW : in std_logic_vector(3 downto 0); --4*4键盘扫描4输入KEY_COL : out std_logic_vector(3 downto 0); --4*4键盘扫描4输出--KEY_DATA : out std_logic_vector(3 downto 0); --输出键值，--KEY_READY : out std_logicKEY_DOWN :out std_logic;KEY_OUT :out integer range 0 to 15);end component;--COMPONENT vdecode IS --引用7段译码器--PORT(indata:IN STD_LOGIC_VECTOR(3 DOWNTO 0);-- outdata:OUT STD_LOGIC_VECTOR(0 TO 6));--END COMPONENT;--COMPONENT diver IS --引用除法器--PORT( a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);-- b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);-- clk: IN STD_LOGIC;--str: IN STD_LOGIC;--s: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);-- y: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)--);--END COMPONENT;BEGIN--inum1: numdecoder port map(c,clk,num,numbuff,numclk);--inum2:keyboard44 port map(clk,num1,num2,numbuff,numclk,ko);inum2:keyboard port map(inclk,num2,num1,numclk,numbuff);clock: PROCESS(inclk,numbuff) --进程clock用于产生分频的时钟，使得12位向量clk_gg不断加1，然后输出12位中的某一位BEGINIF inclk'EVENT AND inclk='1' thenclk_gg(11 DOWNTO 0)<=clk_gg(11 DOWNTO 0)+1;END IF;END PROCESS clock;clk<=clk_gg(11);pacecal: PROCESS(numbuff,clk)BEGINIF (rising_edge(clk) and numbuff=15) theninplus<='0';insubt<='0';inmult<='0';--inmdiv<='0';ELSIF clk'EVENT AND clk='1' thenIF numbuff=10 theninplus<='1'; insubt<='0';inmult<='0';--inmdiv<='0';ELSIF numbuff=11 theninplus<='0';insubt<='1';inmult<='0';--inmdiv<='0';ELSIF numbuff=12 theninplus<='0';insubt<='0';inmult<='1';--inmdiv<='0';-- ELSIF mdiv='1' then-- inplus<='0';insubt<='0';inmult<='0';inmdiv<='1';END IF;END IF;END PROCESS pacecal;ctrflag: PROCESS(numbuff,clk) --用于产生flag信号BEGINIF (rising_edge(clk) and numbuff=15) thenflag<='0';ELSIF clk'EVENT AND clk='1' thenIF inplus='1' OR insubt='1' OR inmult='1' --OR inmdiv='1'THENflag<='1';ELSE flag<='0';END IF;END IF;END PROCESS ctrflag;ctrfirstnum: PROCESS(numbuff,numclk) --用于输入第一个运算数BEGINIF ( numbuff=15) thenacc<=0;ELSIF numclk'EVENT AND numclk='1' thenIF flag='0' thenacc<=acc*10+numbuff;END IF;END IF;END PROCESS ctrfirstnum;ctrsecondnum:PROCESS(numbuff,clear,numclk) --用于输入第二个以后的运算数字BEGINIF ( numbuff=15 OR clear='1')THENreg<=0;f1<='0';ELSIF numclk'event AND numclk='1'THENIF flag='1'THENf1<='1';reg<=reg*10+numbuff;END IF;END IF;END PROCESS ctrsecondnum;ctrclear: PROCESS(numbuff,clk) --用于产生clear信号为什么c和clear不同步反BEGINIF (numbuff=15)thenclear<='0';ELSIF clk'EVENT AND clk='1' thenIF numbuff=10 or numbuff=11 or numbuff=12 thenclear<='1';ELSE clear<='0';END IF;END IF;END PROCESS ctrclear;ctrinequal:PROCESS(numbuff,clk) --用于产生inequal信号BEGINIF (numbuff=15) theninequal<='0';ELSIF clk'EVENT AND clk='1' thenIF numbuff=10 or numbuff=11 or numbuff=12 or numbuff=14 theninequal<='1';ELSE inequal<='0';END IF;END IF;END PROCESS ctrinequal;ctrcou: process (numbuff,inequal) --用于产生cou信号什么意思？BEGINIF (numbuff=15 )thencou<="00";ELSIF inequal'EVENT and inequal='1'thenIF cou="10" thencou<=cou;ELSE cou<=cou+1;END IF;END IF;END PROCESS ctrcou;ctrcal: PROCESS (numbuff,inequal) --用于实现运算BEGINIF ( numbuff=15 ) thenans<=0;--strdiv<='0';ELSIF inequal'EVENT and inequal='1' thenIF flag='1' thenIF inplus='1' thenIF cou="10" thenans<=ans+reg;ELSE ans<=acc+reg;END IF;ELSIF insubt='1'THENIF cou="10"THENans<=ans-reg;ELSE ans<=acc-reg;END IF;ELSIF inmult='1' then--IF acc<="1111111" AND reg<="1111111" then--将乘数和被乘数限制在4位二进制数范围内IF cou="10" thenans<=ans*reg;ELSE ans<=acc*reg;END IF;--ELSE ans<=0;-- END IF;--ELSIF inmdiv='1'THEN--strdiv<='1';END IF;--else strdiv<='0';END IF;END IF;END PROCESS ctrcal;--d1:diver PORT MAP (acc,reg(3 DOWNTO 0),clk,strdiv,dans);--将除法结果放在dans中ctrvf: PROCESS(numbuff,clk) --用来产生vf信号BEGINIF (rising_edge(clk) and numbuff=15) thenvf<='0';ELSIF (rising_edge(clk) and numbuff=14) thenvf<='1';END IF;END PROCESS ctrvf;ctrkeep: process(numbuff,clk) --用于控制keep寄存器BEGINIF (numbuff=15) then --keep寄存器清零keep<=0;ELSIF clk'EVENT AND clk='1' thenIF flag='0' then --输入第二个数以前keep中存放acc中的数keep<=acc;ELSIF flag='1' AND f1='1' AND vf='0' then--输入第二个数以前keep中存放reg中的数keep<=reg;ELSIF flag='1' AND f1='0'AND vf='0'AND cou="10" then--keep中存放ans中的内容keep<=ans;ELSIF flag='1'and vf='1'then --最终的计算结果-- IF inmdiv='0'THENkeep<=ans;-- ELSE-- keep(3 DOWNTO 0)<=dans;--END IF;END IF;END IF;END PROCESS ctrkeep;ctrview:PROCESS(numbuff,clk)BEGINIF (rising_edge(clk) and numbuff=15) THENcat4<=0; cat3<=0;cat2<=0;cat1<=0;cat0<=0;ELSIF clk'EVENT AND clk='1'THENif(keep<0)then result1<=abs(keep);else result1<=keep;end if;if(result1>99999 )then cat4<=10; cat3<=10;cat2<=10;cat1<=10;cat0<=10;end if;if(result1>=90000 and result1<=99999)then cat4<=9;elsif(result1>=80000 and result1<90000)then cat4<=8;elsif(result1>=70000 and result1<80000)then cat4<=7;elsif(result1>=60000 and result1<70000)then cat4<=6;elsif(result1>=50000 and result1<60000)then cat4<=5;elsif(result1>=40000 and result1<50000)then cat4<=4;elsif(result1>=30000 and result1<40000)then cat4<=3;elsif(result1>=20000 and result1<30000)then cat4<=2;elsif(result1>=10000 and result1<20000)then cat4<=1;elsif(result1<10000 )then cat4<=0;end if;if((result1-cat4*10000)>=9000 and (result1-cat4*10000)<10000)then cat3<=9;elsif((result1-cat4*10000)>=8000 and (result1-cat4*10000)<9000)then cat3<=8;elsif((result1-cat4*10000)>=7000 and (result1-cat4*10000)<8000)then cat3<=7;elsif((result1-cat4*10000)>=6000 and (result1-cat4*10000)<7000)then cat3<=6;elsif((result1-cat4*10000)>=5000 and (result1-cat4*10000)<6000)then cat3<=5;elsif((result1-cat4*10000)>=4000 and (result1-cat4*10000)<5000)then cat3<=4;elsif((result1-cat4*10000)>=3000 and (result1-cat4*10000)<4000)then cat3<=3;elsif((result1-cat4*10000)>=2000 and (result1-cat4*10000)<3000)then cat3<=2;elsif((result1-cat4*10000)>=1000 and (result1-cat4*10000)<2000)then cat3<=1;elsif((result1-cat4*10000)<1000)then cat3<=0;end if;if((result1-cat4*10000-cat3*1000)>=900and (result1-cat4*10000-cat3*1000)<1000)then cat2<=9;elsif((result1-cat4*10000-cat3*1000)>=800and (result1-cat4*10000-cat3*1000)<900)then cat2<=8;elsif((result1-cat4*10000-cat3*1000)>=700and (result1-cat4*10000-cat3*1000)<800)then cat2<=7;elsif((result1-cat4*10000-cat3*1000)>=600and (result1-cat4*10000-cat3*1000)<700)then cat2<=6;elsif((result1-cat4*10000-cat3*1000)>=500and (result1-cat4*10000-cat3*1000)<600)thencat2<=5;elsif((result1-cat4*10000-cat3*1000)>=400and (result1-cat4*10000-cat3*1000)<500)then cat2<=4;elsif((result1-cat4*10000-cat3*1000)>=300and (result1-cat4*10000-cat3*1000)<400)then cat2<=3;elsif((result1-cat4*10000-cat3*1000)>=200and (result1-cat4*10000-cat3*1000)<300)then cat2<=2;elsif((result1-cat4*10000-cat3*1000)>=100and (result1-cat4*10000-cat3*1000)<200)then cat2<=1;elsif((result1-cat4*10000-cat3*1000)<100) then cat2<=0;end if;if((result1-cat4*10000-cat3*1000-cat2*100)>=90and(result1-cat4*10000-cat3*1000-cat2*100)<100)then cat1<=9;elsif((result1-cat4*10000-cat3*1000-cat2*100)>=80and(result1-cat4*10000-cat3*1000-cat2*100)<90)then cat1<=8;elsif((result1-cat4*10000-cat3*1000-cat2*100)>=70and(result1-cat4*10000-cat3*1000-cat2*100)<80)then cat1<=7;elsif((result1-cat4*10000-cat3*1000-cat2*100)>=60and(result1-cat4*10000-cat3*1000-cat2*100)<70)then cat1<=6;elsif((result1-cat4*10000-cat3*1000-cat2*100)>=50and(result1-cat4*10000-cat3*1000-cat2*100)<60)then cat1<=5;elsif((result1-cat4*10000-cat3*1000-cat2*100)>=40and(result1-cat4*10000-cat3*1000-cat2*100)<50)then cat1<=4;elsif((result1-cat4*10000-cat3*1000-cat2*100)>=30and(result1-cat4*10000-cat3*1000-cat2*100)<40)then cat1<=3;elsif((result1-cat4*10000-cat3*1000-cat2*100)>=20and(result1-cat4*10000-cat3*1000-cat2*100)<30)then cat1<=2;elsif((result1-cat4*10000-cat3*1000-cat2*100)>=10and(result1-cat4*10000-cat3*1000-cat2*100)<20)then cat1<=1;elsif((result1-cat4*10000-cat3*1000-cat2*100)<10)then cat1<=0;end if;cat0<=result1-cat4*10000-cat3*1000-cat2*100-cat1*10;end if;END PROCESS ctrview;--v1:vdecode PORT MAP (view1,onum1); --7段译码显示百位--v2:vdecode PORT MAP (view2,onum2); --7段译码显示十位--v3:vdecode PORT MAP (view3,onum3); --7段译码显示个位--v4:vdecode PORT MAP (view4,onum4); --7段译码显示十位--v5:vdecode PORT MAP (view5,onum5); --7段译码显示个位xianshi:PROCESS(clk,time1,cat4,cat3,cat2,cat1,cat0)beginIF rising_edge(clk) THENif(keep>=0)thenCASE TIME1 ISWHEN T1 =>CAT <= "101111";CASE CAT4 ISWHEN 0=> DIGITAL <= "1111110";WHEN 1=> DIGITAL <= "0110000";WHEN 2=> DIGITAL <= "1101101";WHEN 3=> DIGITAL <= "1111001";WHEN 4=> DIGITAL <= "0110011";WHEN 5=> DIGITAL <= "1011011";WHEN 6=> DIGITAL <= "1011111";WHEN 7=> DIGITAL <= "1110000";WHEN 8=> DIGITAL <= "1111111";WHEN 9=> DIGITAL <= "1111011";WHEN 10=> DIGITAL <="1001111";END CASE;TIME1 <= T2;WHEN T2 =>CAT <= "110111";CASE CAT3 ISWHEN 0=> DIGITAL <= "1111110";WHEN 1=> DIGITAL <= "0110000";WHEN 2=> DIGITAL <= "1101101";WHEN 3=> DIGITAL <= "1111001";WHEN 4=> DIGITAL <= "0110011";WHEN 5=> DIGITAL <= "1011011";WHEN 6=> DIGITAL <= "1011111";WHEN 7=> DIGITAL <= "1110000";WHEN 8=> DIGITAL <= "1111111";WHEN 9=> DIGITAL <= "1111011";WHEN 10=> DIGITAL <="1000110";END CASE;TIME1 <= T3;WHEN T3 =>CAT <= "111011";CASE CAT2 ISWHEN 0=> DIGITAL <= "1111110";WHEN 1=> DIGITAL <= "0110000";WHEN 2=> DIGITAL <= "1101101";WHEN 3=> DIGITAL <= "1111001"; WHEN 4=> DIGITAL <= "0110011"; WHEN 5=> DIGITAL <= "1011011"; WHEN 6=> DIGITAL <= "1011111"; WHEN 7=> DIGITAL <= "1110000"; WHEN 8=> DIGITAL <= "1111111"; WHEN 9=> DIGITAL <= "1111011"; WHEN 10=> DIGITAL <="1000110"; END CASE;TIME1 <= T4;WHEN T4 =>CAT <= "111101";CASE CAT1 ISWHEN 0=> DIGITAL <= "1111110"; WHEN 1=> DIGITAL <= "0110000"; WHEN 2=> DIGITAL <= "1101101"; WHEN 3=> DIGITAL <= "1111001"; WHEN 4=> DIGITAL <= "0110011"; WHEN 5=> DIGITAL <= "1011011"; WHEN 6=> DIGITAL <= "1011111"; WHEN 7=> DIGITAL <= "1110000"; WHEN 8=> DIGITAL <= "1111111"; WHEN 9=> DIGITAL <= "1111011"; WHEN 10=> DIGITAL <= "1111110"; END CASE;TIME1 <= T5;WHEN T5 =>CAT <= "111110";CASE CAT0 ISWHEN 0=> DIGITAL <= "1111110"; WHEN 1=> DIGITAL <= "0110000"; WHEN 2=> DIGITAL <= "1101101"; WHEN 3=> DIGITAL <= "1111001"; WHEN 4=> DIGITAL <= "0110011"; WHEN 5=> DIGITAL <= "1011011"; WHEN 6=> DIGITAL <= "1011111"; WHEN 7=> DIGITAL <= "1110000"; WHEN 8=> DIGITAL <= "1111111"; WHEN 9=> DIGITAL <= "1111011"; WHEN 10=> DIGITAL <="1000110"; END CASE;TIME1 <= T1;WHEN OTHERS => TIME1 <= T1;END CASE;elsif(keep<0)thenCASE time1 ISWHEN t1 =>cat <= "101111";CASE cat4 ISWHEN 0=> digital <= "1111110";WHEN 1=> digital <= "0110000";WHEN 2=> digital <= "1101101";WHEN 3=> digital <= "1111001";WHEN 4=> digital <= "0110011";WHEN 5=> digital <= "1011011";WHEN 6=> digital <= "1011111";WHEN 7=> digital <= "1110000";WHEN 8=> digital <= "1111111";WHEN 9=> digital <= "1111011";WHEN 10=> DIGITAL <="1001111";END CASE;time1 <= t2;WHEN t2 =>cat <= "110111";CASE cat3 ISWHEN 0=> digital <= "1111110";WHEN 1=> digital <= "0110000";WHEN 2=> digital <= "1101101";WHEN 3=> digital <= "1111001";WHEN 4=> digital <= "0110011";WHEN 5=> digital <= "1011011";WHEN 6=> digital <= "1011111";WHEN 7=> digital <= "1110000";WHEN 8=> digital <= "1111111";WHEN 9=> digital <= "1111011";WHEN 10=> DIGITAL <="1000110";end case;time1 <= t3;WHEN t3 =>cat <= "111011";CASE cat2 ISWHEN 1=> digital <= "0110000"; WHEN 2=> digital <= "1101101"; WHEN 3=> digital <= "1111001"; WHEN 4=> digital <= "0110011"; WHEN 5=> digital <= "1011011"; WHEN 6=> digital <= "1011111"; WHEN 7=> digital <= "1110000"; WHEN 8=> digital <= "1111111"; WHEN 9=> digital <= "1111011"; WHEN 10=> DIGITAL <="1000110"; END CASE;time1 <= t4;WHEN t4 =>cat <= "111101";CASE cat1 ISWHEN 0=> digital <= "1111110"; WHEN 1=> digital <= "0110000"; WHEN 2=> digital <= "1101101"; WHEN 3=> digital <= "1111001"; WHEN 4=> digital <= "0110011"; WHEN 5=> digital <= "1011011"; WHEN 6=> digital <= "1011111"; WHEN 7=> digital <= "1110000"; WHEN 8=> digital <= "1111111"; WHEN 9=> digital <= "1111011"; WHEN 10=> DIGITAL <= "1111110"; END CASE;time1 <= t5;WHEN t5 =>cat <= "111110";CASE cat0 ISWHEN 0=> digital <= "1111110"; WHEN 1=> digital <= "0110000"; WHEN 2=> digital <= "1101101"; WHEN 3=> digital <= "1111001"; WHEN 4=> digital <= "0110011"; WHEN 5=> digital <= "1011011"; WHEN 6=> digital <= "1011111"; WHEN 7=> digital <= "1110000"; WHEN 8=> digital <= "1111111"; WHEN 9=> digital <= "1111011";END CASE;time1 <= t6;when t6=>cat<="011111";digital<="0000001";time1<=t1;WHEN OTHERS => time1 <= t1;END CASE;end if;--end if;--end process;--end lz;end if;end process;END behave;。

实验四计数器的使用一、实验目的熟悉步长可变的加减计数器的工作原理、设计过程和实现方法。

二、实验内容与要求学习用VHDL设计步长可变的加减计数器电路，完成编译、综合、适配、仿真和实验箱上的硬件测试，通过LED数码管显示输入输出各部分数据。

三、实验原理通过输入一组4BIT二进制数据，控制计数方式，即步长，决定每个脉冲到来时计数器增加的数值，同时还有一个单BIT的控制位，选择加计数或者减计数，并通过电路显示各部分数据（输入及输出）。

拨码开关置为MODEL_SEL5-8，全部置为ON，通过USB下载；全部置为OFF，则通过LAB_JTAG_PS_AS接口下载。

DISP_SEL8，处于“ON”状态，这样可以使用静态共阳数码管DISP_SEL1，DISP_SEL2处于“OFF”状态，通过F1，F2的十六进制的输入，在静态共阳数码管DP1B，DP2B上显示输出。

F1，F2预置数据，通过计数器，总的计数值控制电平宽度，其中一组控制高电平，一组控制低电平。

在DP1B上显示的是0-F的步长可变的加减计数器。

四、实验平台（1）硬件：计算机、GX-SOC/SOPC-DEV-LABCycloneII EP2C35F672C8核心板（2）软件：Quartus II软件五、六、仿真截图七、硬件实现八、程序代码1--10 位计数SCAN TOP_LEVEL程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;ENTITY ACOUNT100 ISPORT(clk,clr,en,en6:IN STD_LOGIC ;count1 : out std_logic ;ledseg : out std_logic_vector(6 downto 0);ledcom :out std_logic_vector(5 downto 0)); END;ARCHITECTURE ONE OF ACOUNT100 IS COMPONENT clkgen ISPORT(clkin:IN STD_LOGIC ;clkout: OUT STD_LOGIC);END COMPONENT;COMPONENT COUNT10a ISPORT(clk,clr,en:IN STD_LOGIC ;q:OUT STD_LOGIC_vector(3 downto 0);count1:OUT STD_LOGIC);end COMPONENT;COMPONENT bcd_7seg isport(bcd_led :in std_logic_vector(3 downto 0);--input bcdledseg : out std_logic_vector(6 downto 0));--output to 7 segmentend COMPONENT;COMPONENT mx isport(s:in std_logic;a,b:in std_logic_vector(3 downto 0);q:out std_logic_vector(3 downto 0));end COMPONENT;COMPONENT comcoun isport(clk : in std_logic;--synchronouse clockenable : in std_logic;--scan clockcomclk : out std_logic_vector(2 downto 0));--output countend COMPONENT;COMPONENT com_encode isport(s :in std_logic;--input countledcom :out std_logic_vector(5 downto 0));--output encodeend COMPONENT ;signal clk1,c10: std_logic;signal q1,q2,bcd: std_logic_vector(3 downto 0);BEGINU1:clkgen PORT MAP(CLKIN=>CLK,CLKOUT=>CLK1);U2:COUNT10a PORT MAP(clk=>CLK1,clr=>clr,en=>en,q=>q1,count1=>c10);U3:COUNT10a PORT MAP(clk=>CLK1,clr=>clr,en=>c10,q=>q2,count1=>count1); U4:MX PORT MAP(S=>CLK1,A=>q1,b=>q2,q=>bcd);U5:bcd_7seg PORT MAP(bcd_led=>bcd,ledseg=>ledseg);U6:com_encode PORT MAP(s=>clk1,ledcom=>ledcom );end;2---clkgen.vhdLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_unsigned.all;ENTITY clkgen ISPORT(clkin:IN STD_LOGIC ;clkout: OUT STD_LOGIC);END;ARCHITECTURE even OF clkgen ISconstant N:Integer:=50000000;--constant N:Integer:=10;SIGNAL coun:integer range 0 to N;SIGNAL clk1:STD_LOGIC;BEGINPROCESS(clkin)BEGINIF(clkin'EVENT AND clkin='1')THENIF(coun=N)THENcoun<=0;clk1<=Not clk1;elsecoun<=coun+1;END IF;END IF;END PROCESS;clkout<=clk1;END even;3--10 位计数器程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNT10a ISPORT(clk,clr,en:IN STD_LOGIC;count1:OUT STD_LOGIC;q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END COUNT10a ;ARCHITECTURE rtl OF COUNT10a ISSIGNAL qs:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL ca:STD_LOGIC;BEGINPROCESS(clk)BEGINIF(clk'EVENT AND clk='1')THENIF(clr='1')THENqs<="0000";ELSIF(en='1')THENIF(qs="1001")THENqs<="0000";ca<='0';ELSIF(qs="1000")THEN --在计数到8时,即让进位赋值1,--由于信号会产生一个滞后,使得实际ca在9时出现qs<=qs+1;ca<='1';ELSEqs<=qs+1;ca<='0';END IF;END IF;END IF;END PROCESS;PROCESS(ca,en)BEGINq<=qs;count1<=ca AND en;END PROCESS;END rtl;4library ieee;use ieee.std_logic_1164.all;entity mx isport(s:in std_logic;a,b:in std_logic_vector(3 downto 0);q:out std_logic_vector(3 downto 0));end mx;architecture rtl of mx isbeginq<= a WHEN s = '0' ELSE b ;end rtl;5--七段显示扫描电路--comcoun.vhd 7 segment com scan counterlibrary ieee ;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity comcoun isport(clk : in std_logic;--synchronouse clockenable : in std_logic;--scan clockcomclk : out std_logic_vector(2 downto 0));--output countend comcoun;architecture behavior of comcoun issignal q : std_logic_vector(2 downto 0);--internal counted signal beginfscan:process(clk)beginif (clk'event and clk='1') thenif (enable='1') thenif q>=1 thenq<="000";--initial counterelseq<=q+1;--countingend if;end if;end if;end process fscan;comclk<=q; --output internal countend behavior;6library ieee ;use ieee.std_logic_1164.all;entity bcd_7seg isport(bcd_led :in std_logic_vector(3 downto 0);--input bcdledseg : out std_logic_vector(6 downto 0));--output to 7 segment end bcd_7seg;architecture behavior of bcd_7seg isbeginwith bcd_led selectledseg<="0111111" when "0000",--0,3f"0000110" when "0001",--1,06"1011011" when "0010",--2,5b"1001111" when "0011",--3,4f"1100110" when "0100",--4,66"1101101" when "0101",--5,6d"1111101" when "0110",--6,7d"0100111" when "0111",--7,27"1111111" when "1000",--8,7f"1101111" when "1001",--9,6f"1110111" when "1010",--A"1111100"when "1011", --b"0111001"when "1100",--c"1011110" when "1101",--d"1111001"when "1110",--E"1110001" when "1111",--F"0000000" when others;end behavior;7--计数译码电路-- 6 共阴--com_encode.vhd 7 segment com encoderlibrary ieee ;use ieee.std_logic_1164.all;entity com_encode isport(s :in std_logic;--input countledcom :out std_logic_vector(5 downto 0));--output encode end com_encode;architecture behavior of com_encode isbeginledcom<="000001" when s='0' else"000010" ;end behavior;九、实验总结。

VHDL课程设计 - 可变计数器实验报告总结
一、设计概述
本课程设计的主要目标是设计并实现一个可变计数器，其模（Modulo）值可以在4、8、12、16之间进行选择。

计数器采用VHDL编程语言进行描述，并在FPGA开发板上进行测试验证。

二、设计实现
1. 硬件平台：我们选择了Xilinx的FPGA开发板作为硬件平台，它具有丰富的I/O资源和足够的逻辑单元，可以满足我们的设计需求。

2. VHDL编程：我们采用VHDL语言进行编程，实现了模4、模8、模12和模16的可变计数器。

通过选择不同的计数模式，计数器的模值可以在4、8、12、16之间进行切换。

3. 测试与验证：为了验证计数器的功能，我们编写了测试平台，并通过仿真和实际硬件测试对计数器进行了全面的测试。

三、实验结果与分析
1. 实验结果：通过仿真和实际硬件测试，我们验证了计数器的
功能正确性。

在不同的模值下，计数器都能正确地进行计数操作，并且在达到模值后能正确地回绕到0。

2. 结果分析：实验结果表明，我们的VHDL编程和FPGA开发技能得到了很好的应用和提升。

同时，通过这次课程设计，我们更深入地理解了可变计数器的设计和实现原理，提高了我们的硬件设计能力。

四、总结与展望
本次课程设计让我们深入了解了VHDL编程语言和FPGA开发技术，提高了我们的硬件设计能力。

通过实际的设计和测试，我们成功地实现了一个可变模值的计数器，达到了课程设计的要求。

在未来的学习和工作中，我们将继续深入学习FPGA设计和VHDL编程，不断提高自己的硬件设计能力。

同时，我们也期待将这种技术应用于更多的实际项目中，为工程实践做出贡献。

VHDL-计数器程序十五计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fiveteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END fiveteencout;ARCHITECTURE counter OF fiveteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1110") THENcount_int<="0000";ELSEcount_int <= count_int 1;-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十四计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fourteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END fourteencout;ARCHITECTURE counter OF fourteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1101") THENcount_int<="0000";ELSEcount_int <= count_int 1;-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十三计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY thireteencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END thireteencout;ARCHITECTURE counter OF thireteencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1100") THENcount_int<="0000";ELSEcount_int <= count_int 1;-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十二计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY twelvecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END twelvecout;ARCHITECTURE counter OF twelvecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1011") THENcount_int<="0000";ELSEcount_int <= count_int 1;-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十一计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY elevencout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END elevencout;ARCHITECTURE counter OF elevencout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1010") THENcount_int<="0000";ELSEcount_int <= count_int 1;-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;十计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY count ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic_vector(3 downto 0));END count;ARCHITECTURE counter OF count IS SIGNAL count_int:std_logic_vector(0 to 3); BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1001") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;九计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY ninecout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(3 downto 0));END ninecout;ARCHITECTURE counter OF ninecout ISSIGNAL count_int:std_logic_vector(0 to 3);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="1000") THENcount_int<="0000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;八计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY eightcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(2 downto 0));END eightcout;ARCHITECTURE counter OF eightcout ISSIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="111") THENcount_int<="000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN--q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;六计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY sixcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(2 downto 0));END sixcout;ARCHITECTURE counter OF sixcout ISSIGNAL count_int:std_logic_vector(0 to 2);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="101") THENcount_int<="000";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN --q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--ELSIF--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;--end if;-- END PROCESS;END counter;四计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY fourcout ISPORT(clk,reset,enable : IN std_logic; count : OUT std_logic _vector(1 downto 0));END fourcout;ARCHITECTURE counter OF fourcout ISSIGNAL count_int:std_logic_vector(0 to 1);BEGINPROCESS(clk,reset)BEGINWAIT UNTIL rising_edge(clk);IF reset = '1' THENcount_int <= (OTHERS => '0');ELSIF enable = '1' THENIF(count_int="11") THENcount_int<="00";ELSEcount_int <= count_int 1;--ELSE-- NULL ;--IF (count_int="1001") THEN--count_int<="0000";END IF;END IF;END PROCESS;count <= count_int;-- IF (reset='0') then--q<="0000";---ELSIF(clk'event and clk='1') THEN --q<=q 1;--IF (q<="1001") then--q<="0000";---END IF;--IF (reset<='1')THEN--q<="00";--wait until (clk'event and clk='1');--WAIT UNTIL (clk'EVENT AND clk = '1');--WAIT UNTIL (clock'EVENT AND clock = '1'); -- q<=q '1';--end if;--count<=q;-- WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--clock'event and clock='1';--count <= 0;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT riseedge clock = '1';--if (clock'event and clock='1') then--WAIT UNTIL rising_edge(clock);--count <= 1;--WAIT UNTIL (clock'EVENT AND clock = '1'); --WAIT UNTIL clock = '1';--if (clock'event and clock='1')then--WAIT UNTIL rising_edge(clock);--count <= 2;--end if;--end if;-- END PROCESS; END counter;。

vhdl七段数码管显示0到9计数器显示电路设计在 VHDL 中，可以使用进程`PROCESS`和状态机来实现七段数码管显示 0 到 9 的计数器显示电路设计。

以下是一个示例代码：```vhdl-- 七段数码管显示 0 到 9 的计数器显示电路设计-- 定义七段数码管的显示编码CONSTANT seven_seg : STD_LOGIC_VECTOR(6 DOWNTO 0) := "1111110";CONSTANT seg_map : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000011";-- 定义计数器的位数和初始值CONSTANT count_width : NATURAL := 4;CONSTANT count_init : NATURAL := 0;-- 声明计数器和七段数码管显示的信号Signal count : STD_LOGIC_VECTOR(count_width - 1 DOWNTO 0);Signal seg : STD_LOGIC_VECTOR(6 DOWNTO 0);-- 计数器的进程Process (clk)BeginIf clk'event and clk = '1' ThenIf count = count_init - 1 Thencount <= count_init;Elsecount <= count + 1;End If;End If;End Process;-- 七段数码管显示的进程Process (count)BeginCase count IsWhen count_init - 1 => seg <= seven_seg;When count_init => seg <= seg_map;When count_init + 1 => seg <= seven_seg;When count_init + 2 => seg <= seg_map;When count_init + 3 => seg <= seven_seg;When count_init + 4 => seg <= seg_map;When count_init + 5 => seg <= seven_seg;When count_init + 6 => seg <= seg_map;When count_init + 7 => seg <= seven_seg;When count_init + 8 => seg <= seg_map;When count_init + 9 => seg <= seven_seg;When Others => seg <= seven_seg;End Case;End Process;-- 连接计数器和七段数码管显示的信号Output seg;```上述代码中，使用了两个进程`PROCESS`来实现计数器和七段数码管的显示。

vhdl加法器二位BCD码加法器的VHDL源程序如下导读：就爱阅读网友为您分享以下“二位BCD码加法器的VHDL源程序如下”资讯，希望对您有所帮助，感谢您对的支持!二位BCD码加法器的VHDL源程序如下：ibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bcdadd is ---------------------实体部分port(key:in std_logic;---------------定义key输入口a0,a1,b0,b1:in integer range 0 to 9; -----定义两个加数的输入口a0l,a1l,b0l,b1l,s0l,s1l,s2l:out std_logic_vector(6 downto 0);----定义七个输出数码管s:out std_logic);----定义Key指示灯输出口end;architecture one of bcdadd is ----------结构体部分signal one:integer range 0 to 18; ----定义两个数的个位相加之后的信号signal ten:integer range 0 to 19; -----定义两个数的十位相加之后的信号signal co1,co2:integer range 0 to 1; ----定义个位和十位的进位信号signal s0,s1:integer range 0 to 15;beginp1:process(one,ten,a0,b0,a1,b1,co1)----第一个进程，进行加运算beginone&lt;=a0+b0; --------------------个位相加之和if one&gt;9 then --------------------和大于9，进位为1 co1&lt;=1;s0&lt;=one-10; -----------------------个位的值else -----------------------和小于9，进位为0co1&lt;=0;s0&lt;=one; -------------------------个位的值end if;ten&lt;=a1+b1+co1;----------------------十位相加值和，加数包括个位来的进位if ten&gt;9 then -------------------和大于9，进位为1co2&lt;=1;s1&lt;=ten-10;-------------------十位的值else ----------------------------------和小于9，进位为0co2&lt;=0;s1&lt;=ten;-----------------------十位的值end if;end process p1;p2:process(a0,a1,b0,b1) ----------第二个进程，两个加数的输出数码管显示译码begincase a0 is ----------------------被加数的个位显示译码when 0=&gt;a0l&lt;=“1000000”;when 1=&gt;a0l&lt;=“1111001”;when 2=&gt;a0l&lt;=“0100100”;when 3=&gt;a0l&lt;=“0110000”;when 4=&gt;a0l&lt;=“0011001”;第1页共4页when 5=&gt;a0l&lt;=“0010010”; when 6=&gt;a0l&lt;=“0000010”; when 7=&gt;a0l&lt;=“1111000”; when 8=&gt;a0l&lt;=“0000000”; whenothers=&gt;a0l&lt;=“ZZZZZZZ”; end case; case a1 is ------------------------------被加数的十位显示译码when 0=&gt;a1l&lt;=“1000000”; when 1=&gt;a1l&lt;=“1111001”; when 2=&gt;a1l&lt;=“0100100”; when 3=&gt;a1l&lt;=“0110000”; when 4=&gt;a1l&lt;=“0011001”; when 5=&gt;a1l&lt;=“0010010”; when 6=&gt;a1l&lt;=“0000010”; when 7=&gt;a1l&lt;=“1111000”; when 8=&gt;a1l&lt;=“0000000”; when 9=&gt;a1l&lt;=“0010000”; when others=&gt;a1l&lt;=“ZZZZZZZ”; end case; case b0 is-----------------------------加数的个位显示译码when 0=&gt;b0l&lt;=“1000000”; when 1=&gt;b0l&lt;=“1111001”; when 2=&gt;b0l&lt;=“0100100”; when 3=&gt;b0l&lt;=“0110000”; when 4=&gt;b0l&lt;=“0011001”; when 5=&gt;b0l&lt;=“0010010”; when 6=&gt;b0l&lt;=“0000010”; when8=&gt;b0l&lt;=“0000000”; when 9=&gt;b0l&lt;=“0010000”; when others=&gt;b0l&lt;=“ZZZZZZZ”; end case; case b1 is ----------------------------加数的十位显示译码when 0=&gt;b1l&lt;=“1000000”; when 1=&gt;b1l&lt;=“1111001”; when 2=&gt;b1l&lt;=“0100100”; when 3=&gt;b1l&lt;=“0110000”; when 4=&gt;b1l&lt;=“0011001”; when 5=&gt;b1l&lt;=“0010010”; when 6=&gt;b1l&lt;=“0000010”; when 7=&gt;b1l&lt;=“1111000”; when 8=&gt;b1l&lt;=“0000000”; when 9=&gt;b1l&lt;=“0010000”; when others=&gt;b1l&lt;=“ZZZZZZZ”;第2页共4页end case;end process p2;p3:process(key,s0,s1,co2,a0,a1,b0,b1) --------第三个进程，和的显示译码以及输入大于9是的出beginif key=…0‟ or a0&gt;9 or b0&gt;9 o r a1&gt;9 or b1&gt;9 then --当key等于0或者两个输入中的任何一个位大于9，和的数码显示均为“Z”状态s0l&lt;=“ZZZZZZZ”;s1l&lt;=“ZZZZZZZ”;s2l&lt;=“ZZZZZZZ”;elsecase s0 is-------------------------------和的个位显示译码when 0=&gt;s0l&lt;=“1000000”;when 1=&gt;s0l&lt;=“1111001”;when 2=&gt;s0l&lt;=“0100100”;when 3=&gt;s0l&lt;=“0110000”;when 4=&gt;s0l&lt;=“0011001”;when 5=&gt;s0l&lt;=“0010010”;when 6=&gt;s0l&lt;=“0000010”;when 7=&gt;s0l&lt;=“1111000”;when 8=&gt;s0l&lt;=“0000000”;when 9=&gt;s0l&lt;=“0010000”;wh en others=&gt;s0l&lt;=“ZZZZZZZ”; end case;case s1 is--------------------------------和的十位显示译码when 0=&gt;s1l&lt;=“1000000”;when 1=&gt;s1l&lt;=“1111001”;when 2=&gt;s1l&lt;=“0100100”;when 3=&gt;s1l&lt;=“0110000”;when 4=&gt;s1l&lt;=“0011001”;when 5=&gt;s1l&lt;=“0010010”;when 6=&gt;s1l&lt;=“0000010”;when 7=&gt;s1l&lt;=“1111000”;when 8=&gt;s1l&lt;=“0000000”;when 9=&gt;s1l&lt;=“0010000”;when others=&gt;s1l&lt;=“ZZZZZZZ”; end case;case co2 is --------------------------和的百位显示译码when 0=&gt;s2l&lt;=“1000000”;when 1=&gt;s2l&lt;=“1111001”;end case;end if;end process p3;第3页共4页p4:process(key) -------------第四个进程，设置key的指示灯beginif key=…1‟ then s&lt;=…1‟ ; else s&lt;=…0‟;end if;end process p4;end;第4页共4页百度搜索“就爱阅读”,专业资料,生活学习,尽在就爱阅读网,您的在线图书馆。

基于VHDL的数值比较器、数据选择器、移位寄存器、60进制计数器、复杂ALU设计实验报告VHDL实验报告班级:电子学号:姓名:2014/5/23Experiment 1 两位二进制数的大小比较器一、实验目的:(1)熟悉QuartusII的开发环境、熟练掌握编程开发流程。

(2)学习VHDL的基本语法及编程设计。

二、实验内容:数值比较器设计三、实验要求:(1)熟练掌握QuartusII开发环境下对可编程逻辑器件进行程序化设计的整套流程;2)设计输入使用插入语言模板(Insert Template); ((3)在QuartusII开发环境下对设计程序进行时序仿真，将生成的配置文件下载到实验板，进行最终的实物测试验证。

四、实验原理:根据两位二进制数的大小得到对应的比较结果，其电路示意图及电路特性表为: 比较器特性表A B In_s In_l In_e 比较器电路示意图YsYe YlY A > B × × × 0 0 1A[3:0] Yl Number B[3:0] A < B × × × 1 0 0 Ye A = B 0 1 0 0 0 1 In_sYs Comparer In_l A = B 1 0 0 1 0 0 In_e A = B 0 0 1 0 1 0 A = B 0 0 0 × × × A = B × 1 1 × × × A = B 1 × 1 × × × A = B 1 1 × × × ×五、程序编写、调试及仿真(芯片型号:MAX?系列EPM1270T144C5) (1)程序编写:library ieee;use ieee.std_logic_1164.all;2entity Vhdl1 isport(a,b:in std_logic_vector(3 downto 0);ins,inl,ine: in std_logic;ys,ye,yl: out std_logic);end Vhdl1;architecture one of Vhdl1 issignal temps,tempe:std_logic; beginys<=temps;ye<=tempe;yl<=temps nor tempe;process(a,b,ine)beginif (a=b and ine='1')thentempe<='1';elsetempe<='0';end if;end process;process(a,b,ins)beginif(a<b) thentemps<='1';elsif(a=b and ins='1') then temps<='1';elsetemps<='0';end if;end process;end one;(2)功能仿真:3(3)芯片引脚设定:(4)适配下载结果六、结果分析本实验实现了两位二进制数的比较。

同步FIFO之VHDL描述(1)作者：skycanny时间：2007-09-28 16:09:38 来自：skycanny的笔记浏览次数：1601 文字大小：【大】【中】【小】同步FIFO之VHDL描述同步FIFO的意思是说FIFO的读写时钟是同一个时钟，不同于异步FIFO，异步FIFO的读写时钟是完全异步的。

同步FIFO的对外接口包括时钟，清零，读请求，写请求，数据输入总线，数据输出总线，空以及满信号。

下面分别对同步FIFO的对外接口信号作一描述：1．时钟，输入，用于同步FIFO的读和写，上升沿有效；2．清零，输入，异步清零信号，低电平有效，该信号有效时，FIFO被清空；3．写请求，输入，低电平有效，该信号有效时，表明外部电路请求向FIFO写入数据；4．读请求，输入，低电平有效，该信号有效时，表明外部电路请求从FIFO中读取数据；5．数据输入总线，输入，当写信号有效时，数据输入总线上的数据被写入到FIFO中；6．数据输出总线，输出，当读信号有效时，数据从FIFO中被读出并放到数据输出总线上；7．空，输出，高电平有效，当该信号有效时，表明FIFO中没有任何数据，全部为空；8．满，输出，高电平有效，当该信号有效时，表明FIFO已经满了，没有空间可用来存贮数据。

使用VHDL描述的FIFO将以上面的接口为基础，并且可以参数化配置FIFO的宽度和深度。

先把对外接口描述出来吧。

----------------------------------------------------------------------------------------------------------- Designer : skycanny-- Date : 2007-1-29-- Description : Synchronous FIFO created by VHDLlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity sfifo isgeneric(width : positivedepth : positive);port(clk : in std_logic;rst : in std_logic;wq : in std_logic;rq : in std_logic;data : in std_logic_vector(width - 1 downto 0);q : in std_logic_vector(width - 1 downto 0);empty : out std_logic;full : out std_logic);end entity sfifo;----------------------------------------------------------------------------------------------------------- 同步FIFO内部通过控制电路和RAM实现，控制电路主要包括写指针管理电路，读指针管理电路，以及FIFO状态判断电路，对于同步FIFO来讲，读和写的指针管理电路实际上就是二进制计数器。

VHDL 基础语法篇——VHDLVHDL硬件描述语言1。

1 VHDL概述1。

1。

1 VHDL的特点VHDL语言作为一种标准的硬件描述语言，具有结构严谨、描述能力强的特点，由于VHDL语言来源于C、Fortran等计算机高级语言，在VHDL语言中保留了部分高级语言的原语句，如if语句、子程序和函数等,便于阅读和应用。

具体特点如下：1。

支持从系统级到门级电路的描述，既支持自底向上（bottom-up）的设计也支持从顶向下（top—down）的设计，同时也支持结构、行为和数据流三种形式的混合描述。

2. VHDL的设计单元的基本组成部分是实体(entity）和结构体（architecture），实体包含设计系统单元的输入和输出端口信息，结构体描述设计单元的组成和行为，便于各模块之间数据传送.利用单元（componet)、块(block）、过程（procure）和函数（function）等语句，用结构化层次化的描述方法,使复杂电路的设计更加简便。

采用包的概念，便于标准设计文档资料的保存和广泛使用。

3. VHDL语言有常数、信号和变量三种数据对象，每一个数据对象都要指定数据类型,VHDL的数据类型丰富,有数值数据类型和逻辑数据类型，有位型和位向量型。

既支持预定义的数据类型，又支持自定义的数据类型，其定义的数据类型具有明确的物理意义，VHDL是强类型语言。

4. 数字系统有组合电路和时序电路，时序电路又分为同步和异步,电路的动作行为有并行和串行动作，VHDL语言常用语句分为并行语句和顺序语句，完全能够描述复杂的电路结构和行为状态。

1.1.2 VHDL语言的基本结构VHDL语言是数字电路的硬件描述语言，在语句结构上吸取了Fortran和C等计算机高级语言的语句，如IF语句、循环语句、函数和子程序等，只要具备高级语言的编程技能和数字逻辑电路的设计基础，就可以在较短的时间内学会VHDL语言。

但是VHDL毕竟是一种描述数字电路的工业标准语言,该种语言的标识符号、数据类型、数据对象以及描述各种电路的语句形式和程序结构等方面具有特殊的规定，如果一开始就介绍它的语法规定，会使初学者感到枯燥无味,不得要领.较好的办法是选取几个具有代表性的VHDL程序实例，先介绍整体的程序结构，再逐步介绍程序中的语法概念。

用VHDL描述二进制计数器
使用和结构和行为VHDL可以搭建出一个计数器电路。

在结构性技术器设计中，先列举所有需要的触发器并作为其器件，然后描述出下一状态逻辑来驱动每个触发器的D输入（数据输入）。

与行为性VHDL设计相比，这种设计方法非常冗长乏味，但是却能开发出很好的方案模型。

在任何标准的VHDL环境中，行为性计数器都可以很好的利用IEEE STD_LOGIC_UNSIGNED库。

使用SLU库，所有的STD_LOGIC数据类型都可以使用标准算术操作符，从而使计数器设计相当简单。

注意，计数器的计数输出是一个名称为B的矢量，且被定义为‘inout’类型，从而在赋值操作符两边都可以使用该矢量。

用V H D L实现二位二进制乘法应用译码器文件管理序列号：[K8UY-K9IO69-O6M243-OL889-F88688]------------------------------------------------------------------------------------ Company:-- Engineer:---- Create Date: 18:25:21 04/15/2013-- Design Name:-- Module Name: FOUR - Behavioral-- Project Name:-- Target Devices:-- Tool versions:-- Description:---- Dependencies:---- Revision:-- Revision 0.01 - File Created-- Additional Comments:------------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code.--library UNISIM;entity FOUR isPort ( a : in STD_LOGIC;b : in STD_LOGIC;c : in STD_LOGIC;d : in STD_LOGIC;DOUT : out std_logic_vector(3 downto 0));end FOUR;architecture Behavioral of FOUR issignal DIN :STD_LOGIC_VECTOR(3 DOWNTO 0);signal y : std_logic_vector(16 downto 0);beginDIN <= A & B & C & D;process (A,B,C,D)begincase DIN iswhen "0000" => y(0) <= '0';when "0001" => y(1) <= '0';when "0010" => y(2) <= '0';when "0011" => y(3) <= '0';when "0100" => y(4) <= '0';when "0101" => y(5) <= '0';when "0110" => y(6) <= '0';when "0111" => y(7) <= '0';when "1000" => y(8) <= '0';when "1001" => y(9) <= '0';when "1010" => y(10) <= '0';when "1011" => y(11) <= '0';when "1100" => y(12) <= '0';when "1101" => y(13) <= '0';when "1110" => y(14) <= '0';when "1111" => y(15) <= '0';when others => y(16) <= '0';end case ;end process;DIN(3)<=not(y(15));DIN(2)<=not(y(10) and y(11) and y(14));DIN(1)<=not(y(6) and y(7) and y(9)and y(11) and y(13) and y(14)); DIN(0)<=not(y(5)and y(7) and y(13) and y(15));end Behavioral;。

二位十进制计数显示译码电路一、实训目的1.巩固编译、仿真VHDL文件的方法。

2.掌握VHDL程序并行语句的综合应用。

二、实训器材计算机与Quartus Ⅱ工具软件。

三、实训指导（一）实训原理1.纯VHDL描述设计下面是一种2位十进制计数显示译码电路的VHDL描述，其中2位十进制计数是异步电路，编辑输入下面代码，并通过编译与仿真。

VHDL代码如下：cnt10.vhd文件VHDL文件代码如下：LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;ENTITY cnt10 ISPORT(Clrn,Clk: IN STD_LOGIC;q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);Co : OUT STD_LOGIC);END cnt10;ARCHITECTURE a OF cnt10 ISSIGNAL tmp:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(Clk,Clrn,tmp)BEGINIF Clrn='0' THEN tmp<="0000";ELSIF(Clk'event AND Clk='1')THENIF tmp<9 THEN tmp<=tmp+1;ELSE tmp<="0000";END IF;END IF;q<=tmp;END PROCESS;Co<=NOT(tmp(0) AND tmp(3));END a;decl7s.vhd文件VHDL文件代码如下：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY decl7s ISPORT(a: IN STD_LOGIC_VECTOR(3 DOWNTO 0);Led7s : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END decl7s;ARCHITECTURE one OF decl7s ISBEGINPROCESS(A)BEGINCASE a ISWHEN"0000"=>led7s<="0111111";WHEN"0001"=>led7s<="0000110";WHEN"0010"=>led7s<="1011011";WHEN"0011"=>led7s<="1001111";WHEN"0100"=>led7s<="1100110";WHEN"0101"=>led7s<="1101101";WHEN"0110"=>led7s<="1111101";WHEN"0111"=>led7s<="0000111";WHEN"1000"=>led7s<="1111111";WHEN"1001"=>led7s<="1101111";WHEN OTHERS=>led7s<="0000000";END CASE;END PROCESS;END one;BCD_Disply.vhd文件VHDL文件代码如下：LIBRARY ieee;USE ieee.std_logic_1164.ALL;ENTITY BCD_Disply ISPORT(Clrn,Clk: IN STD_LOGIC;led7s1,led7s0: OUT STD_LOGIC_VECTOR(6 DOWNTO 0));END BCD_Disply;ARCHITECTURE one OF BCD_Disply ISCOMPONENT cnt10PORT(Clrn,Clk: IN STD_LOGIC;q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);Co : OUT STD_LOGIC);END COMPONENT;COMPONENT decl7sPORT(a: IN STD_LOGIC_VECTOR(3 DOWNTO 0);Led7s : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));END COMPONENT;SIGNAL Coi1,coi0:STD_LOGIC;SIGNAL qi1,qi0:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINcnt0:cnt10 PORT MAP(Clrn,Clk,qi0,Coi0);cnt1:cnt10 PORT MAP(Clrn,Coi0,qi1,Coi1);decl7s0:decl7s PORT MAP(qi0,Led7s0);decl7s1:decl7s PORT MAP(qi1,Led7s1);END one;1.混合描述设计试用VHDL设计输入法设计底层文件cnt10.vhd和decl7s.vhd,再用原理图设计输入法设计顶层文件BCD_Disply_g。

VHDL代码书写规范（定稿）文件编号：编制：审核：可靠性审核：标准化：批准：文件会签页文件历史记录文件编号现行版本V1.0 文件标题VHDL代码书写规范文件履历版次编制日期更改内容（条款）V1.0V1.0目录1.目的 (1)2.范围 (1)3.术语说明 (1)4.书写规范 (1)4.1命名规范 (1)R1.一个文件只包含一个模块，文件命名和实体命名必须相同。

文件名大写，其后缀小写。

(1)R2.顶层文件命名方式使用工程名、器件型号与_TOP结合。

顶层文件的元件实例化，后缀使用_module；第二层文件的元件实例化，后缀使用_block；第三层之后不做定义（若遇到常见的基本逻辑电路或子模块，如：SRAM、FIFO等，那么优先使用具有代表性的名称） (1)R3.代码编写之前，以文档的方式，根据功能分类，分别对FPGA的外部端口进行命名约定。

(2)R4.命名要有实际意义。

(2)R5.命名标识符的首字符必须是字母，包含多个单词的标志符单词之间使用下划线分开。

信号、变量等的命名最后字符也一定要求是字母，中间的可以是数字或者其他合法符号。

(2)R6.模块、信号、变量等的命名不大于64个字符 (2)R7.实体、结构名、端口信号、常量用大写标识 (2)R8.行为级、结构级和数据流级结构命名分别以“BEH_实体名”、“STR_实体名”和“RTL_实体名”区分。

如果是混合使用，或者是分不清使用了那一种结构，那么就是用“ARC_实体名”命名。

(3)R9.单口RAM模块命名以SPRAM作后缀；双口RAM模块命名以DPRAM作后缀；ROM模块命名以ROM作后缀；FIFO模块命名以FIFO_作后缀；数字时钟管理模块命名以DCM作后缀；锁相环模块命名以PLL作后缀；乘法模块命名以MULT作后缀；除法模块命名以DIV作后缀；加法模块命名以ADD作后缀；减法模块命名以SUB作后缀。

(3)R10.模块实例化时，采用‘Un_xx_元件名’标识，cell实例化时使用‘Mn_xx_元件名’标识。