allegro2pads原始英文说明
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cadence菜单中英文对照第二部分Allegro菜单栏文件、编辑、察看、器件、连线、文本、模块、组、显示、PSpice、工具、窗口、帮助1.文件菜单原菜单中文菜单说明新建打开关闭保存另存为保存所有保存层转换恢复移动编辑页和符号下一层菜单见下表编辑层同上返回改变组件设置启动的工具察看搜索栈物理输出进行封装并输出物理输入从Allegro导入IFF输入导入IFF文件打印设置打印预览打印输出可输出原理图退出注:若菜单中的说明项为空,则表示不不需要说明或说明项与中文菜单相似。
以下相同。
下一页前一页转向加入新页下一层上一层2.编辑菜单撤销重做移动复制复制所有重复复制排列删除颜色分割镜像翻转旋转模块顺序画弧画圆3.察看菜单放大矩形范围放大到满屏放大缩小按比例放大上移下移左移右移预览网格设定状态条错误信息条控制窗口数据栏工具栏4.器件菜单添加器件替换器件改变版本可改变器件符号的显示类型修改部分可设置器件在封装中的位置交换针脚删除5.连线菜单连线需要从一点画到另一点连线点击两点自动连线添加信号名添加总线名连结总线设定总线参数画点连线加粗设置连线的图案6.文本菜单特性设置习惯设置器件赋值可对电阻电容等进行赋值理性文本设置端点的名称添加注释打开文本文档设置字体大小放大缩小交换重新连结特性显示下一层菜单如下显示名称显示值两样都显示不可见7.模块菜单添加重命名扩展连线连线添加针脚重命名针删除针脚输入针脚输出针脚双向针脚8.组菜单创建组下一层菜单在下表设定当前组显示组的内容移动复制复制全部设置复制个数设置文字大小改变注释删除设定颜色激活器件特性显示矩形框内创建为一组多边形框内创建为一组用表达式创建下一个在组中去除一个器件在组中添加一个器件替换改变显示版本删除修改显示名称两样都显示不可见9.显示菜单激活去激活联系显示信号名和文本与器件的连结关系颜色器件信息连结显示点的坐点击一点标显示目录显示距离点击两点,在下方状态栏显示显示历史信息设置快捷键显示修改信息显示线网信点击线网息显示端点针脚显示所有的针脚针脚名显示点击的器件的针脚名显示特性显示所有器件的针脚信息返回显示字体尺在下方状态栏显示寸10.Pspice菜单创建仿真文件编辑仿真文件删除仿真文件检查生成网表查看网表运行查看结果编辑模型编辑激励仿真多重文件模拟数据11.工具菜单扩展设计取消扩展当前编辑全局查找查找某一个器件全局导航可查出某个器件属于哪个库限制管理器检查进行错误检查显示错误显示错误及告警信息运行script文件反标将封装后的信息标注在原理图仿真层次编辑生成符号图可用于层次设计封装应用程序下一层菜单如下表设计差别比较可将原理图的修改更新到板子设计联系习惯设置可编辑设计环境、快捷键等选项可设置栅格尺寸等材料清单电气规则检查生成网表报告12.窗口菜单新开一个窗口刷新层叠将多个窗口层叠摆放平铺将多个窗口平铺展开排列图标当前激活的窗口13.帮助菜单帮助主题新增功能主要帮助常见问题及解决方法产品说明Cadence文件可链接到Cadence公司网站关于Concept-HDL显示版本信息第二部分Allegro菜单栏文件、编辑、察看、添加、显示、设置、逻辑、布局、布线、分析、制造、工具、帮助1.文件菜单新建打开保存另存为导入导出查看日志打开日志打印设置打印改变编辑器生成说明文件退出2.编辑菜单移动复制镜像旋转修改删除生成图形删除未连结的图形分割平面倒角修改器件边角删除倒角文本分组特性设定3.查看菜单放大矩形范围放大至满屏放大缩小放大整个范围以一点为中心放大保存镜像文件镜像文件恢复刷新习惯设置4.添加菜单线弧形3点弧形圆四边形填充的四边形文本图形实心填充不填充交叉线网填充5.显示菜单颜色设置显示颜色面板元件信息测量寄生参数特性设置激活去激活显示飞线不显示飞线6.设置菜单画图尺寸画图选择文字大小网格设置子目录层结构过孔设置限制设置电气规则设定特性定义线网定义区域内可放置封装区域内不可放置封装区封装高度区域内可布线区域内不可布线区域内不可设置过孔区域内不可设置探针区域内不可优化布线影像输出外框7.逻辑菜单线网逻辑线网方案设置差分对标识直流线网设置RefDes自动命名RefDes改变器件终端设定重命名重命名整个设计重命名一个区域内元件重命名窗口内元件重命名列表中的元件8.布局菜单手工布局快速放置在CCT中布局自动布局交互式布局。
一.PCB中各种词汇的解释:1.Primary Component Side 主元件面层2.Ground Plane 地平面层3.Power Plane 电源平面层4.Secondary Componnet Side 次元件面层21.Solder Mask Top 顶层阻焊(只有焊盘,没有过孔)22.Paste Mask Bottom 底层钢网图23.Paste Mask Top 顶层钢网图(表层要焊的焊盘,不包括圆形焊盘)24.Drill Drawing 钻孔图(PLTD成铜,呈白色)26.Silkscreen Top 顶层丝印图(所有元件名)27.Assembly Drawing Top 顶层装配图(外壳)28.Solder Mask Bottom 底层阻焊29.Silkscreen Bottom 底层丝印图30.Assembly Drawing Bottom 底层装配图Pads 焊盘Traces 走线Vias 过孔Lines 二维线Text 文字Copper 铜皮Ref.De 元件名Keepout 禁止区域Top 顶层Bottom 底层Background 背景色Selections 选中对象的颜色Highligh 高亮(命令为Ctrl+H,取消命令为Ctrl+U)Board 板框色Connection 鼠线(没有连通的线)Pin 元件脚Decals 封装(脚位图)Select Components(元件)Clusters(簇)Nets(网络)Pin Pairs(管脚对)Shapes(形状)Documentation(文字)Board Outline(板框)Tools:Decal Editor 元件编辑器Pour Manager 灌铜管理器Verify Design 设计规则检查(详见P209)L3 显示当前的第3层(快速换层的显示方法)二.单面板制作流程:设计准备:1.调出原理图(用PowerLogic)先点Connect to PowerPCB2.先点Tools→OLE PowerPCB Connection,然后把Preferences中的Parts/Nets/Compare PCB Decal Assignment这3个点亮3.然后点Design中Compare PCB 同原理图PCB相比较Rules To PCB 把原理图的参数同步到PCB里面去Send Netlist 生成网表,对不同软件间的转换Synchronize PCB 同步到PCB里面去(选取)Rules From PCB 把PCB的参数同步到原理图里面去Synchronize SCH 把PCB的所有东西反同步到原理图里面来4.把同步到PCB里去的所有元件打散以及颜色的设定:①全部选中→右键中的Disperse(打散)。
Cadence Allegro简易手册Allegro PCB Layout SystemLab Manual.CHAPTER 1 熟悉环境在开始前请将范例复制到您的工作路径下如:<在安装路径下>\share\pcb\selfstudy\user1 Æ c:\allegroclass\user1启动程序开始Æ程序集ÆCadenceÆPCB systemÆAllegro(电路板工具)开始Æ程序集ÆCadenceÆPCB systemÆPad Designer(焊点编辑)开启旧档选 FILE/OPEN 请开启 C:\AllegroClass\User1\Cds_Routed.brd档如果选了Change Dir 则会将现有路径C:\AllegroClass\User1变成你的内定工作路径认识你的工作窗口有指令区menu bar图标区icon ribbon控制盘control panel工作区design window状态区status window命令区console window.若想自定窗口位置customize 则选View-Customization / Display可设左侧control panel 所放的新位置为浮动式undocked贴左侧Docked_left贴右侧Docked_right(系统值)View / customization / toolbar 则设定控制图标区显示效果项目…显示缩放Zoom by Point Æ显示框选区以左键框二点Zoom fit Æ显示资料全区Zoom in Æ放大比例Zoom out Æ缩小比例Zoom world Æ显示整个工作区Zoom center Æ光标点为下个屏幕中心按Ctrl键配合按着的鼠标右键画w即可Zoom fit.若画Z即可Zoom in画面平移PAN1.利用方向键可平移2.三键鼠标则按中间键即可动态平移.若为二键鼠标则为右键+shift显示项目控制在右侧的控制盘中有visibility 项目来控制显出的对象打勾者代表要显示详细的设定则用指令Setup-color/Visibility而这些对象分成群组 Group级Class次级 Subclass在此可控制图层及各项目的显示与否,我们顺便试一下如何录script1选File-Script指令,键入文件名为colors(勿按Enter键),再点选Record记录2 选Color/Visibility指令,如果要全关选右上角的Global Visibility将值改为All Invisible确定后选套用Apply.这样会关所有显示项目3 选群组中的Components,找到Class里的Ref Des请把它底下的Assembly_top 方框勾选起来表示开启其显示4 选群组中的Geometry把它Board Geometry里的OUTLINE打开, 也把Package Geometry里的Assembly_top 打开5 选群组中的Stack-up,把TOP和BOTTOM的Pin.Via.DRC.Etch打开.而GND及VCC只开DRC.ANTI ETCH如果要设新颜色请在下方色盘Palette中选要用的新颜色,再将它点到要修改项目的色块上就可改过来了6 停止script录制选 File-Script-Stop.先前的层面及颜色设定都会被存在colors.scr中.此colors.scr是一个文字文件,可用一般的文字编辑程序或File-File Viewer加以编辑如果要测试script,请先用All Invisible全关所有显示,再到下方命令列中输入replay colors就会看到程序把先前的设定重跑一次,而显示也回来了标示亮度Highlight将特定对象标示亮度以图形效果显示其特异性如以要找一颗U3的零件为例:1先Zoom in2选标示亮度Display Æ Highlight或其图示3在右侧选高亮度的颜色4选Control panel 中的Find 页面5在Find by name 后net改成symbol (因为是找零件)6点Move键找到U3 (敲入U3 U* 按Tab键)按Apply OK7光标移至右下角全图显示区按右键选Find Next 即可将此对象显示于画面中央控制可被选取对象在编辑对象如:移动复制删除之前须选到所要的对象所以选取对象等的控制会影响后续的动作流程以移动U4的零件及移动U4零件名称RefDes为例1Zoom in到U4附近(在左上角)2选Edit Æ Move指令3选右侧的Find页面4在Find的页面中选全选ALL ON5点 U4的字符串部份你会看到U4会被抓到游标上而你正在移动U4这颗零件(因为symbol有被选取)6选右键中的OOP取消移动U4的动作7在Find页面中选全关ALL OFF 只选Text项目8再选U4字符串部份只有U4字符串被抓起像在调文字面的位置所以跟选择项目很有关系9取消检查数据项利用Display Æ Element 或其图标检查对象内容1先Zoom in2选Display Æ Element或图示3在Find中选ALL ON4随点选对象的不同会显示其相关的资料CHAPTER 2零件的整备本阶段要试建一颗14PIN DIP 零件零件的组成有焊点 PADSACK零件Package symbol每一个接脚PIN及孔Via皆视为一焊点PADSTACK如以60-38为例进入程序开始Æ程序集Æ cadence Æ PCB Systems Æ PAD Designer改种类为贯孔Through单位为mil精确值为1 (小数后1位)焊点在每一铜箔层皆要有一般点regular PAD梅花瓣Thermal-relief PAD挖开点Anti-PAD的三种效果1选Layer 页面2点选Begin Layer3在一般点项目设形状为Circle width为60height为604在梅花瓣设形状为circle值为80Flash项目为TR805在挖开点设形状为circle值为80由于其它层设定相仿可点左侧Bgn按右键copy复制6点internal 的左侧按右键选右键paste即可贴入不须重key in7以同样方法贴到END层8在SOLDERMASK_TOP层的Regular PAD设circle大小为709一样复制到SOLDERMASK_BOTTOM钻孔定义如果定为Through-Hole焊点须定孔径及钻孔符号在Drill Hole 项目中定Plate Type 为Plated (孔壁镀铜)孔径38. Drill symbol的Figure为钻孔符号效果Character为标示字符串Width height为符号的宽及高储存焊点选File Æ Save as 存到 C:\allegroclass \ user1 档名为 60C38d.PAD实体零件的建立建立实体零件的格式不同所以须进入零件建立模式下1File / New 在DRAWING NAME中敲入新零件名如DIP14并在DRAWING TYPE中选PACKAGE SYMBOL2设作图环境选SETUP – DRAWING SIZE在Move Origin项目中的XY各敲入5000使原点调整至适当位置3加入焊点选ADD PIN或其图示并右侧OPTION项目中敲入焊点60S38D后按Tab键状态列会显示出Using ‘ 60S38D.PAD’4光标移至状态列点选后敲入x 0 0会把第一接点放到原点 00的位置上(x须为小写)窗口缩放到PIN1附近5在右侧OPTION中改焊点为60C38D后按Tab键在Y的Qty项目中输入6 6在状态列输x 0 100则会放入向下距100mil的27接点7把Y项目的Qty改7个次序order改up8状态列输入x 300 –600会放入第8PIN到14PIN之焊点但是其脚号仍位于焊点左侧可按右键之OOP取消9将OPTION中的OFFSET值由-100改为100 (表右边100mil处)于状态列输入x 300 -60010完成按右键中的DONE文字面绘制 SILKSCREEN要调整格点大小时请以SETUP /GRIDS将NON-ETCH的X Y值键入25表文字面绘制格点为251选ADD/LINE2将右侧OPTION选为Package Geometry下的SILKSCREEN_TOP设画线角度等3画上文字面的矩形框组装外型绘制Assembly outline (可省略)同文字面之动作但层面为Package Geometry下的Assembly-Top设文字面之零件名称及零件号1选Layout_Label Æ Ref Des或其图示2图面为 refDes下的Assembly_Top3点选放零件名称的好位置(须在Assembly outline中)4键入名称如U* (请先注意右侧的字体基准点角度)5选Layout_Label中Æ Device6选适当的位置后键入 dev type后按右键的DONE绘制零件限制区Package boundary (可省略自动抓)定义零件高度(需要有Package boundary才可定义)1Setup-Area-Package Boundry Height层面为Package Geometry下的Place_Bound_Top2点先前建的Package Boundry 区域3输入高度值如180若没设则以Drawing option下的symbol Height为其内定高度值存零件文件(两者都要存)1选File Æ Create Symbol存成可放到PCB上的.PSM檔2选File Æ SAVE存成供以后修改的图形.DRA檔以自动程序建零件利用Symbol Wizard填入参数自动建零件1、File /New后在Drawing Name键入名称如dip16在Drawing type选PackageSymbol [Wizard] 后选OK2选Package Type为dip后点Next (选零件包装)3套用CADENDCE规划选Default Cadence Supplied template套用其它零件则选Custom template后选.Dra档套入后选Next4设定使用的公英制准确位数及名称前字符串prefix5依不同零件外形设定其参数如脚数Number of Pins脚距LeadPitch行距Terminal row spacing文字面的宽及长Width&Length)6选套用的焊点(一般焊点及第一脚)7定零件原点为中心center of body或第一脚pin1 of symbol及是否另存.PSM檔8选Finish 即OKCHAPTER 3板框绘制板框在Allegro中属于特殊的Mechanical Symbol板框为电路板的外形尺寸,其来源可由手工绘入.,键坐标输入画成.如果有Option 接口的话可由AUTOCAD转入DXF或Pro-Engineer的IDF.键坐标画图框1选File一New,在檔名Drawing Name中敲入如cds_outline.请注意格式务必改成Mechanical Symbol后按OK2设绘图区选Setup一Drawing Size.将图区Size设成A.并把DRAW Extent改设成Left X与Lower Y在设原点偏移量.Width 与Height设工作区大小设工作格点选Setup一Grids.将Non-Etch的格点设为25后按OK画板框选Add一Line.注意层面须改成BOARD GEOMETRY/OUTLINE.请输入x 0 200iy 2300ix 4000iy –2300ix –100iy –200ix –3700iy 200x 0 200 完毕按右键下的Done定工具孔Tooling Hole选指令Add Pin在右侧的Padstack中输入hole109再按Tab键.请在命令列输入x 100 300x 100 2400x 3900 2400 完毕按Done 结束标尺寸Dimension利用Dimension linear指令,层面会自跳到BOARD GEOMETRY下的DIMENSION.点选被测线段就可拖出其尺寸标注线放上.倒角Chamfer如果画的板框有直角要倒角,可用指令Edit一Chamfer.在右侧Options中TrimSegment的First栏设50.表示未倒角的两边线段长为50mil.试着点要倒角的第一段线,再点它的垂直线,就可做出倒角效果来设走线及摆零件区1先Zoom in到图框的左下角,2选Setup一Area一Route Keepin(走线区)在板框内的50mil(二个格点)内画出其布线限制区.(会在ROUTE KEEPIN下的ALL.)3选Setup一Area一Package Keepin(摆零件)画出相同的限制区设禁止摆零件及走线区选Setup一Area一Route Keepout(走线)画上不能走线的范围,其显示为一填满区.试画过后请Edit一Delete删除(在Find中要勾Shape),否则稍后可布线区域可能不够.其它如ViaKeepout则为禁打贯孔区存板框檔1选File一Create Symbol设入档名如cds_outline后选Save会存成cds_outline.bsm的Board Symbol 檔.2再选File一Save存成cds_outline.dra的图形文件.建立环境档Master Design File (.brd)环境档通常是只先放入板框而未含有逻辑数据的作图文件.利用它把大家讨论过认证的Geometry先设好的存在图档上.达到统一作图环境的目的.当成公司内的标准档.1选File一New,在檔名Drawing Name中敲入如cds_master.请注意格式为Layout 后按OK2设绘图区选Setup一Drawing Size.将图区Size设成B.,小数后位数Accuracy设成2.并把DRAW Extent的Left X设成-5000 ,Lower Y设成-5000完成按OK3放入板框零件,选Place一By Symbol一Mechanical,先点Library键才会列出各Mechanical Symbol,选先前建的cds_outline后按OK键准备放到图上4在命令列敲入x 0 0 ,放到图上(0,0)点.完毕按Done加图框Format Symbols如果要加上图框或其它注意事项宣告1Place一By Symbol 一Format, 先点Library键使列出各Format Symbol.如果点选Asizeh.表示要挂上A Size 横向的图框2利用光标把图框放至工作区上(请并确定板框数据含于图框范围内)3按右键选Next选到Note这个Symbol4请放在图框内板框外的适当区域中预放零件如果有特定的零件位置或固定的某几颗零件如connector.switch.等等.可以先摆到板上1选Place一By Symbol一Package.点Library使列出各实体零件.请选其中的conn140后按OK2在命令列输入x 3775 -200后按Done摆到图上设颜色1进到Color/Visibility中设定显示项目或其颜色.如果先前已存有Script 文件请Replay控制图形效果,请在命令列输入 replay colors层数设定Cross SectionAllegro内定的板层为二层板(指二个电气层).您如果是多层板则必须先宣告其层面结构.如层数.材质.用途.Subclass name.正负底片效果等.而其材质的种类及特性定义在<cds ins dir>/share/pcb/text/materials.dat檔中1选Setup一Cross Section点FR-4层名左侧的Edit后选Insert新增,则在原层之上会加入一个新的FR-4层.请总共新加入8层,因为我们待会要宣告此板为六层板,加上五层FR-4介质层及二层原有的空气层全部为13层.2点选第二个FR-4层准备把改设为内层的GND.请点其材质Material项目改设为铜箔Copper,将层面特性Layer Type改选成Plane,而Etch Subclass name取名成GND.最后把其底片效果由念Positive改为Negative表示此层为负片.3最后设定完成如下.表示此板为47.2mil厚的六层板.如果要删层则点选那一层其左侧的Edit键后按右键选删除Delete即可存环境档宣告完毕要存成环境档,请用File-Save As另存新档设入档名为cds_master1.brd 存入.通常Allegro的环境档可统一放在<course inst dir>/allegro/project1/worklib/esdesign/physical路径下CHAPTER 4加载联机关系与设定规范载入联机关系Load the Netlist联机关后档是一个由线路图程序所产生的文字文件netlist目的在交代零件(外型名称)及联机关系(接点及讯号名).要是零件需要作功能互换(gate swap或pin swap)则需另定零件宣告文件device file.如果有同类型但不同名零件可用对应文件map file宣告其对应不需每颗皆定义.以ORCAD为例,再执行完ERC电器检查后.即可执行其Tools-Netlist将线路图档转出联机关系档,其格式请选用others页面里的Allegro.就可把整份图转成一个联机档 .net或.txt零件若是在布线时会做swap的联机交换则须为零件定义其Device file 以宣告其零件之脚数闸数等到时:7400会对应7400.TXT套入宣告如果二者名称不同可以devices.map档宣告其对应性.以下devices.map为例零件7400会对应到74abcd.txt的device檔而非7400.txt如果要零件宣告文件device file,新版的ORCAD 9.x可用指令Accessories-Allergo Netlist自动产生各零件的device file.不需手动以文字编辑程序逐一编写载入联机 Import Logic1. 选File/Import Logic定来源格式Logic Type为Third party.2. 来源档案 Import From 点选后再选Browse键选文字联机文件的3rdparty.txt.3. 是否替换新零件Replace changed component.设Always4. 是否允许拆原有布线Allow etch removed during eco依情况而定5. 设定转联机关系时取代原图上的逻辑数据supersede All logical.6. 要加载联机成为电路板文件选加载Import.设计规范Allegro的设计规范是在定义设计过程中的条件限制,这些条件的设定是用来作为设计时安全检查的标准.例如我们可以定义层数,各层的规范,特殊讯号的限制条件如线宽间距打贯孔数,或特定区域条件等等,以配合电器或机构考量.而且宣告过的规范存在图档上,可避免以后布线时因考量因素众多而疏漏所造成需重修的情况.设定内定设计规则内定设计规则是给图文件中未经特定宣告的任意讯号(一般线)所套用进入Setup-Constraints请点选内定标准值Default Value设定其线到线,线到点,点到点,线宽,套用的贯孔等设定其它的设计规则在一份图档上有些特殊的线有其不同的规则相对于先前定的内定标准值如CLOCK讯号它的间距如为10 mil不同于先前内定的 5 mil.其步骤为定RULE SET请点选SPACING RULE SET下的SET V ALUE.在DELETE后的空白处输入 10 MIL SPACE后点选加入键加入新的RULE SET.随后输入其各间距的值再按OK键确定宣告相关讯号选ATTACH PROPERTY -NET,选右侧的FIND点选下方的FIND BY NAME切换成NET后再输入CLK2.程序跳出其PROPERTY画面请选NET-SPACING-TYPE, 在其V ALUE中输入其组别名称如CLOCK后按APPLY确定讯号套上RULE SET选在SPACING RULE SET中的ASSIGMENT TABLE设定各个RULE SET之间的规范如CLOCK与NO_TYPE指先前订的CLOCK(本例中只有CLK2)与一般讯号NO_TYPE所套用的间距值为10 MIL SPACE设定实体规范在实体规范PHYSICAL RULE SET中选其SET V ALUE键,在DELETE后的空白处输入10 MIL LINE 后点选加入ADD键,建立新的PHYSICAL SET.随后输入其允许最小线宽MIN LINE WIDTH,缩线后最小线宽,最大线宽,是否形走线,套用的贯孔焊点为何等等.,结束按宣告相关讯号选ATTACH PROPERTY-NET,选右侧的FIND点选下方的FIND BY NAME切换成NET后再输入REF.程序跳出其PROPERTY画面请选NET-PHYSICAL_TYPE在其V ALUE中输入其组别名称如ANALOG后按APPLY确定讯号套上RULE SET选在PHYSICAL RULE SET中的ASSIGMENT TABLE套上各个RULE SET的规范如把ANALOG套上先前订的10 MIL LINE,NO_TYPE指一般讯号请套上DEFAULT.第二项为AREA是当有设定特定区域AREA时才有对应的新值可输入STUB LENGTH,允许最多贯孔数MAX VIA等等而AREA则是以特定区域的方式来宣告其特别的设定值如线宽间距等设计规范存盘我们可将前面所设好的规范存成一个技术文件TECH FILE,请选指令FILE-EXPORT-TECHFILE设好文件名再按执行RUN键即可产生下次开新文件时层面只有二层,也没有特殊线宽或间距等设定,这时你可以加载技术档..这样这些设定即不须重设只须要把新讯号重新指定其对应的规则就可了查属性要检查己订属性可用1选EDIT-PROPERTIES配合右侧FIND2 选DISPLAY-PROPERTIES指令后选要查询的值如NET_SPACING_TYPE,再于V ALUE栏输入查询值如 * 表示任意即可查到先前订的CLOCK.在您绘图的过程中Allegro会以先前订的规范持续的检查你的图档当它有违规时则会有DRC的标记在上面.而这个蝴蝶形的标记的两边各有一个英文字母代表它检查的数据种类如L表线段LINE,.V表VIA,P表PAD等等,使我们能很快的知道错误在那儿而侦测到的错误项目又是什么数据间的状况可以马上加以改正.您也可以用SHOW ELEMENT的指令来查看更详细的结果Chaper 5摆放零件在建完零件,传入联机关系,订好规则之后紧接着的就是零件的摆放动作在图示中通常已经挂上了一些有关摆放零件的图标而这些图标就如同指令PLACE下的各个摆放功能请开启位于c:\\allegroclass\user1\ 底下的constrainted.brd手动编名因为置于板上的金手指尚未命名所以我们必须手动的帮它编名请选Logic-Assign RefDes并点选右侧Options下方的RefDes字段中输入J1 点选金手指则会把这颗零件命名为J1设定摆放格点设摆放零件时移动零件的距离请选Setup-Grid下的Non-Etch将其Spacing X:值输入50,Y:值输入50.要不要显示格点则设定左上角的GRID ON以零件名称摆放Placed By RefDes一般摆零件时习惯边看线路图边摆零件,所以我们须将相关的零件逐一叫出这样就会用到此功能请选Place By RefDes指令敲入零件名U5后按OK就可抓出U5到图上准备摆入.如果想要旋转,请按鼠标右键选择Rotate这时零件上就会跑出一根控制杆到光标位置利用鼠标转动即可控制其旋转角度.按左键可停止旋转.移动到要摆的中下图区后按右键选Done放置如果摆上的零件看起来是一个填满的大方块是因为开启了它的限制区.想关闭请至Display-Color/Visibility把Package Geometry/Place_Bound_Top项目勾勾去掉除了此种方法外如果新摆入的零件都须转一个特定角度的话可到Setup-Draw Options选其中的SYMBOL把Angle字段输入或改选成90再点OK键试着抓U7进来摆,你可看到它己是旋转了90度等着您摆入移动零件如果已摆入零件其位置须要挪移请选Edit一Move后再到右侧的Find项中全关只留Symbols.请点选要移动的零件(最好点它的名称字符串)零件就会被抓到光标上,待移到新位置后,点右键按Done即完成移动一群零件同样以Edit一Move指令以鼠标左键框出一个区域,框住要一齐挪移的零件(如果要放弃框选范围可选右键下的Oops).再以左键定其基准点就可一齐移动到时再以右键下的Done确定.再框选时请勿框到 Board Outline,Keepins,keepouts的Board Symbol资料.其它摆放的动作有Place一Component一ICs 摆IC类零件Place一Component一IOs 摆输出入类零件Place一Component一Discrete 摆附属小零件Place一Component一ALL 摆所有零件联机互换的动作有Place一Swap一Component 零件位置互换Place一Swap一Functions 闸联机互换(需有device宣告)Place一Swap一pins 接点联机互换(需有device宣告)联机显示控制联机指点到点间用来表示其电气接续性的表示线.我们会依不同需求开关某些零件或讯号的显示效果来达到评估布线策略的目的显示(关闭)所有联机Display一Show(Blank) Rats一All显示(关闭)单颗零件Display一Show(Blank) Rats一Component显示(关闭)单条联机Display一Show(Blank) Rats一Net产生摆放零件报表您可以产生一份摆放零件报表它可列出图中已摆放及未摆放之零件数据您在摆完零件后可用它来再确认是否有漏网之鱼尚未摆入HAPTER 6 布线布线相关指令设定布线格点随着不同的布线须求.您可为不同层设定不同的布线格点或是设定所谓的不等距格点如8 9 8这样的工作格点.指令为Setup一Grids设定格点,其中左上角的Grids On 为设定是否显示格点.Non-Etch为非电气层格点如摆零件.All Etch为所有电气层之走线格点.Top….为各电气层之走线格点值在布线时我们必须在右侧的Options中设定布线的工作层Act及代换层Alt在走线时首先走在工作层上如果要换层只须连续点二下左键(双击)则您的工作层及代换层会自动互换并打上贯孔试走第一条线1请先关闭所有联机显示,然后选Display一Show Rats一Net按鼠标右键选其中的Net Name输入 clk2使只开此讯号的显示效果2 Zoom in到U15 选择布线图示或Route一Connect将右侧的Options中的Act 层设为Top,Alt层设为IS3,线的角度设45度线宽设5,布线效果RouteType设手动布线Manual.3 试着点线开始布线,一开始走出时是在正面ToP层,如果觉得走得不好请用右键按OoP取消删除布线如果不满意先前所走的布线结果可以用Delete指令予以删除但是请配合右侧Options或Find的选项让使用上更加的便利1.全线删除请选择删除示或指令Edit一Delete在Find下请先选ALL OFF再开Clines请点CLK2的布线,此线会全部高亮请再按右键下的Done就会把它删掉(请救回此线以执行以试作底下其它动作)2.线段删除如果要删掉的只是某些线段非整条布线,请在右侧的下Find关所有项目只留ClineSegs同样点CLK2你会只看到此线段高亮,如果点其它线段则先前的线段即消失被删除了3.二点间线段删除如果要删掉的只是某些线段内的一小段,选Edit一Delete按右键下的Cut,点要删掉线段内的第一点(线段变亮)再点第二点,则剩此区间高亮可删除.布线效果Routing Type在走线的过程中我们有三种效果可以选择,分别是手动布线Manual,循迹布线To Cursor,结点布线To Pick1.手动布线Manual--------在前一光标位置与目前的光标位置间显示出走线’不会自动闪其中的障碍但推线效果明显2.循迹布线To Cursor-----随游标带出布线的走向,可动态的看出将布线的效果,会自动的闪避其中的障碍3.结点布线To Pick--------前后光标点间无法看到动态的布线轨迹,但是会自动闪线且速度比较快走线的过程中按鼠标右键会出现一些选项Done =>布线停止,回到空-状态IdleOops =>取消前线段动作Cancel =>取消前指令Next =>布线暂停,改走其它线Temp Group =>宣告走bus线讯号Complete =>结束bus线讯号选入动作Reject =>放弃现有选取,可改选其它Add Via =>打贯孔Finish =>以同层自动走完未布线段Snap Rat T =>移动讯号T点位置Neck =>窄线布线,须依Physical Rule Set宣告New Target =>改定同讯号的目的点(布线终点)No Target =>尾段讯号不显示Swap Layer =>走线换层(Act层换到Alt层) Toggle =>出线角度切换(先直再斜或先斜再直)打贯孔贯孔是用来导通层到层之间的讯号关系,贯孔必须有焊点的特性在布线的过程若加入贯孔则其工作层与代换层就会自动切换走到对应的布线层面.动作为连续点二下左键(双击)或选右键里的Add Via.移线利用移线指令SLIDE可移动先前所布的线段.你只需要选好指令后用左键点选要移动的线段即可动态的移动此线段,而与此线段相连的线段效果也会自动调整保持整体的完整性1请开启档案CDS_ROUTED.BRD稍为Zoom in到局部区域上.请选图标区上的移线图示或ROUTE一SLIDE2在右侧的Find项目中全清只留Via及Segment3以左键点选线段移动看看,也以左键定其新的落点4可以试着改变调整右边设定如角度CORNER或最大斜线长度Max 45 Len看看它的效果修端点VERTEX要挪动,新增,重迭,删除(选右键下的DELETE VERTEX),请利用EDIT-VERTEX或按F7键.即可修整端点自动整线有Route-Custom Smooth或Route-Gloss可执行SPECCTRA自动布线当您执行ROUTE一SPECCTRA-Auto儿时Allegro会发起SPECCTRA的自动布线程序并建立一个同档名的.dsn檔.在自动布线结束后SPECCTRA会产生一个.ses檔在回到Allegro时转入成已布线档SPECCTRA手动布线执行ROUTE一SPECCTRA-Interactive,可转档到Specctra并以其EditRoute作手动布线产生未布线报表在布线完毕后.我们如果要确定定否有未布线点仍然存在.可以执行TOOLS一Reports选输出的资料为Unconnected pins再点Run键就会产生此报表加以查核CHAPTER 7 内层及铺铜如果您的设计超过二层,那么您就须要设定其内层铜箔的效果包括它的铺铜箔效果,所带的讯号名,避开的间距,内层切割等等的问题通常铜箔分二种,正片铜及负片铜.正片铜显示的是含铜的部分,也就是黑的部分以后就是铜箔.在Allegro中的正片铜您可以看到它所挖开的开孔void 及所接的梅花瓣Thermal 它的缺点是一但铜箔的接续性更改如移零件或贯孔.则铜箔须要重铺以重新连结正确的梅花瓣及挖开不同讯号点负片铜显示的是以后要挖掉铜的部分,反而是白色的部分以后才会有铺铜在Allegro中负片铜只是显示一些点在内层上面.随着所设定的讯号.程序会自动判定那些点该是要改成内层要接的Thermal Relief定义效果,那些不接的点其内层必须是挖开的Anti-Pad定义.Allegro并不会把那些焊点挂在层面上.好处是零件或是贯孔可随意移动不须重铺重算.只有在他产生底片输出时才会将焊点数据并入处理.而它的缺点是您无法在图上即看到真实的底片效果.(尤其是梅花瓣)宣告内层负片铜l.Add一Shape一Solid Fill画内层铺铜范围2.Edit一Change Net(Pick)宣告铜箔的讯号名3.Shape一Fill填铜箔1请开cds_routed.brd檔.设定Setup一Drawing Options在Display项目中勾选Thermal Pads(显示梅花瓣) 及Filled Pads and Cline Endcaps(填满式显示)选项2 选Display一Color/Visibility把Group项目改成Stack再把底下的Etch项全关只留VCC层.其它项的PIN与VIA也是只留VCC后跳出3选Add一Shape一Solid Fill在右侧设Etch及VCC层,在板内的走线区范围内Route Keepin画一个Polygon画完按右键Done结束4宣告内层讯号选Edit一Change Net(Name)在列表中选VCC后跳出5填铜箔.选Shape一Fill这样会灌满并显示出Thermal Pad(单线)及AntiPad的效果宣告内层正片铜l.Add一Shape一Solid Fill画内层铺铜范围2.Edit一Change Net(Pick)宣告铜箔的讯号名3Shape一Parameter设定自动挖开铜箔的效果4V oid一Auto执自动清铜动作(讯号不同者挖开,相同者挖开后架上桥接花辫)5Shape一Fill填满铜箔效果1 选Display一Color/Visibility把Group项目改成Stack再把底下的Etch项全关只留GND层.其它项的PIN与VIA也是只留GND后跳出2选Add一Shape一Solid Fill在右侧设Etch及GND层,在板内的走线区范围内Route Keepin画一个Polygon画完按右键Done结束3宣告内层讯号选Edit一Change Net(Name)在列表中选GND后跳出4选Shape一Parameters设定挖开的项目,间距值,效果等参数5选V oid一Auto在跑了几秒后可看到铜箔该接的变成正片的梅花瓣.不该接的自动避开挖空。
ALLEGRO 基本使用指南一. 常用术语和概念PCB(Printed Circuit Board):印刷电路板,指所有具有互关系的元器件放在一块指定大小、形状、由特殊材料叠加而成、实现一定电路功能的线路板。
Symbol:器件封装Pad :焊盘Etch: 线,用于接各pin 点以实现物理电路功能.Line width :线宽,连接线的宽度。
Spacing : 线距,连接线与连接线、pin 等之间的距离.Outline: 板边Rats:飞线,指释各pin 点间连接关系的虚线。
DRC:PCB 板上产生短路及各种不符合约束规则时产生的报错标志.Shape:铜铂Via :过孔Text :丝印,也称文字。
Top 层:PCB 板表面层. Bot 层:PCB 板底面层。
内层:压合在PCB 板内的,用于布线和电源使用。
spacingtopFR4In1FR4 内层FR4二.ALLEGRO 菜单的使用 File 菜单:File\new 命令:建一个文档,如图2—1-1…进行选择;在在Drawing Name 中输入新文档的保存路径及名称,可点击B B r r o o w w s s e e…Drawing_Type:的下拉栏中选择要新建的文档的格式,主要有以下几种:Board/board(wizard):新建一个.brd文档;Module:Package symbol:/Package symbol(wizard):Mechanical symbol:Format symbol:Shape symbol:Flash symbol:本文只介召.brd 文档的建立,其它各模块暂不说明。
File\open命令:打开一个已经存在的文档。
File\save命令:保存一个文档。
File\save as…命令: 将文档以其它名字保存.注意:ALLEGRO 进行此命令后,当前正在编辑的文档也将随这更名。
Import/export命令:此部份将在后面中会介召。
Cadence allegro菜单解释——file已有 320 次阅读2009-8-16 19:17|个人分类:工作|关键词:Cadence allegro file 菜单解释每一款软件几乎都有File菜单,接下来详细解释一下allegro与其他软件不同的菜单。
new新建PCB文件,点new菜单进入对话框后,drawing type里面包含有9个选项,一般我们如果设计PCB就选择默认第一个board即可。
如果我们要建封装库选package symbol即可,其他7个选项一般很少用,大家可以理解字面意思就可以知道什么意思了。
open打开你所要设计的 PCB文件,或者封装库文件。
recent designs打开你所设计的PCB文件,一般是指近期所设计的或者打开过的PCB文件。
save保存save as另存为,重命名。
importimport 菜单包含许多项,下面详细解释一下我们经常用到的命令。
logic 导入网表,详细介绍在allegro基础教程连载已经有介绍,在此不再详细介绍。
artwork 导入从其他PCB文件导出的.art的文件。
一般很少用词命令。
命令IPF和stream 很少用,略。
DXF 导入结构要素图或者其他DXF的文件。
导入方法如下:点import/DXF后,在弹出的对话框选择,在DXF file里选择你要导入的DXF的路径,DXF units 选择MM,然后勾选use default text table和incremental addition,其他默认即可。
再点edit/view layers弹出对话框,勾选select all,DXF layer filter选择all,即为导入所有层的信息,然后在下面的class里选择board geometry,subclass选择assembly_notes,因为一般导入结构要素图都是导入这一层,然后点ok,进入了点import/DXF后弹出的对话框,然后点import即可将结构要素图导入。
一.PCB中各种词汇的解释:1.Primary Component Side 主元件面层2.Ground Plane 地平面层3.Power Plane 电源平面层4.Secondary Componnet Side 次元件面层21.Solder Mask Top 顶层阻焊(只有焊盘,没有过孔)22.Paste Mask Bottom 底层钢网图23.Paste Mask Top 顶层钢网图(表层要焊的焊盘,不包括圆形焊盘)24.Drill Drawing 钻孔图(PLTD成铜,呈白色)26.Silkscreen Top 顶层丝印图(所有元件名)27.Assembly Drawing Top 顶层装配图(外壳)28.Solder Mask Bottom 底层阻焊29.Silkscreen Bottom 底层丝印图30.Assembly Drawing Bottom 底层装配图Pads 焊盘Traces 走线Vias 过孔Lines 二维线Text 文字Copper 铜皮Ref.De 元件名Keepout 禁止区域Top 顶层Bottom 底层Background 背景色Selections 选中对象的颜色Highligh 高亮(命令为Ctrl+H,取消命令为Ctrl+U)Board 板框色Connection 鼠线(没有连通的线)Pin 元件脚Decals 封装(脚位图)Select Components(元件)Clusters(簇)Nets(网络)Pin Pairs(管脚对)Shapes(形状)Documentation(文字)Board Outline(板框)Tools:Decal Editor 元件编辑器Pour Manager 灌铜管理器Verify Design 设计规则检查(详见P209)L3 显示当前的第3层(快速换层的显示方法)二.单面板制作流程:设计准备:1.调出原理图(用PowerLogic)先点Connect to PowerPCB2.先点Tools→OLE PowerPCB Connection,然后把Preferences中的Parts/Nets/Compare PCB Decal Assignment这3个点亮3.然后点Design中Compare PCB 同原理图PCB相比较Rules To PCB 把原理图的参数同步到PCB里面去Send Netlist 生成网表,对不同软件间的转换Synchronize PCB 同步到PCB里面去(选取)Rules From PCB 把PCB的参数同步到原理图里面去Synchronize SCH 把PCB的所有东西反同步到原理图里面来4.把同步到PCB里去的所有元件打散以及颜色的设定:①全部选中→右键中的Disperse(打散)。
PADS 中英文对照PADS PCB:一 Setup1、Preference优先设置⑴ global◆ Pick Radius捕捉半径◆ Keep Same View on Window Resize设计环境窗口变化是否保持同一视图◆ Active Layer Comes to Front激活的曾显示在最上面层◆ Minimum Display Width最小显示线宽,如果当前PCB 板中有小于这个值的线宽时,则此线不以其真实线宽显示而只显示其中心线◆ Drag and attach附属拖动◆ Drag and drop放下拖动对象就可完成移动◆ No Drag Move禁止采用拖取移动方式⑵ Design◆ Stretch Trace During Component Move移动元件时保持走线链接◆ Miter倒角◆ Keep Signal and Part Name保持信号和元件名称◆ Include Traces not Attached定义一个区域时,内部包含的和块内没有相同网络的连接也作为块的一部分◆ Line/Trace Angle 2D和走线的角度◆ Drill oversize对沉铜进行全景补偿⑶ Routing◆ Generate Teardrops产生泪滴◆ Show Guard Band显示保护带,如果违反了操作,会在违规的临界点上用一个八边形来阻止用户的操作,可通过On-Line DRC设置◆ Highlight Current Net当前选中的或正在操作的网络是否要高亮显示◆ Show Drills Holes是否显示钻孔◆ Show Tracks是否显示Tack,Tack是一种错误标志,当在层定义里定义的走线方向和实际的走向不一致时,就会有这种菱形的标记出现◆ Show Protection显示保护线◆ Show Test Points显示测试点,如果关闭此选项,测试点和过孔就表现为相同的形式了◆ Show Trace Length显示线长,实时地显示走线的长度和已布线的总长度◆ Centering-Maximum Channel设置最大的通道长度◆ Unrouted Path Double Click用鼠标双击未连接的飞线,通过设置可以产生两种结果,一种是自动连线(Dynamic Route),一种是手动连线(Add Route),如果是自动连线,最好打开在线检查设计规则On-Line DRC◆ Auto Protect Traces自动保护走线,保护一个网络的走线,包括长度受控的网络和走线末端的过孔◆ Enable Bus Route Smoothing使总线圆滑,当完成总线布线后,进行一个圆滑的动作,这个设置只在总线布线模式下有效,它的优先级高于全局优化的优先级◆ Guide Pad Entry允许连线以任何角度和焊盘连接◆ Smooth Pad Entry/Exit允许对和焊盘成90°的连线进行优化,优化为45°的连线◆ Minimum Amplitude(Times Trace Width)蛇形走线的高度,这个高度是按照线宽的整数倍来设置的◆ Minimum Gap(Times Trace to Trace Clearance)蛇形走线时GAP的宽度,这个宽度是按照垂直线之间距离的整数倍来设置的◆ Thermals热焊盘在电源和地层也称为花孔,为了对电路板进行好的屏蔽,通常会在顶层和底层甚至中间层铺大量的铜皮,并将其与地网络连接在一起,铜皮 与地网络连接的过孔或焊盘称为热焊盘,通常分为两种:通孔热焊盘(Drilled Thermals)和表面贴装的热焊盘(Non-drilled Thermals)·Width热焊盘连接线的线宽·Min.Spoke最少连接线,一个热焊盘上至少有几根连接线·Pad Shape焊盘形状·Flood over填满,创建完全连接的热焊盘·Orthogonal正交,连线和焊盘的连接角度为正交·No Connect不形成热焊盘·Routed Pad Thermals元件的焊盘也可以形成热焊盘·Show Genernal Plane Indicators是否显示内层的热焊盘,关闭这个选项,热焊盘就表现为通常的焊盘了·Remove Isolated Copper移除孤立的铜皮·Remove violating Thermal Spokes移除冲突的热焊盘连接,违反规则的连接线应该被移除◆ Auto Dimensioning自动尺寸标注·General Settings通用设置·Draw 1st起点标注线·Draw 2nd终点标注线·Pick Gap测量点到尺寸标注线一端之间的距离·Circle Dimension圆弧测量·Alignment and Arrow校准直线和标注箭头·Alignment tool校直工具·Text尺寸标注值文字·Omit Text不需要尺寸标注文字◆ Teardrops泪滴·Auto Adjust允许在设计过程中根据不同的要求来自动调整泪滴◆ Drafting·Board component height restriction板上元件高度限制·See through将铜皮显示成一些Hatch平行线·Min.hatch最小铜皮面积·Smoothing铜皮在拐角处的平滑度·Pour outline显示整块铜皮的外框·Hatch outline显示铜皮(Pour)中每一个Hatch的外框◆ Grids·Fanout Grid扇出栅格,仅用于BlazeRouter·Radial Move Setup径向移动·Inner Radius靠近原点的第一个圆环跟原点的径向距离·Delta Radius除第一个圆环外,其他各圆环之间的径向距离·Sites Per Ring在移动角度范围内最小移动角度的个数·Auto Rotate移动元件时自动调整元件状态·Disperse移动元件时自动疏散元件·Use Discrete Radius移动元件时可以在径向上进行不连续地移动元件·Initial使用最初的·Let me Specify极的方向由自己设置◆ Split/Mixed Plane混合分割层·Plane Polygon Outline只显示分割层的外框·Plane Thermal Indicators除了显示分割层以外还要显示热焊盘·Generated Plane Date显示分割层上的所有数据·Smoothing Radius设置分割层的铜皮的平滑度·Auto Separate Gap设置分割的各个平面之间的距离·Use Design Rules for Thermals and Antipads对花孔和反焊盘使用设计规则·Die component模具元件2、Layer Definition叠层设置◆ No Plane布线层◆ CAM Plane整个的平面层,比如电源和地层等◆ Split/Mixed Plane分割后的平面层,比如存在多种电源和地的平面层3、Pad Stacks焊盘叠设置4、Drill Pairs钻孔层对设置5、Jumpers跳线设置6、ECO(Engineering Change Order)工程变更设置◆ Write ECO files记录ECO文件◆ Append to files追加到文件中◆ Write ECO file after close ECO toolbox在关闭ECO工具盒或者退出ECO模式时,更新ECO文件数据7、Design Rules设计规则设置设计规则优先级:(低)Default->Layer->Class->Net->Group->Pin pairs(高)◆ Default默认设置·Drill to Drill钻孔之间·Body to Body元件体之间·Clearance-Pad(通孔焊盘)、SMD(表贴焊盘)、Board(板框)·Protected不对飞线进行优化·Minimized采用网络的所有管脚对的连接最短的规则来产生飞线·Serial Source对ECL电路适用,多个驱动源串在一起·Parallel Source对ECL电路适用,多个驱动源并在一起·Mid-driven这个规则适用于高速电路和ECL电路,最小化网络中所有管脚对的距离,中间驱动意味着网络可以尽量短,如果是一个源两个接收端的话,那么这个拓扑表现为源在中间接收端在两边,并且源到两个接收端等长·Copper sharing铜皮共享一via过孔的铜皮共享·Auto Route自动布线器可以自动对网络布线·Allow Ripup自动布线器在布一个已经布过的网络时,允许删除现有的走线·Allow Shove自动推挤功能,可以对一个已布的网络进行推挤和重布·Allow Shove Protected自动布线器可以对一个已布的并且受保护的网络进行推挤和重布·Layer Biasing设置约束生效的层·Vias选择定义的过孔·Parallelism平行长度·Tandem纵向平行度·Aggressor此网络是否是干扰源,可以定义电流较大和速率较高的信号为干扰源·Shielding使用屏蔽功能,减少外界的干扰,通常用平面层作屏蔽信号·Gap网络同屏蔽网络走线之间的距离·Use Net屏蔽的网络·Stub走线中出现分支会难以控制匹配和端接,较长的分支会引起反射以及过冲,所以要加以约束·Match Length要求长度匹配·Fanout Length扇出的长度·Nets扇出的类型·Pad Entry Quality焊盘引入的质量控制,在BlazeRouter中有效·Via at SMD焊盘下放置过孔◆ Class类设置◆ Net网络设置◆ Group组设置◆ Pin Pairs管脚对设置◆ Decal封装设置◆ Component元件设置◆ Conditional Rules条件规则设置◆ Differentia Pairs差分对设置◆ Report报表设置二 Tools工具设置1、Automatic Cluster Placement簇的自动布局◆ Build Clusters创建簇·Min.Top Level Count最小的顶层簇的数量·Unglued Parts Number当前没有被锁定的元件的数目·Build Mode创建模式,簇分为open簇和close簇,其区别在于是否在Query/Modify窗口选中了close选项,在选择创建模式的时 候,Rebuild open clusters指open的簇可以拆开重建Maintain Open Clusters指要保留open属性的簇◆ Place Clusters放置簇·Board Outline Clearance簇到板框的最小间距·Percent Part Expansion簇之间的距离·Efforts布局的努力程度·Number of Iterations簇布局的次数·Attemps Per Iterations每次布局的尝试·% From Part Swappling元件、簇或组合交换的频率·Create Pass大范围的布局·Refine Pass小范围的微调◆ Place Parts放置元件·Eliminate Overlaps是否要消除元件重叠的情况·Min % Expansion Allowed最小的元件空间扩展的比例·Align Parts布局微调时,相邻的元件是否要对齐·Only if No Overlaps相邻的元件要对齐的前提是没有元件叠加的情况2、Disperse Componets打散元件3、Length Minimization长度最小化4、Cluster Manager簇管理器5、Auto Nudge自动推挤6、Specctra是Cadence公司的自动布线器7、DX-Designer反标注8、BoardSim板级防真9、BlazeRouter自动布线器10、CAM350菲林输出11、Pour Manager灌铜管理器12、Assembly Options装配选项13、Verify Design验证设计14、Compare Test Points比较测试点15、Compare/ECO Tools比较网络表16、DFT Audit(Design For Test)自动为设计插入测试点。
三款EDA工具,AD、PADS与Allegro的简单介绍一、市面上原理图设计和pcb绘制的软件主要有如下三个:1、Altium Designer(简称AD)2、PADS3、Cadence的Allegro(简称阿狸狗)二、三款软件的简单介绍Altium Designer:优点:1、软件界面友好,操作简单,适合入门,由于前身是protel99SE,有广大的学生会使用,有很好的群众基础。
2、绘制原理图和PCB都是在同一个软件。
缺点:1、非常吃电脑内存,一般的电脑用起来非常慢,需要配置比较高的电脑。
2、AD的容错率较差,如果粗心一点那么很可能导致出错。
3、大型公司使用AD比较少,工作上升空间不大。
应用场景:主要是一些简单的双层及四层板,市面上小型产品使用较多。
PADS:特点:有三个界面:PADS Logic 、PADS Layout 、PADS RouterPADS Logic用于原理图设计PADS Layout用于布局PADS Router用于布线应用场景:PADS目前主要流行在沿海地区,比如说广州、深圳。
PADS主要用在消费类电子产品,早期的VCD,DVD,MP3 ,MP4,U盘,液晶电视,到现在的平板电脑,行车记录仪,车载电子产品,导航仪,数字机顶盒,安卓智能电视盒、手机等都是由PADS绘制的。
PADS界面比较简单,上手还是比较容易的。
而且PAD画一下比较大型的板子比较好,在一些沿海发达地区找工作还是较为容易,薪资上升空间也不错。
Allegro:Allegro应该叫Cadence allegro。
Cadence是公司名,allegro是该公司旗下的设计软件,一般用OrCAD Capture画原理图,用Allegro画PCB。
优点:功能强大。
缺点:不好学,不容易上手。
应用:allegro一般只有大公司用,特别是做电脑主板的公司用,因为这个软件功能强大,画大型板子有优势。
如电脑主板,大型工控板,服务器主板,等大型板子,他的效率和优势非常明显。
电子设计开发平台PADS2Allegro切换方案推荐设计平台:Cadence Allegro电子产品设计开发平台推荐产品类型:原理图设计+ 原理图功能仿真+高速PCB设计平台切换前提:见1.1详细说明电子设计平台切换方案概要1.1 设计平台切换方案软件要求软件要求:PADS Logic原理图工具DxDesigner原理图工具PADS Layout布局布线工具Cadence Design Entry CIS原理图工具Cadence Allegro PCB Designer布局布线工具1.2 原理图切换方案PADS Logic原理图可以通过EDIF格式的原理图数据,直接导入Cadence Design Entry CIS 原理图环境中,可以实现PADS Logic原理图向Design Entry CIS原理图的数据切换,其具体过程如下所述。
(1)PADS Logic环境中设计原理图(2)DxDesigner环境中导入PADS Logic原理图数据执行File/Import/PADS命令,在Symbol &Schematic Translators: PADS Logic to DxDesignerNetlist对话框中,设置转换参数即可将PADS Logic设计的原理图*.sch文件,转换为DxDesigner原理图。
其中转换窗口中的设置如下:Schematics——设置需要转换的PADS Logic原理图设计;Libraries——设置器件库;Mapping——设置PADS Logic环境中符号属性与DxDesigner环境中符号属性的对应关系。
(3)DxDesigner原理图导出EDIF原理图在DxDesigner环境中执行File/Export/EDIF Schematic命令,将DxDesigner原理图导出EDIF格式原理图数据*.eds。
(4)Design Entry CIS环境导入EDIF原理图在Cadence Design Entry CIS原理图设计环境中,执行File/Import Design命令,在弹出的Import Design窗口中,选择需要切换的原理图数据*.eds文件,如下图所示:其中Import Design转换设置如下:Open——需要转换的原理图EDIF格式数据;Save As——指定EDIF原理图切换至Design Entry CIS原理图的设置;Configuration——选择原理图切换进程的配置文件EDI2CAP.CFG。
CadenceAllegro简易手册连载2:零件的整备Allegro是Cadence推出的先进PCB设计布线工具。
Allegro提供了良好且交互的工作接口和强大完善的功能,和它前端产品Cadence、OrCAD、Capture的结合,为当前高速、高密度、多层的复杂PCB 设计布线提供了最完美解决方案。
本文介绍了Cadence Allegro零件的整备。
Cadence Allegro简易手册连载1:熟悉环境CHAPTER 2 零件的整备本阶段要试建一颗14PIN DIP 零件零件的组成有焊点 PADSACK,零件Package symbol每一个接脚PIN及孔Via皆视为一焊点PADSTACK如以60-38为例进入程序开始→程序集→cadence →PCB Systems→PAD Designer改种类为贯孔Through,单位为mil,精确值为1 (小数后1位),焊点在每一铜箔层皆要有一般点regular PAD,梅花瓣Thermal-relief PAD,挖开点Anti-PAD的三种效果1、选Layer 页面2、点选Begin Layer3、在一般点项目设形状为Circlewidth为60height为604、在梅花瓣设形状为circle,值为80,Flash项目为TR805、在挖开点设形状为circle,值为80,由于其它层设定相仿,可点左侧Bgn按右键copy复制。
6、点internal 的左侧,按右键选右键paste即可贴入,不须重key in7、以同样方法贴到END层8、在SOLDERMASK_TOP层的Regular PAD设circle,大小为709、一样复制到SOLDERMASK_BOTTOM钻孔定义如果定为Through-Hole焊点,须定孔径及钻孔符号在Drill Hole 项目中定Plate Type 为Plated (孔壁镀铜),孔径38. Drill symbol的Figure为钻孔符号效果,Character为标示字符串,Widthheight为符号的宽及高储存焊点选File →Save as 存到C:\allegroclass \ user1 档名为60C38d.PAD实体零件的建立建立实体零件的格式不同,所以须进入零件建立模式下1、File / New 在DRAWING NAME中敲入新零件名,如DIP14并在DRAWING TYPE中选PACKAGE SYMBOL2、设作图环境选SETUP –DRAWING SIZE在Move Origin项目中的XY各敲入5000使原点调整至适当位置3、加入焊点,选ADD PIN或其图示,并右侧OPTION项目中敲入焊点60S38D后按Tab键状态列会显示出Using ‘60S38D.PAD’4、光标移至状态列点选后敲入x00,会把第一接点放到原点00的位置上(x须为小写),窗口缩放到PIN1附近5、在右侧OPTION中改焊点为60C38D后按Tab键,在Y的Qty项目中输入66、在状态列输 x 0 100则会放入向下距100mil的2~7接点7、把Y项目的Qty改7个,次序order改up8、状态列输入x 300 –600,会放入第8PIN到14PIN之焊点,但是其脚号仍位于焊点左侧可按右键之OOP取消9、将OPTION中的OFFSET值由-100改为100 (表右边100mil 处),于状态列输入x 300 -60010、完成按右键中的DONE文字面绘制 SILKSCREEN要调整格点大小时,请以SETUP /GRIDS将NON-ETCH的X、Y 值键入25,表文字面绘制格点为251、选ADD/LINE2、将右侧OPTION选为Package Geometry下的SILKSCREEN_TOP,设画线角度等3、画上文字面的矩形框组装外型绘制Assembly outline (可省略)同文字面之动作但层面为Package Geometry下的Assembly-Top设文字面之零件名称及零件号1、选Layout_Label →Ref Des或其图示2、图面为 refDes下的Assembly_Top3、点选放零件名称的好位置(须在Assembly outline中)4、键入名称如U* (请先注意右侧的字体基准点角度)5、选Layout_Label中→Device6、选适当的位置后键入 dev type后按右键的DONE绘制零件限制区Package boundary (可省略自动抓)定义零件高度(需要有Package boundary才可定义)1、Setup-Area-Package Boundry Height层面为Package Geometry下的Place_Bound_Top2、点先前建的Package Boundry 区域3、输入高度值如180若没设则以Drawing option下的symbol Height为其内定高度值存零件文件(两者都要存)1、选File → Create Symbol存成可放到PCB上的.PSM檔2、选File →SAVE存成供以后修改的图形.DRA檔以自动程序建零件利用Symbol Wizard填入参数自动建零件1、File /New后在Drawing Name键入名称,如dip16,在Drawing type选Package Symbol [Wizard] 后,选OK2、选Package Type为dip后点Next (选零件包装)3、套用CADENDCE规划选Default Cadence Supplied template,套用其它零件则选Custom template后选.Dra档套入,后选Next4、设定使用的公英制,准确位数及名称前字符串prefix5、依不同零件外形,设定其参数,如脚数Number of Pins,脚距LeadPitch,行距Terminal row spacing,文字面的宽及长Width&Length)6、选套用的焊点(一般焊点及第一脚)7、定零件原点为中心center of body或第一脚pin1 of symbol 及是否另存.PSM檔8、选Finish,即OK。
Cadence allegro菜单解释——file已有 320 次阅读2009-8-16 19:17|个人分类:工作|关键词:Cadence allegro file 菜单解释每一款软件几乎都有File菜单,接下来详细解释一下allegro与其他软件不同的菜单。
new新建PCB文件,点new菜单进入对话框后,drawing type里面包含有9个选项,一般我们如果设计PCB就选择默认第一个board即可。
如果我们要建封装库选package symbol即可,其他7个选项一般很少用,大家可以理解字面意思就可以知道什么意思了。
open打开你所要设计的 PCB文件,或者封装库文件。
recent designs打开你所设计的PCB文件,一般是指近期所设计的或者打开过的PCB文件。
save保存save as另存为,重命名。
importimport 菜单包含许多项,下面详细解释一下我们经常用到的命令。
logic 导入网表,详细介绍在allegro基础教程连载已经有介绍,在此不再详细介绍。
artwork 导入从其他PCB文件导出的.art的文件。
一般很少用词命令。
命令IPF和stream 很少用,略。
DXF 导入结构要素图或者其他DXF的文件。
导入方法如下:点import/DXF后,在弹出的对话框选择,在DXF file里选择你要导入的DXF的路径,DXF units 选择MM,然后勾选use default text table和incremental addition,其他默认即可。
再点edit/view layers弹出对话框,勾选select all,DXF layer filter选择all,即为导入所有层的信息,然后在下面的class里选择board geometry,subclass选择assembly_notes,因为一般导入结构要素图都是导入这一层,然后点ok,进入了点import/DXF后弹出的对话框,然后点import即可将结构要素图导入。
基本术语SMD: Surface Mount Devices/表面贴装元件。
RA:Resistor Arrays/排阻。
MELF:Metal electrode face components/金属电极无引线端面元件.SOT:Small outline transistor/小外形晶体管。
SOD:Small outline diode/小外形二极管。
SOIC:Small outline Integrated Circuits/小外形集成电路.SSOIC: Shrink Small Outline Integrated Circuits/缩小外形集成电路.SOP: Small Outline Package Integrated Circuits/小外形封装集成电路.SSOP: Shrink Small Outline Package Integrated Circuits/缩小外形封装集成电路.TSOP: Thin Small Outline Package/薄小外形封装.TSSOP: Thin Shrink Small Outline Package/薄缩小外形封装.CFP: Ceramic Flat Packs/陶瓷扁平封装.SOJ:Small outline I ntegrated Circuits with J Leads/ “J”形引脚小外形集成电路.PQFP:Plastic Quad Flat Pack/塑料方形扁平封装。
SQFP:Shrink Quad Flat Pack/缩小方形扁平封装。
CQFP:Ceramic Quad Flat Pack/陶瓷方形扁平封装。
PLCC:Plastic leaded chip carriers/塑料封装有引线芯片载体。
LCC :Leadless ceramic chip carriers/无引线陶瓷芯片载体。
DIP:Dual-In-Line components/双列引脚元件。
第一部分Concept HDL 第二部分 Allegro菜单栏文件、编辑、察看、器件、连线、文本、模块、组、显示、PSpice、工具、窗口、帮助1.文件菜单原菜单新建打开关闭保存另存为保存所有保存层转换恢复移动编辑页和符号编辑层返回改变组件察看搜索栈物理输出物理输入 IFF输入打印设置打印预览打印输出中文菜单下一层菜单见下表同上设置启动的工具进行封装并输出从Allegro导入导入IFF文件可输出原理图说明退出注:若菜单中的说明项为空,则表示不不需要说明或说明项与中文菜单相似。
以下相同。
下一页前一页转向2.编辑菜单撤销重做加入新页下一层上一层移动复制复制所有重复复制排列删除颜色分割镜像翻转旋转模块顺序画弧画圆3.察看菜单放大矩形范围放大到满屏放大缩小按比例放大上移下移左移右移预览网格设定状态条错误信息条控制窗口数据栏工具栏4.器件菜单添加器件替换器件改变版本修改部分交换针脚删除可改变器件符号的显示类型可设置器件在封装中的位置5.连线菜单连线连线添加信号名添加总线名连结总线设定总线参数画点连线加粗连线减细6.文本菜单特性设置习惯设置器件赋值理性文本设置端点的名称添加注释打开文本文档设置字体大小放大缩小交换重新连结显示名称显示值两样都显示7.模块菜单添加重命名扩展连线连线添加针脚重命名针删除针脚移动针脚不可见特性显示可对电阻电容等进行赋值下一层菜单如下设置连线的图案需要从一点画到另一点点击两点自动连线输入针脚输出针脚8.组菜单创建组设定当前组显示组的内容移动复制复制全部设置复制个数设置文字大小改变注释删除设定颜色激活器件特性显示矩形框内创建为一组多边形框内创建为一组用表达式创建下一个在组中去除一个器件替换改变显示版本删除显示名称显示值两样都显示9.显示菜单激活去激活联系颜色器件信息连结显示信号名和文本与器件的连结关系不可见修改在组中添加一个器件下一层菜单在下表双向针脚显示点的坐标显示目录显示距离显示历史信息设置快捷键显示修改信息显示线网信息显示端点针脚针脚名显示特性返回显示字体尺寸10.Pspice菜单创建仿真文件编辑仿真文件删除仿真文件检查生成网表查看网表运行查看结果编辑模型编辑激励仿真多重文件11.工具菜单扩展设计取消扩展当前编辑全局查找全局导航限制管理器检查显示错误显示错误及告警信息运行script文件反标仿真模拟数据点击一点点击两点,在下方状态栏显示点击线网显示所有的针脚显示点击的器件的针脚名显示所有器件的针脚信息在下方状态栏显示查找某一个器件可查出某个器件属于哪个库进行错误检查将封装后的信息标注在原理图层次编辑生成符号图封装应用程序设计差别比较设计联系习惯设置选项可用于层次设计下一层菜单如下表可将原理图的修改更新到板子可编辑设计环境、快捷键等可设置栅格尺寸等材料清单电气规则检查生成网表报告12.窗口菜单新开一个窗口刷新层叠平铺排列图标当前激活的窗口13.帮助菜单帮助主题新增功能主要帮助常见问题及解决方法产品说明 Cadence文件关于Concept-HDL可链接到Cadence公司网站显示版本信息将多个窗口层叠摆放将多个窗口平铺展开第二部分 Allegro菜单栏文件、编辑、察看、添加、显示、设置、逻辑、布局、布线、分析、制造、工具、帮助1. 文件菜单新建打开保存另存为导入导出查看日志打开日志打印设置打印改变编辑器生成说明文件退出2. 编辑菜单移动复制镜像旋转修改删除生成图形删除未连结的图形分割平面倒角删除倒角文本分组特性设定3.查看菜单放大矩形范围修改器件边角放大至满屏放大缩小放大整个范围以一点为中心放大保存镜像文件镜像文件恢复刷新4.添加菜单线弧形 3点弧形圆四边形填充的四边形文本实心填充不填充5.显示菜单颜色设置显示颜色面板元件信息测量寄生参数特性设置激活去激活显示飞线6.设置菜单画图尺寸画图选择文字大小网格设置不显示飞线交叉线网填充图形习惯设置子目录层结构过孔设置限制设置电气规则设定特性定义线网定义7.逻辑菜单线网逻辑线网方案设置差分对标识直流线网设置RefDes 自动命名RefDes 改变器件终端设定重命名重命名整个设计重命名一个区域内元件重命名窗口内元件8.布局菜单手工布局快速放置在CCT中布局自动布局交互式布局交换自动交换调整重命名列表中的元件更新符号临时使用SPECCTRAQuest交换针脚交换功能交换元件可视布局参数设定布局布顶层元件布底层元件布设计中的元件布指定区域的元件布窗口中的元件布列表中的元件参数设定交换设计内容交换指定区域交换窗口内容交换列表内容参数设定调整整个设计调整指定区域调整窗口中内容调整列表内容器件9.布线菜单连线倒角光滑边角在CCT中布线优化运行布线检查选择式布线自动布线交互编辑测试准备符号参数设定优化设计优化指定区域优化窗口优化激活内容自动设置生成测试点删除测试点交换测试点测试记录优化列表内容10.分析菜单审查报告执行报告11.制造菜单图样设置影像文件设定文件输出钻孔参数设定设置标识制造检查设置测试内容丝印层设置钻孔参数钻孔图例钻孔记录文件输出生成组装图生成材料清单参数设置设置字体类型测直线距离测角度生成详细说明生成报告13.工具菜单创建模块焊盘编辑焊盘去除连结报告技术文件比较可进行有关焊盘的操作。
Allegro to PADS® TranslatorUser’s GuidePADS 9.4© 1987-2012 Mentor Graphics CorporationAll rights reserved.This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonableThis document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made.The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever.MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.RESTRICTED RIGHTS LEGEND 03/97U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights. Use, duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227.7202-3(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - Restricted Rights clause at FAR 52.227-19, as applicable.Contractor/manufacturer is:Mentor Graphics Corporation8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.Telephone: 503.685.7000Toll-Free Telephone: 800.592.2210Website: SupportNet: /Send Feedback on Documentation: /doc_feedback_form TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a third-party Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics’ trademarks may be viewed at: /trademarks.Table of ContentsChapter 1Migrating Cadence Allegro Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Method 1—PADS and Allegro on the Same Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Method 2—PADS and Allegro on Different Machines. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Allegro Designs Translator Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Chapter 2Allegro to PADS Layout Translation Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Zero Size Pads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Decals and Design Graphics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Board Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 SMD Edge Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Lack of Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Create_devices Failure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..12 Exclamation mark (!) in the Design Board Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Disabling Board Refresh while Exporting Data with SKILL Scripts . . . . . . . . . . . . . . . . . .12 Allegro to PADS Mapping Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Chapter 3Error Codes and Log Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Third-Party InformationEnd-User License AgreementTable of ContentsChapter 1Migrating Cadence Allegro DesignsThe Cadence Allegro to PADS Layout design translator is one of a group of translators included with the PADS PCB Design Tools. It installs with PADS Layout.Tip: To find the version number of the translator, click the translator icon in the title bar, and select About Allegro Designs Translator.Supported VersionsThe translator supports up to version 16.3 of Allegro PCB.Restrictions•You must have access to both PADS Layout and to the Cadence Allegro PCB Editor in at least the XL version.•Only the “electrical” type data is translated.Choosing a MethodIf both applications reside on the same machine, use Method 1 to migrate the design. If they are on different machines, use Method 2.Method 1—PADS and Allegro on the Same MachinePerform the following steps to migrate an Allegro design to PADS Layout when PADS Layout and Allegro PCB Editor reside on the same machine.Procedure1.To prepare the Allegro design(s) for migration, copy the contents of the<PADS installdir>\SDD_HOME\translators\skill_scripts folder to:o Unix—the $HOME\pcbenv folder.o Windows—the %HOME% folder. For example, C:\SPB_Data\pcbenv2.Verify that the following "System" Variables are set prior to running "skill loaddfl_main.il" otherwise translator executable files do not properly generate correct output files and folders in the background.Migrating Cadence Allegro DesignsMethod 2—PADS and Allegro on Different MachinesAEX_BIN_ROOT=%SDD_HOME%\translators\win32\binAEX_ENABLE_JOBPREFS_LAYER_FIX=1Tip: Some environments remove the above Variables when you run The MGC SDDConfigurator. If this happens add them to "User" variables.3.For each design you want to translate:a.Create a new folder (for example C:\SPB_Data\convert_1), and copy into it theAllegro design (.brd) file you want to migrate.b.Open the .brd file, and in the Allegro command prompt window enter thesecommand lines:Command> skill load “dfl_main.il” (include quotes)Command> main outc.The “main out” opens the Allegro to Expedition Translator dialog box. Click theStart One Way Translation button.d.After the SKILL script has completed, any errors reported must be fixed, then rerunthe SKILL script. The migration will not complete correctly if all errors are notfixed. When completed, numuerous folders and files are generated under the newdesign folder you created in step a.4.Migrate the prepared Allegro design(s) (for example C:\SPB_Data\convert_1) to PADSLayout using one of the following steps:• A single design—In PADS Layout, use File > Import. This procedure automatically includes attributes. When migration completes, it is automatically opened in PADSLayout.•Multiple designs or to control attribute translation—Perform the following steps:i.From the Start Menu, run the Allegro to PADS Translator.ii.In the Allegro Designs Translator dialog box:a.Identify the location where you want the translated files placed.e the Add button to specify the files you want to translate.c.Specify whether or not to translate attributes.d.Click the Translate button. The output filename(s) will be in the formatdesign_##########.pcb.Method 2—PADS and Allegro on Different MachinesPerform the following steps to migrate an Allegro design to PADS Layout when PADS Layout and Allegro PCB Editor reside on different machines.Migrating Cadence Allegro DesignsMethod 2—PADS and Allegro on Different Machines Procedure1.On the PADS machine, copy..•The contents of the <PADS install dir>\SDD_HOME\translators\skill_scripts folder •The <PADS install dir>\SDD_HOME\translators\win32\bin\tech_translator.exe..to the Allegro machine in the $HOME\pcbenv folder (for exampleC:\SPB_Data\pcbenv).2.Set the AEX_BIN_ROOT environment variable to point to $HOME\pcbenv.3.Verify that the following "System" Variables are set prior to running "skill loaddfl_main.il" otherwise translator executable files do not properly generate correct output files and folders in the background.AEX_BIN_ROOT=%SDD_HOME%\translators\win32\binAEX_ENABLE_JOBPREFS_LAYER_FIX=1Tip: Some environments remove the above Variables when you run The MGC SDDConfigurator. If this happens add them to "User" variables.4.For each design you want to translate:a.Create a new folder (for example C:\SPB_Data\convert_1), and copy into it theAllegro design (.brd) file you want to migrate.b.Open the .brd file, and in the Allegro command prompt window enter thesecommand lines:Command> skill load “dfl_main.il” (include quotes)Command> main outc.The “main out” opens the Allegro to Expedition Translator dialog box. Click theStart One Way Translation button.d.After the SKILL script has completed, any errors reported must be fixed, then rerunthe SKILL script. The migration will not complete correctly if all errors are notfixed. When completed, numuerous folders and files are generated under the newdesign folder you created in step a.e.Zip-up and transfer the entire design folder (for example, C:\SPB_Data\convert_1)to the PADS machine.f.On the PADS machine, unzip to any location to migrate the prepared Allegrodesign(s) to PADS Layout.5.Migrate the prepared Allegro design(s) (for example C:\SPB_Data\convert_1) to PADSLayout using one of the following steps:• A single design—In PADS Layout, use File menu > Import. This procedure automatically includes attributes. When migration completes, it is automaticallyopened in PADS Layout.Migrating Cadence Allegro DesignsAllegro Designs Translator Dialog Box•Multiple designs or to control attribute translation—Perform the following steps:i.From the Start Menu, run the Allegro to PADS Translator.ii.In the Allegro Designs Translator dialog box:a.Identify the location where you want the translated files placed.e the Add button to specify the files you want to translate.c.Specify whether or not to translate attributes.iii.Click the Translate button. The output filename(s) will be in the formatdesign_##########.pcb.Related TopicsError Codes and Log MessagesAllegro Designs Translator Dialog BoxUse the Allegro Designs Translator dialog box to translate multiple Allegro designs and/or control attribute translation. When using the File > Import transtlation method, attributes are automatically translated.Accessing•Start menu > All Programs > Mentor Graphics SDD > PADS (version) > Translators > Allegro to PADS TranslatorMigrating Cadence Allegro DesignsAllegro Designs Translator Dialog BoxFigure 1-1. Designs TabTable 1-1. Designs Tab ContentsName DescriptionPlace translated files in Type the pathname of the folder where you want thetranslated files to be placed, or click the browse button tofind the folder.Log file Displays the location of the translation log file. When thetranslation completes, the Translation Results dialog boxdisplays the translation log.Migrating Cadence Allegro DesignsAllegro Designs Translator Dialog BoxRelated TopicsMigrating Cadence Allegro Designs Allegro files to translate Click the Add button to browse for Allegro .brd designfiles.Select and click Remove to take a design file out of thelist of designs that can be translated.Restrictions:•Filenames must be unique in the list.•Only designs whose check box is selected aretranslated.Update mapping Click to update the attribute mapping.Restriction: This button is unavailable until you add oneor more designs to translate.Translation Options area Translate attributesSelect this check box to translate Allegro attributes intoPADS attributes.Table 1-1. Designs Tab ContentsNameDescriptionChapter 2 Allegro to PADS Layout Translation NotesThis chapter describes differences between Allegro file content and PADS Layout file content, and possible discrepancies that can occur in translation.Zero Size PadsAllegro zero size pads are not supported by the translator. As a workaround, you can resize them to make them as small as possible (1 DBU), and put a message in the log file stating what these pads are.Decals and Design GraphicsDecals generated during the translation do NOT contain all the pertinent information that existed in Allegro (for example, notes, some graphics, etc). Therefore check the translated design closely.Board OutlineBoard outlines must be contiguous in Allegro to successfully translate into PADS. Check the board outline in Allegro to ensure that there are no gaps or opens.SMD Edge ConnectorsAn outstanding bug exists when sometimes the translator does not handle double-sided SMD edge connectors correctly. If the design has one of these connectors please double-check it after the translation in PADS. This problem typically occurs on designs that have an AGP / PCI type connector.Lack of MemoryDue to Windows OS limitations, the translator cannot allocate more than 2GB of memory. If you are translating a very large design, the translator may run out of memory and display an “Unable to allocate enough memory to translate current design” message.The suggested workaround is to configure Windows to provide 3GB virtual address space. To do this:Allegro to PADS Layout Translation NotesCreate_devices Failure1.Add /3GB to the Windows boot.ini file as described at/whdc/system/platform/server/PAE/PAEmem.mspx.2.Reboot your computer and start the translation again.Create_devices FailureSKILL scripts use the Allegro create_devices command to export device files to ...\devices in the design directory. If this command fails, data export cannot complete successfully. To complete the data export process, you must fix the design board to make the create_devices command work.One example of this problem is Allegro device names containing an equals sign (=). When the SKILL script encounters such a name, it removes the equals sign, which causes the Allegro create_devices command to fail. To resolve this problem, you must do one of the following: •Edit the device name in the Allegro schematic and forward annotate it to the board.•Remove the device from the Allegro design.Another example is device names longer than 32 characters. This causes a problem with exporting devices. If your job has device names that are longer than 32 characters, set the Allegro environment variable ALLEGRO_LONG_PACKAGE_NAME to TRUE.Exclamation mark (!) in the Design Board Path SKILL scripts create a temporary Allegro macro file with commands exporting part of the data. If the design board path contains an exclamation mark (!), the temporary macro file name also contains an exclamation mark; this causes the SKILL script to try to execute the temporary macro file with the replay command.Disabling Board Refresh while Exporting Data with SKILL ScriptsFor better performance, design board refresh is disabled while exporting data from Allegro with SKILL scripts.Allegro to PADS Layout Translation NotesAllegro to PADS Mapping Table Allegro to PADS Mapping TableThe following table shows the translation mapping of Allegro elements to PADS.Table 2-1. Allegro to PADS Mapping TableFrom Allegro Element: To PADS Element:LayersSupportedAssy_Line NotBoard Outline Board Outline objectBreak Outs Traces & Vias (Fanouts)Component_Body Outline_1User layer (Component Body Outline_1)Component_Body Outline_2User layer (Component Body Outline_2)DAM Not SupportedDielectric Not SupportedDimension_Keepout Not SupportedDrill Not SupportedError Not SupportedFixture_Outline Not SupportedForce Not SupportedGlue_Mask_1Not SupportedGlue_Mask_2Not SupportedHead_Insertion Not SupportedInsertion_Machine_Keepout User layer (Insertion)Milling Not SupportedOne-Way_Region User layer (One Way Region)Panel_Outline Not SupportedPaste_Mask_1Paste Mask TopPaste_Mask_2Paste Mask BottomPlace_1Layer 20 (Placement Outline)Place_2Layer 20 (Placement Outline)Placement_Keepout_1User layerPlacement_Keepout_2User layerAllegro to PADS Layout Translation NotesAllegro to PADS Mapping TableTable 2-1. Allegro to PADS Mapping Table From Allegro Element: To PADS Element:Placement_Region_1User layerPlacement_Region_2User layerPower Plane LayerPrepreg Not SupportedProbe_1 and Probe_2Not SupportedProbe_Area Not SupportedProbe_Symbol Not SupportedRouting_Keepout Keepout (Trace & Via)Shape_Edit Not SupportedSheet_Dielectric Not SupportedSignal_X Layer (Signal)Silkscreen_1Silkscreen Outline TopSilkscreen_2Silkscreen Outline BottomSolder_Paste_1Paste Mask TopSolder_Paste_2Paste Mask BottomSoldermask_1Soldermask TopSoldermask_2Soldermask BottomTest Points Test PointsTestPoint_Keepout Not SupportedTestPoint_Outline Not SupportedTestPoint_Reference Not SupportedThermal SupportedTrace Keepout Keepout (Trace)User Defined Layer User layerVia Keepout Keepout (Via)FabricationAperture Table Not SupportedArtwork Format Not SupportedArtwork Simulation Not SupportedArtwork Stackup Not SupportedAllegro to PADS Layout Translation NotesAllegro to PADS Mapping TableTable 2-1. Allegro to PADS Mapping TableFrom Allegro Element: To PADS Element:Drill Data Not SupportedDrill Simulation Not SupportedDrill Table Not SupportedMill Table Not SupportedFills, Keepouts, PlanesArea Fills Copper Pour or Plane AreaArea Fills (Protected)Copper Pour or Plane AreaArea Fill Tie Bar and Cutouts Not SupportedClassic Area Fills Copper Pour or Plane AreaCutouts Copper KeepoutCutouts (Protected)Copper KeepoutNo Connect Rules Not supportedPlacement Outline Not SupportedPower Fill Plane LayerRoute Keepout Keepout (Trace)Signal Layer Electrical LayerSplit Power Planes Plane LayerTrace Keepout Keepout (Trace)Via Keepout Keepout (Via)Visual-Text, Shapes, etc.Color map settings Not SupportedComponent Ref. Des. (Top)Ref. Des. on Silkscreen TopComponent Ref. Des. (Bottom)Ref. Des. on Silkscreen Bottom Dimensioning Not SupportedDrill Symbols SupportedGuides Not supportedNet Type Patterns Not SupportedPart Name Not SupportedPin Ref. Des.Pin NumbersShapes on User Defined Layers Shapes on User LayersAllegro to PADS Layout Translation NotesAllegro to PADS Mapping TableTable 2-1. Allegro to PADS Mapping TableFrom Allegro Element: To PADS Element:Shapes on Route Layers Shapes on Routing LayersTargets/Registration Marks Graphics on User LayersText on User Defined Layer Text on User LayerText on Route Layer Text (Keepout)Parts, Traces & ViasBlind Padstacks SMD PadstacksBlind/Buried Vias Buried ViasBlind/Buried Vias (Protected)Buried ViasBreak Outs Traces & ViasBreak Outs (Protected)Traces & ViasBreakouts (Component)TracesBuried Padstacks Only for 2 pin parts, maps to Buried PartComponent Type Rules Not SupportedComponents PartsComponents (Fixed)PartsComponents (Protected)PartsDrilled Holes Part HolesFixed Components PartsJumpers PartsMicroVias Vias (small diameter)MicroVias (Protected)Vias (small diameter)Mounting Holes Additional pins in decalNo Cleanup Vias ViasPins (Protected)PartsReuse Block (Primitive)Treated as single componentReuse Block (Replica linked)Components and tracesReuse Block (Replica un-linked)Treated as editable components & tracesReuse Block (Smashed linked)Components and tracesReuse Block (Smashed un-linked)Treated as editable components & tracesShield Trace TracesAllegro to PADS Layout Translation NotesAllegro to PADS Mapping TableTable 2-1. Allegro to PADS Mapping TableFrom Allegro Element: To PADS Element:Shield Trace (Protected)TracesTeardrops Not SupportedTest Coupon Not SupportedTest Points Test PointsThrough Padstacks Through PadstacksThrough Vias Through ViasThrough Vias (Protected)Through ViasTraces TracesTraces (Protected)TracesTraces in Cell Not supportedOtherComponent to Component Rules SupportedComponent Type Rules Not SupportedHighspeed Rules Not supportedHybird Objects Not SupportedMCM Objects Not SupportedNet Types Net ClassesPin Type, SLT Not SupportedRF Objects Not SupportedThermal Not SupportedVariants Not SupportedAllegro to PADS Layout Translation Notes Allegro to PADS Mapping TableChapter 3Error Codes and Log MessagesTable 3-1 is a list of error codes and translator log messages.Table 3-1. Error Codes and Log MessagesError code Explanation[F] A fatal error. The translator will terminate. A file was not created due to aproblem, setting, or switch that would not allow the file to be translated. Atranslated file is not created due to the fatal error that was encountered.[E] A serious, but non-fatal error. The translator will continue, but you must resolvethe problem, and the problem encountered might prevent the file from beinguseable by Expedition.[I]Current status information.[W] A warning.Error Codes and Log MessagesThird-Party InformationThis section provides information on open source and third-party software that may be included in the Allegro to PADS Translator product.•This software application may include BOOST version1.46.0third-party software.BOOST version1.46.0is distributed under the terms of the BOOST Software License version1.0and is distributed on an"AS IS"basis, WITHOUT WARRANTY OF ANY KIND,either express or implied.See the license for the specific language governingrights and limitations under the license.You can view a copy of the license at:<your_Mentor_Graphics_documentation_directory>/legal/boost_1.0.pdf.End-User License AgreementThe latest version of the End-User License Agreement is available on-line at:/eulaEND-USER LICENSE AGREEMENT (“Agreement”)This is a legal agreement concerning the use of Software (as defined in Section 2) and hardware (collectively “Products”)between the company acquiring the Products (“Customer”), and the Mentor Graphics entity that issued the corresponding quotation or, if no quotation was issued, the applicable local Mentor Graphics entity (“Mentor Graphics”). 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