(完整word版)AEC_Q101中文标准规范

AEC-Q100是美国汽车电子委员会针对车载应用集成电路产品的应力测试标准。

它主要测试芯片在各种应力环境下的可靠性和稳定性，包括预处理试验、偏压高加速应力试验、无偏压高加速应力试验、温度循环试验、高温贮存寿命试验、高温工作寿命试验、早期失效率试验、非易失性存储耐久试验、键合金球剪切试验、键合金球拉力试验、可焊性试验、物理尺寸试验、静电放电人体模型试验、静电放电充电装置模型试验、高温闩锁试验、电磁兼容试验、耐焊接热试验、锡须观察试验等19项内容。

組件技術委員會基于离散半导体元件应力测试认证的失效机理内容列表組件技術委員會AEC-Q101 基于离散半导体元件应力测试认证的失效机理附录1: 认证家族的定义附录2: Q101 设计、构架及认证的证明附录3: 认证计划附录4: 数据表示格式附录5: 最小参数测试要求附录6: 邦线测试的塑封开启附录7: AEC-Q101 与健壮性验证关系指南附件AEC-Q101-001: 人体模式静电放电测试AEC-Q101-002: 人体模式静电放电测试 (废止)AEC-Q101-003: 邦线切应力测试AEC-Q101-004: 同步性测试方法AEC-Q101-005: 静电放电试验–带电器件模型AEC-Q101-006: 12V 系统灵敏功率设备的短路可靠性描述感谢組件技術委員會任何涉及到复杂的技术文件都来自于各个方面的经验和技能。

为此汽车电子委员会由衷承认并感谢以下对该版文件有重大贡献的人：固定会员:Rick Forster Continental CorporationMark A. Kelly Delphi CorporationDrew Hoffman Gentex CorporationSteve Sibrel HarmanGary Fisher Johnson ControlsEric Honosowetz Lear Corporation技术成员:James Molyneaux Analog DevicesJoe Fazio Fairchild SemiconductorNick Lycoudes FreescaleWerner Kanert InfineonScott Daniels International RectifierMike Buzinski MicrochipBob Knoell NXP SemiconductorsZhongning Liang NXP SemiconductorsMark Gabrielle ON SemiconductorTom Siegel Renesas TechnologyTony Walsh Renesas TechnologyBassel Atallah STMicroelectronicsArthur Chiang VishayTed Krueger [Q101 Team Leader]Vishay其他支持者:John Schlais Continental CorporationJohn Timms Continental CorporationDennis L. Cerney International RectifierRene Rongen NXP SemiconductorsThomas Hough Renesas TechnologyThomas Stich Renesas Technology本文件是专门的纪念：Ted Krueger (1955-2013)Mark Gabrielle (1957-2013)注意事项組件技術委員會AEC 文件中的材料都是经过 AEC 技术委员会准备、评估和批准的。

aec-q101标准-回复什么是AEC-Q101标准？AEC-Q101是由全球汽车电子理事会（Automotive Electronics Council，简称AEC）制定的一项标准。

AEC成立于1994年，是由三大汽车制造商联合组建的非营利性组织，旨在制定汽车电子领域的技术标准和规范，以确保汽车电子产品的可靠性和一致性。

AEC-Q101作为AEC所制定的一项标准，旨在评估和验证电子元件在汽车环境下的可靠性。

为什么需要AEC-Q101标准？在汽车行业中，电子元件所面临的环境条件和工作要求与其他行业有很大的不同。

汽车电子元件需要在极端的温度、湿度、振动和电磁干扰等条件下正常工作，同时还必须保证在整个汽车使用寿命中的稳定性和可靠性。

因此，为了确保汽车电子产品的质量和可靠性，AEC-Q101标准应运而生。

AEC-Q101标准的内容和指导AEC-Q101标准主要包括了以下内容和指导：1. 环境和可靠性测试：AEC-Q101标准列出了一系列环境和可靠性测试的要求，包括温度循环、湿度试验、振动和冲击试验等。

这些测试旨在模拟汽车使用过程中的各种极端条件，以评估电子元件的耐久性和可靠性。

2. 电气特性测试：AEC-Q101标准还要求进行电气特性测试，包括与电压和电流相关的测试，以确保电子元件在汽车电气系统中能够正常工作并满足设计要求。

3. 元器件可靠性：AEC-Q101标准还对元器件可靠性提出了一系列要求。

这些要求涉及到元器件的失效率、失效模式和失效机制等方面，以确保元器件在汽车使用寿命内的可靠性。

4. 生产过程控制：AEC-Q101标准还要求制造商建立并执行一套完整的生产过程控制，并对生产过程中的各个环节进行监控和管理。

这样可以确保生产过程的一致性和可靠性，从而保证最终产品的质量。

AEC-Q101标准的应用和影响AEC-Q101标准广泛应用于汽车电子元件的设计、制造和测试过程中。

符合AEC-Q101标准的电子元件可以获得AEC-Q101认证，成为汽车行业中广泛使用的标准化元件。

aec-q101 环境试验判定标准本标准提供了AEC-Q101所规定的各项环境试验的判定准则。

这些试验包括温度和湿度、机械冲击、机械振动、重复测试、温度变化、湿度变化、耐腐蚀性、耐氧化性、耐电压性、耐沙尘性、耐气候性、耐烟雾性、耐振动性、耐老化性、耐久性测试以及其他特殊测试。

1.温度和湿度在环境试验过程中，样品应能在所规定的温度和湿度条件下正常工作，无明显的性能下降或功能丧失。

2.机械冲击在规定的冲击条件下，样品应能保持其结构和性能的稳定，无明显的损坏或功能丧失。

3.机械振动在规定的振动条件下，样品应能保持其结构的稳定性和功能的完整性，无明显的损坏或功能丧失。

4.重复测试在重复测试过程中，样品应能保持其性能的稳定性和结构的完整性，无明显的性能下降或功能丧失。

5.温度变化在所规定的温度变化条件下，样品应能保持其性能的稳定性和结构的完整性，无明显的性能下降或功能丧失。

6.湿度变化在所规定的湿度变化条件下，样品应能保持其性能的稳定性和结构的完整性，无明显的性能下降或功能丧失。

7.耐腐蚀性在所规定的腐蚀性环境下，样品应能保持其性能的稳定性和结构的完整性，无明显的腐蚀现象。

8.耐氧化性在所规定的氧化性环境下，样品应能保持其性能的稳定性和结构的完整性，无明显的氧化现象。

9.耐电压性在所规定的电压条件下，样品应能正常工作并保持其结构和性能的稳定性。

10.耐沙尘性在规定的沙尘条件下，样品应能保持其性能的稳定性和结构的完整性，无明显的沙尘侵入现象。

11.耐气候性在所规定的各种气候条件下，样品应能保持其性能的稳定性和结构的完整性，无明显的气候影响。

12.耐烟雾性在规定的烟雾条件下，样品应能保持其性能的稳定性和结构的完整性，无明显的烟雾侵入现象。

13.耐振动性在规定的振动条件下，样品应能保持其性能的稳定性和结构的完整性，无明显的振动影响。

14.耐老化性在所规定的老化条件下，样品应能保持其性能的稳定性和结构的完整性，无明显的老化现象。

aeq100标准
AEC-Q100标准是汽车电子行业中广泛使用的质量认证标准，它是由汽车电子市场协会（Automotive Electronics Council，简称AEC）制定的。

该标准主要是为了保障汽车电子零部件的质量和可靠性，确保它们能够在车辆的复杂环境下正常运行，减少可能产生的故障和事故。

AEC-Q100标准涵盖了电子元器件的多种类型，包括芯片、集成电路、传感器、开关等。

它主要考虑了这些元器件在汽车中的环境因素，如温度、湿度、振动、电磁干扰等，以及它们的可靠性、安全性、质量控制等方面的要求。

在AEC-Q100认证过程中，需要进行一系列的测试和验证，如耐久性测试、环境测试、可靠性测试等，以确保元器件满足标准中的要求。

只有通过了这些测试和验证，才能最终获得AEC-Q100认证，并被用于汽车电子领域。

aec-q101标准测试项目
AEC-Q101是汽车电子委员会（Automotive Electronics Council）制定的一套关于汽车电子元件可靠性的标准。

该标准旨在
确保汽车电子元件在极端环境下的可靠性和稳定性。

AEC-Q101标准
涵盖了多个测试项目，以评估电子元件在汽车应用中的性能。

下面
我将从多个角度介绍AEC-Q101标准的测试项目。

1. 温度周期测试，这个测试项目旨在评估电子元件在不同温度
条件下的性能。

它会暴露元件在高温和低温交替的环境下的稳定性，以验证其能否在汽车中长期可靠地工作。

2. 湿热循环测试，该测试项目用于模拟电子元件在潮湿和高温
环境下的工作情况。

这有助于评估元件在潮湿条件下的耐久性和稳
定性。

3. 压力循环测试，这个测试项目旨在模拟汽车电子元件在高海
拔和低海拔地区的工作环境。

通过在不同压力条件下进行测试，可
以评估元件在不同海拔下的可靠性。

4. 温度湿度偏倚测试，该测试项目结合了高温、高湿和电压偏
倚条件，以评估元件在这些极端环境下的稳定性和可靠性。

5. 机械冲击测试，这个测试项目用于评估元件在汽车行驶中受
到的机械冲击时的稳定性和耐久性。

总的来说，AEC-Q101标准的测试项目涵盖了温度、湿度、压力、机械冲击等多个方面，以确保汽车电子元件在极端环境下的可靠性
和稳定性。

这些测试项目有助于确保汽车中使用的电子元件能够经
受住各种极端条件下的考验，从而提高汽车的安全性和可靠性。

AEC-Q101环境试验判定标准一、概述AEC-Q101是汽车电子组件的可靠性标准，其中详细规定了汽车电子组件的环境试验要求和判定标准。

该标准旨在确保汽车电子组件能够在各种恶劣的环境条件下正常工作，提高汽车的安全性和可靠性。

本文将详细介绍AEC-Q101环境试验的判定标准。

二、环境试验要求AEC-Q101环境试验分为五个阶段：温度试验、湿度试验、振动试验、冲击试验和耐久性试验。

每个阶段都有具体的试验条件和要求，以确保汽车电子组件能够承受各种恶劣的环境条件。

1.温度试验温度试验旨在模拟汽车电子组件在不同温度下的性能表现。

试验过程中，样品需要承受从-40℃到125℃的温度变化，每个温度点保持至少2小时。

在每个温度点，都需要对样品进行功能测试，以确保其在不同温度下都能正常工作。

2.湿度试验湿度试验模拟汽车电子组件在不同湿度环境下的性能表现。

试验过程中，样品需要承受95%的相对湿度，并在高温（85℃）和高低温（45℃和-30℃）下进行测试。

在每个湿度条件下，都需要对样品进行功能测试，以确保其在不同湿度环境下都能正常工作。

3.振动试验振动试验模拟汽车在行驶过程中产生的振动对电子组件的影响。

试验过程中，样品需要承受频率范围在5Hz到500Hz的正弦波振动，每个振动条件至少持续1小时。

在每个振动条件下，都需要对样品进行功能测试，以确保其能够承受振动的影响。

4.冲击试验冲击试验模拟汽车在遇到突发情况时产生的冲击对电子组件的影响。

试验过程中，样品需要承受从-60g到+60g的冲击，每个冲击条件至少持续11ms。

在每个冲击条件下，都需要对样品进行功能测试，以确保其能够承受冲击的影响。

5.耐久性试验耐久性试验旨在模拟汽车电子组件在实际使用过程中的性能表现。

试验过程中，样品需要在高温（85℃）、高低温（-40℃到125℃）和湿度（95%）等条件下进行循环测试。

每个循环周期为24小时，共进行1000个循环周期。

在每个循环周期结束后，都需要对样品进行功能测试，以确保其能够承受长期使用的影响。

aec q标准
AEC-Q标准是一套车规元器件产品验证标准，由克莱斯勒、福特和通用汽
车为建立一套通用的零件资质及质量系统标准而设立的汽车电子委员会（AEC）制定。

AEC-Q标准包括多个子标准，如AEC-Q100（集成电路IC）、AEC-Q101（离散半导体元件，如二极管，三极管）、AEC-Q102（离散光电LED）、AEC-Q104（多芯片组件）和AEC-Q200（被动元器件）等。

AEC-Q标准是国际通用的车规元器件产品验证标准，通过AEC-Q认证意味着产品能够应用于汽车上。

供应商只有在通过元器件相应标准中规定的所有测试项目后，才能声称产品已通过AEC-Q认证。

完整的AEC-Q验证项目
数量众多，且周期较长，因此指定时间表是为了确保测试按计划进行。

此外，AEC-Q100的工作温度等级分4个等级（AEC_Q100_Rev_H规范），AEC-Q100要求器件能够承受2KV人体放电模式 (HBM)，在边角引脚上能承受750V的带电器件模式 (CDM)，而在所有其它引脚上则能承受500V
的电压。

以上内容仅供参考，如需了解更多信息，建议查阅AEC-Q标准相关文献或
咨询该标准业内人士。

AEC - Q101 - REV -May 15, 1996 Automotive Electronics CouncilComponent Technical CommitteeATTACHMENT 3AEC – Q101-003WIRE BOND SHEAR TESTAEC - Q101-003 - REV-AJuly 18, 2005 Automotive Electronics CouncilComponent Technical CommitteeMETHOD - 003DISCRETE COMPONENTWIRE BOND SHEAR TEST1. SCOPE:1.1 Description:This test establishes a procedure for determining the strength of the interface between a gold ball bond and a die bonding surface, or an aluminum wedge/stich bond and a die or package bonding surface, on either pre-encapsulation or post-encapsulation components. This strengthmeasurement is extremely important in determining two features:1) the integrity of the metallurgical bond which has been formed.2) the reliability of gold and aluminum wire bonds to die or package bonding surfaces.This test method can be used only when the ball height and diameter for ball bonds, or the wireheight (1.25 mil and larger at the compressed bond area) for wedge/stitch bonds, are largeenough and adjacent interfering structures are far enough away to allow suitable placement and clearance (e.g., above the bonding surface and between adjacent bonds) when performing thewire bond shear test.The wire bond shear test is destructive. It is appropriate for use in process development, process monitoring, and/or quality assurance.1.2 ReferenceDocuments:Not Applicable1.3 Terms and Definitions:The terms and definitions shall be in accordance with the following sections.1.3.1 BallBond:The welding of a thin wire, usually gold, to a die bonding surface, usually an aluminum alloy bond pad, using a thermal compression or thermosonic wire bonding process. The ball bond includes the enlarged spherical portion of the wire (sometimes referred to as the nail head and formed by the flame-off and first bonding operation in thermal compression and thermosonic process),theunderlying bonding surface, and the intermetallic weld interface. For the purposes of thisdocument, all references to ball bonds are applicable to gold ball bonds on die bonding surfaces;other ball bond material combinations may require a new set of failure criteria (see section 4.1).1.3.2 Bonding Surface:Either 1) the die surface (e.g., die bond pad) or 2) the package bonding surface (e.g., platedleadframe post or finger, downbond to the flag or paddle, etc.) to which the wire is ball, wedge, or stitch bonded.1.3.3 Bond Shear:A process in which an instrument uses a chisel shaped tool to shear or push a ball orwedge/stitch bond off the bonding surface (see Figure 1). The force required to cause thisseparation is recorded and is referred to as the bond shear strength. The bond shear strength of a gold ball bond, when correlated to the diameter of the ball bond, is an indicator of the quality of the metallurgical bond between the gold ball bond and the die bonding surface metallization. The bond shear strength of an aluminum wedge/stitch bond, when compared to the manufacturer’s bond wire tensile strength, is an indicator of the integrity of the weld between the aluminum wire and the die or package bonding surface.Shear ToolhSpecimen ClampTest SpecimenBonding Bond Weld AreaBondC LSurfaceFigure 1: Bond Shear Set-up1.3.4 Definition of Bond Shear Types for Ball and Wedge/Stitch Bonds (see Figure 3):1.3.4.1 Type 1 - Bond Lift:A separation of the entire wire bond from the bonding surface with only an imprint being left on the bonding surface. There is very little evidence of intermetallic formation or welding to the bonding surface metallization.1.3.4.2 Type 2 - Bond Shear:A separation of the wire bond where: 1) A thin layer of bonding surface metallization remains with the wire bond and an impression is left in the bonding surface, or 2) Intermetallics remain on the bonding surface and with the wire bond, or 3) A major portion of the wire bond remains on the bonding surface.1.3.4.3 Type 3 - Cratering:A condition under the bonding surface metallization in which the insulating layer (oxide orinterlayer dielectric) and the bulk material (silicon) separate or chip out. Separation interfaceswhich show pits or depressions in the insulating layer (not extending into the bulk) are notconsidered craters. It should be noted that cratering can be caused by several factors includingthe wire bonding operation, the post-bonding processing, and even the act of wire bond sheartesting itself. Cratering present prior to the shear test operation is unacceptable.1.3.4.4 Type 4 - Die Surface Contact:The shear tool contacts the die surface and produces an invalid shear value. This condition maybe due to improper placement of the specimen, a die surface not parallel to the shearing plane, alow shear height, or instrument malfunction. This bond shear type is not acceptable and shall beeliminated from the shear data.1.3.4.5 Type 5 - Shearing Skip:The shear tool removes only the topmost portion of the ball or wedge/stich bond. This condition may be due to improper placement of the specimen, a die surface not parallel to the shearing plane, ahigh shear height, or instrument malfunction. This bond shear type is not acceptable and shall beeliminated from the shear data.1.3.4.6 Type 6 - Bonding Surface Lift:A separation between the bonding surface metallization and the underlying substrate or bulkmaterial. There is evidence of bonding surface metallization remaining attached to the ball orwedge/stich bond.1.3.5 Footprint:An impression of the compressed wedge/stitch bond area created in the bonding surface during the ultrasonic wire bonding process. The bond footprint area is normally larger than the actualmetallurgical weld interface.1.3.6 Shear Tool or Arm:A tungsten carbide, or equivalent, chisel with specific angles on the bottom and back of the toolto insure a shearing action.Bond:1.3.7 Wedge/StitchThe welding of a thin wire, usually aluminum, to a die or package bonding surface using anultrasonic wire bonding process. The wedge bond, sometimes referred to as a stitch bond,includes the compressed (ultrasonically bonded) area of the bond wire and the underlyingbonding surface. When wedge/stitch bonding to an aluminum alloy bonding surface, nointermetallic exists because the two materials are of the same composition; but rather the twomaterials are combined and recrystallized by the ultrasonic energy of the welding process. Forthe purposes of this document, all references to wedge/stich bonds are applicable to aluminumwedge/stich bonds only; gold wedge/stich bonds are not required to be wire bond shear tested.2. APPARATUS AND MATERIAL:The apparatus and materials required for wire bond shear testing shall be as follows:Equipment:2.1 InspectionAn optical microscope system or scanning electron microscope providing a minimum of 70Xmagnification.Equipment:2.2 MeasurementAn optical microscope or measurement system capable of measuring the wire bond diameter to within ± 0.1 mil.2.3 Workholder:Fixture used to hold the component being tested parallel to the shearing plane and perpendicular to the shear tool. The fixture shall also eliminate component movement during wire bond shear testing. If using a caliper controlled workholder, place the holder so that the shear motion isagainst the positive stop of the caliper. This is to insure that the recoil movement of the caliper controlled workholder does not influence the wire bond shear test.2.4 Wire Bond Shear Equipment:The wire bond shear equipment must be capable of precision placement of the shear toolapproximately 0.1 mil above the topmost part of the bonding surface. This distance (h) shallinsure the shear tool does not contact the die or package bonding surface and shall be less than the distance from the topmost part of the bonding surface to the center line (C L) of the ball orwedge/stich bond.2.5 Bond Shear Tool:Required shear tool parameters include but are not limited to: flat shear face, sharp shearingedge, and shearing width of 1.5 to 2 times (1.5X to 2X) the bond diameter or bond length. Theshear tool should be designed so as to prevent plowing and drag during wire bond shear testing.The shear tool should be clean and free of chips (or other defects) that may interfere with thewire bond shear test.3. PROCEDURE:3.1 Calibration:Before performing the wire bond shear test, it must be determined that the equipment has been calibrated in accordance with the manufacturer's specifications and is presently in calibration.Recalibration is required if the equipment is moved to another location.3.2 Visual Examination of Wire Bonds to be Shear Tested After Decapsulation:Before performing wire bond shear testing on a component which has been opened using wetchemical and/or dry etch techniques, the bonding surfaces shall be examined to insure there isno absence of metallization on the bonding surface area due to chemical etching and wire bonds are attached to the bonding surface. Ball or wedge/stitch bonds on bonding surfaces withevidence of degradation from chemical attack or absence of metallization shall not be used forwire bond shear testing. Wire bonds on bonding surfaces without degradation from chemicalattack may not be attached to the bonding surface due to other causes (e.g., package stress).These wire bonds are considered valid and shall be included in the shear data as a zero (0) gram value. Wire bonds must also be examined to ensure adjacent interfering structures are farenough away to allow suitable placement and clearance (above the bonding surface andbetween adjacent wire bonds) when performing the wire bond shear test.Sizes:3.3 SampleThe sample size shall be as specified in Table 1 of CDF-AEC-Q101.3.4 Measurement of the Ball Bond Diameter to Determine the Ball Bond Failure Criteria:Once the bonding surfaces have been examined and prior to performing wire bond shear testing, the diameter of all ball bonds (from at least one representative sample to be tested) shall bemeasured and recorded. For asymmetrical ball bonds, determine the average using both thelargest (d large) and the smallest diameter (d small) values (see Figure 2). These ball bonddiameter measurements shall be used to determine the mean, or average, diameter value. The resulting mean, or average, ball bond diameter shall then be used to establish the failure criteria as defined in section 4.1. If process-monitor data has established the nominal ball bonddiameter, then that value may be used to determine the failure criteria as defined in section 4.1.SYMMETRICAL ASYMMETRICALFigure 2: Ball Bond Diameter Measurement (symmetrical vs. asymmetrical)3.5 Wire Bond Shear Test Procedure:The wire bond shear testing procedure shall be performed as follows:a. The wire bond shear equipment shall pass all self diagnostic tests prior to performing thewire bond shear test.b. The wire bond shear equipment and test area shall be free of excessive vibration ormovement. Examine the shear tool to verify it is in good condition and is not bent ordamaged. Check the shear tool to verify it is in the up position.c. Adjust the workholder to match the component being tested. Secure the component tothe workholder. Make sure the die or package bonding surface is parallel to the shearingplane of the shear tool. It is important that the shear tool does not contact the bondingsurface or adjacent structures during the shearing operation as this will give incorrect highreadings.d. Position the component so that the wire bond to be tested is located adjacent to theshear tool. Lower the shear tool (or raise the component depending upon wire bondshear equipment used) to approximately the die or package bonding surface but notcontacting the surface (approximately the thickness of the wire bond above the die orpackage bonding surface).e. For ball bond shear testing, position the ball bond to be tested so that the shear motionwill travel perpendicular to the die edge. Wire bond shear testing is required for ballbonds located at the die bonding surface interface only.f. For aluminum wedge/stitch bond shear testing, a wire height at the compressed bondarea of 1.25 mils and larger is required. For wires too small for wire bond shear testing(less than 1.25 mils in height at the compressed bond area), only a footprint inspection isrequired (see section 3.7). Position the wedge/stitch bond to be tested so that the shearmotion will travel toward the long side of the wedge/stitch bond and is free of anyinterference (i.e. shear the outside wedge/stitch bond first and then shear toward thepreviously sheared wedge/stitch bond). Wire bond shear testing is required for aluminumwedge/stitch bonds located at die and package bonding surfaces; gold wedge/stichbonds are not required to be wire bond shear tested.g. Position the shear tool a distance of approximately one ball bond diameter (or onealuminum wire diameter for wedge/stitch bonds) from the wire bond to be shear testedand shear the wire bond.3.6 Examination of Sheared Wire Bonds:All wire bonds shall be sheared in a planned/defined sequence so that later visual examinationcan determine which shear values should be eliminated due to an improper shear. The wirebonds shall be examined using at least 70X magnification to determine if the shear tool skippedover the wire bond (type 5) or the shear tool scraped or plowed into the die surface (type 4). See Figure 3 for bond shear types and illustrations.Readings in which either a bond shear type 4 or 5 defective shear condition occurred shall beeliminated from the shear data. Bond shear type 1, 2, 3, and 6 shall be considered acceptableand included in the shear data.Sheared wire bonds in which a bond shear type 3 cratering condition has occurred shall beinvestigated further to determine whether the cracking and/or cratering is due to the wire bonding process or the act of wire bond shear testing. Cratering caused prior to the wire bond shear test operation is unacceptable. Cratering resulting from the act of wire bond shear testing shall beconsidered acceptable and included in the shear data.3.7 Footprint Inspection of Aluminum Wedge/Stitch Bonds:a. All aluminum wire bonding processes to both die and package bonding surfaces shallhave a bond footprint inspection performed.b. For wires too small for wire bond shear testing (less than 1.25 mils in height at thecompressed bond area), the wires shall be removed at the wedge/stitch bond locationusing a small sharp blade to peel or pluck the wire bond from the bonding surface. Theremoval of the aluminum wire shall be sufficient such that the wire bond interface can bevisually inspected and the metallurgical wire bond area determined.c. For larger wires (greater than 1.25 mils in height at the compressed bond area), the wiresshall be inspected after wire bond shear testing to examine the failure mode and todetermine the wedge/stitch bond footprint coverage.3.8 Bond Shear Data:Data shall be maintained for each wire bond sheared. The data shall identify the wire bond(location, ball bond and/or wire diameter, wire material, method of bonding, and material bonded to), the shear strength, and the bond shear type (as defined in section 1.3.4 and Figure 3).CRITERIA:4. FAILUREThe following failure criteria are not valid for components that have undergone environmentalstress testing or have been desoldered from circuit boards.4.1 Failure Criteria for Gold Ball Bonds:The gold ball bonds on a component shall be considered acceptable if the minimum individualand sample average ball bond shear values are greater than or equal to the values specified inFigure 4 and Table 1. This criteria is applicable for gold wire ball bonds on aluminum alloybonding surfaces. Other material combinations may require a new set of failure criteria.Alternate minimum ball bond shear values may be proposed by the supplier if supporting datajustifies the proposed minimum values.4.2 Failure Criteria for Wedge/Stitch Bonds:The aluminum wedge/stitch bonds on a component shall be considered acceptable if theminimum shear values are greater than or equal to the manufacturer’s bond wire tensile strength.In addition, the percent of the wedge/stitch bond footprint in which bonding occurs shall begreater than or equal to 50%. If it is necessary to control the wire bonding process using SPC for percent coverage, a C pk value can be calculated to this limit.Figure 3: Wire Bond Shear Types ** (Shear types are illustrated using ball bonds; these types also apply to wedge/stitch bonds)MINIMUM SHEAR VALUESBALL BOND DIAMETER (mils)2.252.53.03.253.53.754.254.54.755.05.252.0S H E A R S T R E N G T H (g r a m s )1.750102030405060708090100110 2.754.0Figure 4: Minimum Acceptable Individual and Sample Average Ball Bond Shear Values *, seeTable 1 for exact ball bond shear values ** (Shear values are applicable for gold wire ball bonds on aluminum alloy bonding surfaces)Table 1: Minimum Acceptable Individual and Sample Average Ball Bond Shear Values * * (Shear values are applicable for gold wire ball bonds on aluminum alloy bonding surfaces)Ball Bond Diameter(mils)MinimumSample Average(grams)Minimum IndividualShear Reading(grams)2.012.6 5.72.1 14.0 6.8 2.2 15.5 8.1 2.3 17.1 9.5 2.4 18.8 10.9 2.5 20.6 12.4 2.6 22.4 14.0 2.7 24.4 15.6 2.8 26.5 17.42.9 28.6 19.23.0 30.8 21.1 3.1 33.2 23.1 3.2 35.6 25.1 3.3 38.1 27.2 3.4 40.7 29.4 3.5 43.4 31.7 3.6 46.2 34.1 3.7 49.1 36.5 3.8 52.1 39.13.9 55.2 41.74.0 58.3 44.3 4.1 61.6 47.1 4.2 65.0 50.0 4.3 68.4 52.9 4.4 71.9 55.8 4.5 75.6 59.0 4.6 79.3 62.1 4.7 83.1 65.3 4.8 87.0 68.64.9 91.0 72.05.0 95.1 75.5Revision HistoryRev #-A Date of changeMay 15, 1996July 18, 2005Brief summary listing affected sectionsInitial Release.Added new Section 1.3.5. Revised the following: Sections 1.1, 1.3.1,1.3.4.1, 1.3.4.4, 1.3.4.5,2.2, 2.5,3.2, 3.5, 3.6 (b); Figure 3.。

aec-q101标准AEC-Q101是由国际汽车电子理事会（International Automotive Electronics Council，简称IAEC）发布的一个标准，它规定了用于汽车电子元件的可靠性测试方法和要求。

这个标准旨在确保汽车电子元件在极端环境和条件下的稳定性和可靠性，以满足汽车行业对于高质量和高可靠性的需求。

以下是对AEC-Q101标准的简要介绍：1. AEC-Q101标准的背景汽车电子元件需要在各种恶劣环境中工作，包括高温、低温、湿度、振动、电磁干扰等条件。

为了确保这些元件在汽车中的可靠性和稳定性，汽车制造商和供应商之间需要共同的标准和测试方法。

AEC-Q101标准就是为了满足这一需求而制定的。

2. AEC-Q101标准的内容AEC-Q101标准主要涉及到以下方面：2.1 温度试验AEC-Q101要求在不同的温度范围内进行测试，包括高温（通常超过100摄氏度）和低温（通常低于-40摄氏度）条件下的测试。

这有助于评估元件在极端温度条件下的性能和可靠性。

2.2 湿度试验湿度试验是通过将元件置于高湿度环境中，通常与高温结合，以模拟潮湿条件下的性能。

这有助于验证元件在湿润环境中的稳定性。

2.3 振动和冲击试验AEC-Q101标准要求进行振动和冲击测试，以模拟车辆在行驶中所受到的振动和冲击。

这有助于评估元件在车辆运动和不平路面等条件下的可靠性。

2.4 电磁干扰测试标准中还包括对元件的电磁干扰测试，以确保元件不会受到来自其他汽车电子设备的干扰，也不会对其他设备造成干扰。

2.5 其他测试要求AEC-Q101标准还包括一系列其他测试要求，例如对焊接可靠性、封装材料的性能等方面的测试。

3. 适用范围AEC-Q101标准适用于各种汽车电子元件，包括但不限于集成电路、传感器、电容器、电感、二极管等。

这个标准的广泛应用有助于确保汽车电子系统的整体可靠性和性能。

4.AEC-Q101标准在汽车电子领域起到了至关重要的作用，它为汽车制造商和供应商提供了共同的测试方法和标准，以确保汽车电子元件在各种极端条件下都能够稳定可靠地工作。

AEC-Q101 是汽车电子元件质量标准，主要用于规范汽车电子零部件的设计、开发、生产、测试和质量保证。

以下是AEC-Q101 标准的主要总结：
1. 适用范围：AEC-Q101 标准适用于汽车电子设备、组件和系统，包括处理器、存储器、传感器、执行器等。

2. 设计要求：AEC-Q101 标准要求汽车电子零部件设计时应考虑功能安全、可靠性、耐久性、热性能、电磁兼容性等因素。

3. 开发流程：标准要求采用成熟的开发流程，确保零部件的开发质量。

包括需求分析、设计、验证、生产准备和质量保证等阶段。

4. 生产工艺：AEC-Q101 标准对生产工艺提出了严格的要求，包括生产设备、原材料、工艺流程、检验和测试等环节。

5. 质量保证：标准要求建立完善的质量保证体系，包括生产过程控制、失效分析、客户反馈处理等环节。

6. 环境适应性：AEC-Q101 标准对汽车电子零部件在高温、低温、湿热、振动、冲击等环境条件下的适应性提出了要求。

7. 可靠性和耐久性：标准要求零部件在规定的工况下具有足够的可靠性和耐久性，确保汽车安全性和稳定性。

8. 功能安全：AEC-Q101 标准要求汽车电子零部件在开发和生产过程中充分考虑功能安全，降低潜在的安全风险。

9. 电磁兼容性：标准要求汽车电子零部件具有较好的电磁兼容性，避免电磁干扰对其他电子设备的影响。

10. 后期服务：AEC-Q101 标准鼓励企业提供完善的售后服务，包括故障处理、零部件更换和升级等。

车规级AEC-Q101认证规范汽车电⼦对元件的外部⼯作环境，如温度、湿度、发霉、粉尘、⽔、EMC以及有害⽓体侵蚀等的要求，根据不同的安装位置等有不同的需求，但⼀般都⾼于消费电⼦产品。

车规级元器件认证，是指我们如果需要打造⼀个满⾜车载等级要求的元器件，那么就必须要经历过的⼀系列认证，⽽AEC-Q 系列标准就是⾏业公认的车规元器件认证标准。

这⾥的AEC（Automotive Electronics Council）也就是汽车电⼦委员会。

这是⼀个由通⽤、福特和克莱斯勒为建⽴⼀套通⽤的零件资质及质量系统标准⽽设⽴的组织。

⽽Q则是Qualification的⾸字母。

半导体产业链可以分为上游⽀撑、中游制造和下游应⽤，其中上游⽀撑主要包含半导体材料、半导体⽣产设备、EDA 和 IP 核；中游制造包括芯⽚设计、晶圆制造和封装测试三⼤环节；下游应⽤覆盖汽车、⼯业控制、消费电⼦等领域。

2021年11⽉1⽇，国家新能源汽车技术创新中⼼提出，并主责起草的《车规级半导体功率器件测试认证规范》、《车规级半导体功率模块测试认证规范》和《车规级智能功率模块（IPM）测试认证规范》三项团体标准正式⾯向产业发布。

三项标准参照AECQ101、AQG324以及国军标等标准，按照汽车⾏业OEM和Tire1的要求，基于BJEV的路谱，综合考虑第三代半导体的特点和应⽤要求，规定了车规级Si基和SiC基功率半导体（器件、模块和组件）鉴定检验和质量⼀致性检验的抽样⽅案，以及试验和测试要求，形成了适⽤于国内车规级功率半导体的产品测试认证规范。

该规范为车规级功率半导体的测试认证、供货体系流程提供依据，充分指导⾃主车规级功率半导体技术的快速进步。

AEC-Q101是基于失效机制的分⽴半导体应⼒测试认证规范。

半导体分⽴器件被⼴泛应⽤到消费电⼦、计算机及外设、⽹络通信，汽车电⼦、led显⽰屏等领域，⽽汽车领域是全球半导体分⽴器件最⼤的应⽤市场。

随着汽车电⼦朝向智能化、信息化、⽹络化⽅向发展,新能源汽车的产销爆发性增长，半导体分⽴器件在汽车电⼦产品中的应⽤呈现出更加⼴阔的发展空间。

基于离散半导体元件应力测试认证的失效机理内容列表AEC-Q101 基于离散半导体元件应力测试认证的失效机理附录1: 认证家族的定义附录2: Q101 设计、构架及认证的证明附录3: 认证计划附录4: 数据表示格式附录5: 最小参数测试要求附录6: 邦线测试的塑封开启附录7: AEC-Q101与健壮性验证关系指南附件AEC-Q101-001: 人体模式静电放电测试AEC-Q101-002: 人体模式静电放电测试 (废止)AEC-Q101-003: 邦线切应力测试AEC-Q101-004: 同步性测试方法AEC-Q101-005: 静电放电试验–带电器件模型AEC-Q101-006: 12V系统灵敏功率设备的短路可靠性描述感谢任何涉及到复杂的技术文件都来自于各个方面的经验和技能。

为此汽车电子委员会由衷承认并感谢以下对该版文件有重大贡献的人：固定会员:Rick Forster Continental CorporationMark A. Kelly Delphi CorporationDrew Hoffman Gentex CorporationSteve Sibrel HarmanGary Fisher Johnson ControlsEric Honosowetz Lear Corporation技术成员:James Molyneaux Analog DevicesJoe Fazio Fairchild SemiconductorNick Lycoudes FreescaleWerner Kanert InfineonScott Daniels International Rectifier Mike Buzinski MicrochipBob Knoell NXP Semiconductors Zhongning Liang NXP SemiconductorsMark Gabrielle ON SemiconductorTom Siegel Renesas TechnologyTony Walsh Renesas TechnologyBassel Atallah STMicroelectronicsArthur Chiang VishayTed Krueger [Q101 Team Leader]Vishay其他支持者:John Schlais Continental Corporation John Timms Continental Corporation Dennis L. Cerney International Rectifier Rene Rongen NXP SemiconductorsThomas Hough Renesas TechnologyThomas Stich Renesas Technology本文件是专门的纪念：Ted Krueger (1955-2013)Mark Gabrielle (1957-2013)注意事项AEC文件中的材料都是经过AEC技术委员会准备、评估和批准的。

AEC - Q101 - REV -June 29, 2005 Automotive Electronics CouncilComponent Technical CommitteeATTACHMENT 5AEC – Q101-005CAPACITIVE DISCHARGE MODEL (CDM)ELECTROSTATIC DISCHARGE (ESD)TESTAEC - Q101-005 - REV-July 18, 2005 Automotive Electronics CouncilComponent Technical CommitteeMETHOD - 005DISCRETE COMPONENTCHARGED DEVICE MODEL (CDM)ELECTROSTATIC DISCHARGE (ESD) TEST1. SCOPE1.1 Description:The purpose of this specification is to establish a reliable and repeatable procedure fordetermining the CDM ESD sensitivity for electronic components. This test method does notinclude socketed CDM.1.2 Reference Documents:ESD Association Specification STM5.3.1JEDEC Specification EIA/JESD22-C1011.3 Terms and Definitions:The terms used in this specification are defined as follows.1.3.1 Charged Device Model (CDM) ESD:An ESD pulse meeting the waveform criteria specified in this test method, approximating anESD event that occurs when a component becomes charged (e.g., triboelectric) anddischarges to a conductive object or surface.1.3.2 Component Failure:A condition in which a component does not meet all the requirements of the acceptancecriteria, as specified in section 5, following the ESD test.1.3.3 Device Under Test (DUT):An electronic component being evaluated for its sensitivity to ESD.1.3.4 Electrostatic Discharge (ESD):The transfer of electrostatic charge between bodies at different electrostatic potentials.1.3.5 Electrostatic Discharge Sensitivity:An ESD voltage level resulting in component failure.1.3.6 ESD Simulator:An instrument that simulates the charged device model ESD pulse as defined in thisspecification.Copyright © 2005 by Siemens VDO, Delphi Electronics & Safety, and Visteon Corporation. This document may be freely reprinted with this copyright notice. This document cannot be changed without approval by AEC Component Technical Committee.1.3.7 Pin Under Test (PUT):The pin and/or terminal under test; this includes all component pins as well as all power supplyand ground pins.1.3.8 Withstanding Voltage:The ESD voltage level at which, and below, the component is determined to pass the failurecriteria requirements specified in section 4.2. EQUIPMENT:2.1 Test Apparatus:The apparatus for this test consists of an ESD pulse simulator; Figure 1 shows a typicalequivalent CDM ESD circuit. Other equivalent circuits may be used, but the actual simulatormust be capable of supplying pulses that meet the waveform requirements of Table 2, Table 3, and Figure 3.(a) Direct charge CDM (b) Field induced charge CDM Note: Parasitics in the charge and discharge path of the test equipment can greatly affect test results Figure 1: Charged Device Model ESD Typical Equivalent Circuit for (a) Direct Charge and (b) Field Induced Charge2.2 Measurement Equipment:Equipment shall include an oscilloscope/digitizer, current probe, attenuators, andcable/connector assemblies to verify conformance of the simulator output pulse to therequirements of this document as specified in Table 2, Table 3, and Figure 3.2.2.1 Oscilloscope/Digitizer:The oscilloscope/digitizer shall have a minimum bandwidth of 1.0GHz and nominal inputimpedance of 50Ω (Tektronix SCD1000, HP 7104, or equivalent).2.2.2 Current Probe:The current probe shall be an inductive current transducer or coaxial resistive probe with aminimum bandwidth of 5GHz.2.2.3 Attenuator:The attentuator, if required, shall be high precision (+0.1dB precision at 1.0GHz) with impedance of 50Ω.2.2.4 Cable/Connector Assembly:The cable/connector assembly, if required, shall be low loss (less than 0.4dB loss up to 1GHz) with impedance of 50Ω.2.2.5 Verification Modules:The two verification modules shall be gold-plated or nickel-plated etched copper disks on singlesided FR-4 material (thickness = 0.8mm). The disks shall be: 1) a small disk (diameterapproximately = 9 mm) configuration with a capacitance value of 4pF ±5% measured at 1MHz,and 2) a large disk (diameter approximately = 26mm) configuration with a capacitance of 30pF ±5% measured at 1MHz. Each disk shall be created using an etching process and centered on FR-4 material measuring at least 30mm by 30mm. Capacitance shall be measured with the non-metallized and non-disk side of the verification module in direct contact with the metal surface ofa ground plane. Verification module parameters and illustrations are shown in Table 1 andFigure 2.Table 1: Verification Module ParametersVerification Module Parameter Accepted ValueCapacitance 3.8pF to 4.2pFDisk diameter ~ 9mm4pFFR-4 material size ≥ 30mm by 30mmFR-4 thickness 0.8mmCapacitance 28.5pF to 31.5pFDisk diameter ~ 26mm30pFFR-4 material size ≥ 30mm by 30mmFR-4 thickness 0.8mm(Top View) (Top View)etched copper disk(Side View) (Side View)(a) 4pF verification module (~ 9mm disk) (b) 30pF verification module (~ 26mm disk)Figure 2: Verification Module Illustrations, (a) 4pF and (b) 30pF2.2.6 Capacitance Meter:The capacitance meter shall have a resolution of 0.2pF when measured at 1.0MHz with 3%accuracy.2.3 Equipment Calibration and Qualification:All peripheral equipment (including but not limited to the oscilloscope/digitizer, current probe,attenuators, cable/connector assemblies, verification modules, and capacitance meter) shall be periodically calibrated according to manufacturer’s recommendations. A period of one (1) year is the maximum permissible time between full calibration tests. Qualification of the CDM simulator must be performed during initial acceptance testing or after repairs that are made to theequipment that may affect the waveform. The simulator must meet the requirements of Table 2 and Figure 3 for five (5) consecutive waveforms at all voltage levels using the 4pF verificationmodule shown in Figure 2. Simulators not capable of producing the maximum voltage levelshown in Table 2 shall be qualified to the highest voltage level possible. The simulator must also meet the requirements of Table 3 and Figure 3 for five (5) consecutive waveforms at the 500 volt level using the 30pF verification module shown in Figure 2. Thereafter, the test equipment shall be periodically qualified as described above; a period of one (1) year is the maximum permissible time between full qualification tests.2.4 Verification Module Calibration:The capacitance value of verification modules can be dramatically degraded by excessive use (indentations due to repetitive pogo pin contact, cracks in metallization, warping, etc.).Therefore, to ensure proper capacitance values, it is recommended that module capacitancebe verified per section 2.4.1. When modules are degraded to the point they no longer meet the specified capacitance requirements shown in Table 1, they must be replaced.2.4.1 Verification Module Capacitance Measurement Procedure:a. Using the 4pF verification module, place the non-metallic side of the module in directcontact with the metallic surface of a ground plane. Capacitance measurements can beaffected by air gaps between the module and the ground plane (e.g., due to warping ofthe FR-4 material, etc.). Therefore, the air space between the module and the groundplane must be minimized. This can be accomplished by applying slight pressure usingthe capacitance meter probes; care must be taken to avoid damaging the diskmetallization.b. Using the capacitance meter defined in section 2.2.6, measure the capacitance of theverification module to the ground plane. The capacitance value shall meet therequirements defined in Table 1.c. Repeat steps (a) and (b) using the 30pF verification module.2.5 Simulator Waveform Verification:The performance of the simulator can be dramatically degraded by parasitics in the dischargepath. Therefore, to ensure proper simulation and repeatable ESD results, it is recommendedthat waveform performance be verified using the 4pF verification module. The waveformverification shall be performed prior to performing CDM testing. If at any time the waveforms do not meet the requirements of Table 2 and Figure 3 at the 500 volt level, the testing shall behalted until waveforms are in compliance.2.5.1 Waveform Verification Procedure:a. Prior to performing waveform verification, verification modules and tester components(e.g., pogo pin, charge plate, etc.) must be cleaned with isoproponal (isopropyl alcohol)using a procedure approved by the user’s internal safety organization. Once clean,avoid direct skin contact. If handling is required, the use of vacuum tweezers orpersonnel finger cots is strongly recommended.b. Place the 4pF verification module in direct contact with the charge plate of the CDMsimulator. If a dielectric film is used during component testing, it shall be less than 130microns thick and must be in place during the waveform verification procedure.c. Set the horizontal time scale of the oscilloscope at 0.5 nanoseconds per division orless.d. Raise the charge plate potential to positive 500 volts. With the discharge pin centeredwithin the 4pF metallic disk, bring the discharge pin in direct contact with theverification module and initiate a discharge.e. Measure and record the rise time, first peak current, second peak current, third peakcurrent, and full width at half height. All parameters must meet the limits specified inTable 2 and Figure 3.f. Raise the charge plate potential to negative 500 volts. With the discharge pin centeredwithin the 4pF metallic disk, bring the discharge pin in direct contact with theverification module and initiate a discharge.g. Measure and record the rise time, first peak current, second peak current, third peakcurrent, and full width at half height. All parameters must meet the limits specified inTable 2 and Figure 3.Table 2: CDM Waveform Specification for 4pF Verification ModuleVoltage Level (V) 1st peakcurrentfor 4pFI p1(A)(±20%)2nd peakcurrentfor 4pFI p2(A)3rd peakcurrentfor 4pFI p3(A)RiseTimet r(ps)Full width at half heightfor 4pFFWHH(ps)250 2.25 < 50% ofI p1 < 25% ofI p1< 400 < 600500 4.50 < 50% ofI p1 < 25% ofI p1< 400 < 6001000 9.00 < 50% ofI p1 < 25% ofI p1< 400 < 6002000 18.00 < 50% ofI p1 < 25% ofI p1< 400 < 600Table 3: CDM Waveform Specification for 30pF Verification ModuleVoltage Level (V)1st peakcurrentfor 30pF *I p1 (A)(±20%)2nd peakcurrentfor 30pF *I p2(A)3rd peakcurrentfor 30pF *I p3(A)RiseTimeT rfor 30pF *(ps)Full width at half heightfor 30pF *FWHH(ps)500 14.00 < 50% of I p1 < 25% of I p1 < 400 < 1000* The 30pF verification module is used only during Equipment Qualification as specified in section 2.3.90%10%50%C u r r e n t i n A m p e r e sTime in nanoseconds0.5 1.0 1.5 2.00.0Figure 3: Typical CDM Current Waveform3. PROCEDURE: 3.1 Sample Size:Each sample group shall be composed of ten (10) components per stress voltage level. Each sample group shall have all component pins and/or terminals (including power and ground pins) stressed at one (1) voltage level, following the test flow diagram of Figure 4. Each stress voltage level requires a new sample group of ten (10) components.3.2 Charging and Discharging Methods:There are two acceptable methods of charging a DUT: Direct Charging and Field-induced Charging. Either method may be used to perform CDM ESD testing and must be recorded. While several methods exist for discharging a DUT, the direct contact discharge method is the only acceptable method to discharge a DUT for this test method.3.2.1 Direct Charging Method:The DUT is placed “dead-bug” (upside down with pins and/or terminals pointing up) withcomponent body in direct contact with the charge plate and charged either through the pin(s) providing the best ohmic connection to the substrate of the DUT or through all DUT pinssimultaneously (see Figure 1). To prevent damaging the DUT, ensure both the component and charging mechanism are at ground potential prior to initiating the CDM test. Contact to thecharging pin(s) must be made prior to raising the charge potential. Once the DUT is charged, a pin under test (PUT) is discharged (except any pin(s) directly connected to the substrate of theDUT). It is permissible to leave the charging probe in direct contact with the charging pin during the discharge event provided the discharge waveform meets the requirements of Table 2, Table 3, and Figure 3. After discharging the PUT, the DUT shall be re-charged and the process isrepeated for each pin to be tested. All charge pins must be recorded.3.2.2 Field-induced Charging Method:The DUT is placed “dead-bug” (upside down with pins and/or terminals pointing up) withcomponent body in direct contact with the field charging plate and charged by raising the potential of the charge plate (see Figure 1). To prevent damaging the DUT, ensure both the componentand charge plate are at ground potential prior to initiating the CDM test. Once the DUT ischarged, a pin under test (PUT) is discharged. After discharging the PUT, the DUT shall be re-charged and the process is repeated for each pin to be tested. The field charging plate shall be at least seven times (7X) larger in area than the DUT and shall meet the requirements of Table 2,Table 3, and Figure 3. If a dielectric film is used during component testing, it shall be less than130 microns thick and must be in place during the waveform verification procedure.3.2.3 Charging Small Components:Small component packages may not be able to hold enough charge to meet the specifieddischarge voltage levels. For these packages, perform the test once and, if there is insufficientcharge, the supplier must instead perform both HBM and MM ESD testing. The supplier shalldocument that the package could not hold sufficient charge to perform the CDM ESD test.3.2.4 Direct Discharging Method:Direct contact discharge is initiated within a relay and can add parasitics to the discharge path(care must be taken to minimize these parasitics). A discharge probe (e.g., pogo pin),connected to the relay, is placed in direct contact with the PUT and produces a very repeatableCDM event.3.3 Test Temperature:Each component shall be subjected to ESD pulses at room temperature.3.4 Measurements:Prior to ESD testing, complete parametric testing (initial electrical verification) shall beperformed on all sample groups and all components in each sample group per applicable userdevice specification at room temperature followed by hot temperature, unless specifiedotherwise in the user device specification. A data log of each component shall be made listingall parameter measurements as defined in Table 4. The data log will be compared to theparameters measured during final electrical verification testing to determine the failure criteriaof section 4.3.5 Cleaning Method:To avoid charge loss during CDM testing, components should be cleaned with isopropanol(isopropyl alcohol) using a procedure approved by the local safety organization. Componentsshould then be handled only by vacuum tweezers, personnel wearing finger cots or equivalent, or plastic tweezers which have been neutralized by holding in an ionized air stream. The CDM tester should be cleaned periodically with isopropanol (isopropyl alcohol) to remove any surfacecontamination that could result in charge loss. Particular attention should be paid to the discharge probe, charging probe, and the charge plate on which the component is placed.3.6 Detailed Procedure:The ESD testing procedure shall be per the test flow diagram of Figure 4 and as follows:a. Place clean DUT “dead-bug” (upside down with pins and/or terminals pointing up) withcomponent body in direct contact with the charge plate.b. Follow the recommended test flow diagram of Figure 4.c. Select a charging method and charge the DUT to a positive potential.d. Select a PUT and discharge the DUT. After discharging, wait a minimum of 1 secondand re-charge the DUT. The use of three (3) discharges at each charge voltage polarityis required.e. Set the charge voltage to a negative potential.f. Repeat steps (c) through (d) using the same PUT.g. Repeat steps (b) through (f) until every PUT (all component pins and/or terminals) isdischarged at the specified voltage.h. Test the next component in the sample group and repeat steps (a) through (g) until allcomponents in the sample group have been tested at the specified voltage level.i. Submit the components for complete parametric testing (final electrical verification) perthe user device specification at room temperature followed by hot temperature, unlessspecified otherwise in the user device specification, and determine whether thecomponents meet the failure criteria requirements specified in section 4. It is permittedto perform the parametric testing (final electrical verification) per user devicespecification after all sample groups have been tested.j. Using the next sample group, select the next stress voltage level as specified in Figure 4 and repeat steps (a) through (i).k. Repeat steps (a) through (j) until failure occurs or the component fails to meet the 125 volt stress voltage level.4. FAILURE CRITERIA:A component will be defined as a failure if, after exposure to ESD pulses, the component fails anyof the following criteria:1. The component exceeds the allowable shift values for the specific key parameters listedin Table 4. Other component parameters and allowable shift values may be specified inthe user device specification. During initial parametric testing, a data log shall be madefor each component listing the applicable parameter measurement values. This data logwill be compared to the parameters measured during final parametric testing to determinethe shift value. Components exceeding the allowable shift value will be defined as afailure.2. The component no longer meets the user device specification requirements. Completeparametric testing (initial and final electrical verification) shall be performed per applicableuser device specification at room temperature followed by hot temperature, unlessspecified otherwise in the user device specification.Table 4: Key Parameters and Allowable Shift ValuesComponent Type Parameters Maximum Allowable Shift Values Bipolar I CES, I CBO, and I EBO Ten times (10X) the initialmeasurementFET I DSS and I GSS Ten times (10X) the initialmeasurementIGBT I CES and I GES Ten times (10X) the initialmeasurementDiode I R Ten times (10X) the initialmeasurement5. ACCEPTANCE CRITERIA:A component passes a voltage level if all components stressed at that voltage level and belowpass. All the samples must meet the measurement requirements specified in section 3 and thefailure criteria requirements specified in section 4. Using the classification levels specified inTable 5, the supplier shall classify the components according to the maximum withstandingvoltage level. Due to the complex nature of the CDM event, a change in manufacturing process, design, materials, or component package may require reclassification according to this testmethod.Table 5: Discrete Component CDM ESD Classification LevelsComponent ClassificationMaximum Withstand VoltageC0 ≤ 125 V C1 > 125 V to ≤ 250 V C2 > 250 V to ≤ 500 V C3 > 500 V to ≤750 V C4 > 750 V to ≤ 1000 VC5> 1000 VFigure 4: Discrete Component CDM ESD Test Flow DiagramRevision HistoryRev #- Date of changeJuly 18, 2005Brief summary listing affected sectionsInitial Release.。

aec-q101 环境试验判定标准环境试验是指在特定的环境条件下对产品或设备进行可靠性和性能等指标的测试。

其中，SAE（Society of Automotive Engineers，美国汽车工程师协会）制定的环境试验标准之一就是AEC-Q101。

AEC-Q101是应用于汽车电子元器件的环境试验要求的标准。

该标准的目的是确保汽车电子元器件在各种恶劣的环境条件下能够正常工作，并满足汽车行业对可靠性和性能的要求。

AEC-Q101标准包括了一系列不同的试验项目，以保证元器件的可靠性和耐久性。

AEC-Q101标准的试验项目包括了温度循环试验、湿热循环试验、热冲击试验、丈量温度试验、机械振动试验、冲击试验等。

下面分别介绍这些试验项目的判定标准。

温度循环试验是通过将元器件在高温和低温之间循环进行多次，检测元器件在温度变化下的性能和可靠性。

判定标准根据元器件的不同，通常分为三个级别：Level1、Level2和Level3。

Level1要求元器件在-40°C至125°C之间进行1000次温度循环，而Level3要求元器件在-40°C至125°C之间进行5000次温度循环。

温度循环试验的主要判定依据是元器件的电性能是否发生明显变化，如电阻、电容等是否在合理的范围内。

湿热循环试验是将元器件放置于高温高湿度环境中进行多次循环，以测试其在高湿度环境下的稳定性。

判定标准同样根据元器件的不同而有所不同。

例如，对于陶瓷电容器来说，AEC-Q101标准要求在40°C、93%相对湿度下循环1000次，判定标准是元器件的电容值变化是否超过一定范围。

热冲击试验是将元器件迅速放置于高温和低温之间，以测试其在温度变化冲击下的可靠性。

判定标准通常根据元器件的不同而有所不同。

以半导体器件为例，对于AEC-Q101标准中的Level1，要求元器件在-40°C和150°C之间进行1000次热冲击试验，判定标准是元器件的电性能是否发生明显变化。

aecq标准关于高压组件AECQ标准是国际汽车电子协会的车规验证标准，包括多个子标准，其中与高压组件相关的标准是AEC-Q101。

AEC-Q101是针对离散组件的可靠性验证标准，其中涉及到高压组件的验证。

该标准要求高压组件在承受高电压、大电流等极端条件下，仍能保持稳定的性能和可靠性，以确保汽车电子系统的安全和可靠性。

具体来说，AEC-Q101对高压组件的验证包括以下几个方面：1. 耐压测试：测试高压组件在承受高电压时的稳定性和耐久性，以确保其在极端条件下不会发生击穿或短路等故障。

2. 绝缘测试：测试高压组件的绝缘性能，以确保其在高电压下不会产生漏电或电击等危险情况。

3. 热性能测试：测试高压组件在高温环境下的性能和稳定性，以确保其在高温下不会发生热失控或烧毁等故障。

4. 耐腐蚀测试：测试高压组件在恶劣环境下的耐腐蚀性能，以确保其在恶劣环境下不会发生腐蚀或老化等故障。

5.机械振动测试：高压组件在汽车电子系统中，需要承受各种机械振动，因此需要进行机械振动测试。

这一测试旨在验证高压组件在振动环境下性能的稳定性和可靠性，确保其在实际使用过程中不会因振动而导致故障。

6.电磁兼容性测试：汽车电子系统中的高压组件需要与其他电子元件共同工作，因此需要具备良好的电磁兼容性。

电磁兼容性测试旨在验证高压组件在电磁干扰环境下性能的稳定性和可靠性，确保其不会对其他电子元件产生干扰，也不会受到其他元件的干扰。

7.寿命周期测试：高压组件在汽车电子系统中的使用寿命至关重要。

寿命周期测试旨在模拟实际使用环境，验证高压组件在长时间运行过程中的性能稳定性和可靠性，确保其在使用寿命内保持良好的工作状态。

8.封装和材料测试：高压组件的封装和材料对其性能和可靠性具有重要影响。

封装和材料测试旨在验证高压组件的封装和材料是否具备足够的强度、耐热性、耐腐蚀性等性能，以确保其在极端环境下的稳定性。

9.失效模式分析：失效模式分析是对高压组件在各种工况下可能出现的失效模式进行研究，以便在设计阶段就消除潜在的故障隐患。

基于离散半导体元件应力测试认证的失效机理内容列表AEC-Q101 基于离散半导体元件应力测试认证的失效机理附录1: 认证家族的定义附录2: Q101 设计、构架及认证的证明附录3: 认证计划附录4: 数据表示格式附录5: 最小参数测试要求附录6: 邦线测试的塑封开启附录7: AEC-Q101与健壮性验证关系指南附件AEC-Q101-001: 人体模式静电放电测试AEC-Q101-002: 人体模式静电放电测试 (废止)AEC-Q101-003: 邦线切应力测试AEC-Q101-004: 同步性测试方法AEC-Q101-005: 静电放电试验–带电器件模型AEC-Q101-006: 12V系统灵敏功率设备的短路可靠性描述感谢任何涉及到复杂的技术文件都来自于各个方面的经验和技能。

为此汽车电子委员会由衷承认并感谢以下对该版文件有重大贡献的人：固定会员:Rick Forster Continental CorporationMark A. Kelly Delphi CorporationDrew Hoffman Gentex CorporationSteve Sibrel HarmanGary Fisher Johnson ControlsEric Honosowetz Lear Corporation技术成员:James Molyneaux Analog DevicesJoe Fazio Fairchild SemiconductorNick Lycoudes FreescaleWerner Kanert InfineonScott Daniels International RectifierMike Buzinski MicrochipBob Knoell NXP SemiconductorsZhongning Liang NXP SemiconductorsMark Gabrielle ON SemiconductorTom Siegel Renesas TechnologyTony Walsh Renesas TechnologyBassel Atallah STMicroelectronicsArthur Chiang VishayTed Krueger [Q101 Team Leader]Vishay其他支持者:John Schlais Continental CorporationJohn Timms Continental CorporationDennis L. Cerney International RectifierRene Rongen NXP SemiconductorsThomas Hough Renesas TechnologyThomas Stich Renesas Technology本文件是专门的纪念：Ted Krueger (1955-2013)Mark Gabrielle (1957-2013)注意事项AEC文件中的材料都是经过AEC技术委员会准备、评估和批准的。

aec q100 标准AEC Q100标准是汽车电子行业的质量管理标准，它是由汽车电子理事会（AEC）制定的，旨在确保汽车电子零部件在极端环境下的可靠性和稳定性。

这一标准对汽车电子零部件的设计、制造、测试和验证提出了严格的要求，对于保障汽车电子产品的质量和安全具有重要意义。

首先，AEC Q100标准对汽车电子零部件的可靠性进行了详细的规定。

在汽车行驶过程中，汽车电子零部件需要经受极端的温度、湿度、振动等环境条件，因此其可靠性至关重要。

AEC Q100标准要求汽车电子零部件在这些极端条件下仍能正常工作，并且在整个使用寿命内保持稳定性。

为了达到这一要求，汽车电子零部件需要经过严格的可靠性测试，包括高低温循环测试、湿热循环测试、振动测试等，以确保其能够在各种极端环境下正常工作。

其次，AEC Q100标准对汽车电子零部件的设计和制造提出了严格的要求。

汽车电子零部件的设计需要考虑到汽车行驶过程中的各种环境条件和挑战，以确保其能够在极端条件下正常工作。

同时，在制造过程中需要严格控制材料的选择和加工工艺，以确保产品的稳定性和可靠性。

此外，AEC Q100标准还对汽车电子零部件的质量管理体系提出了要求，包括对供应链的管理、过程控制和产品验证等方面，以确保产品的质量和稳定性。

最后，AEC Q100标准对汽车电子零部件的验证和认证提出了严格的要求。

在产品设计和制造完成后，需要进行严格的验证和测试，以确保产品符合AEC Q100标准的要求。

同时，汽车电子零部件需要通过相关的认证机构进行认证，以证明其符合AEC Q100标准的要求，并且能够在汽车行驶过程中保持稳定性和可靠性。

总之，AEC Q100标准是汽车电子行业的重要标准，它对汽车电子零部件的可靠性、设计、制造和验证提出了严格的要求，对于保障汽车电子产品的质量和安全具有重要意义。

遵循AEC Q100标准，可以帮助汽车电子企业提高产品质量，确保产品在极端环境下的可靠性和稳定性，从而为汽车行业的发展提供有力支持。