D. Single-Rail Self-timed Logic Circuits

组合逻辑电路英语Combinational logic circuits are electronic circuits that perform logical operations on input signals to produce an output signal. These circuits are made up of logic gates that are arranged in a way to perform a particular logical function.The logic gates used in combinational circuits include the AND gate, OR gate, NOT gate, NAND gate, NOR gate, and XOR gate. Each gate is designed to perform a specific logical operation. The gate function can be represented by a truth table which shows the output of the gate for every possible combination of input signals.One of the simplest combinational circuits is the Inverter circuit, which uses a NOT gate to invert the input signal. The output of this circuit is the opposite of the input signal. This circuit finds many applications in digital systems.The AND gate is one of the most commonly used gates in combinational circuits. It produces an output signal only when both input signals are high. The OR gate, on the other hand, produces an output signal when at least one input signal is high. The NAND gate is the negation of the AND gate, while the NOR gate is the negation of the OR gate.The XOR gate is another important gate used in combinational circuits. It produces an output signal when the input signals are different. This gate finds many applications in digital data processing, such as error detection and correction. Combinational circuits are used in many digital systems such ascomputers, calculators, and communication systems. They are designed to perform specific logical operations on input signals to produce output signals. These circuits are characterized by their speed, reliability, and ease of implementation.Sequential logic circuits are another type of digital circuit used in digital electronics. Unlike combinational circuits, sequential logic circuits contain a memory element that allows them to store information. These circuits are characterized by their state, which changes with the input signals and time.Sequential logic circuits include flip-flops, registers, and counters. These circuits find many applications in digital systems, such as digital clocks, frequency dividers, and shift registers.The basic building block of sequential logic circuits is the flip-flop.A flip-flop is a circuit that has two stable states, known as the SET state and RESET state. The flip-flop changes its state when certain input conditions are met. There are two types of flip-flops, namely the SR flip-flop and the JK flip-flop.Registers are another type of sequential logic circuit that is used to store data. These circuits are commonly used in microprocessors, digital signal processors, and other digital systems that require temporary storage of data.Counters are sequential logic circuits that are used to count the number of events that occur in a digital system. These circuits find many applications in digital systems, such as frequency dividers, timers, and pulse generators.In conclusion, combinational logic circuits are a fundamental building block of digital electronics. These circuits are used to perform logical operations on input signals to produce output signals. They are characterized by their speed, reliability, and ease of implementation. Sequential logic circuits, on the other hand, include a memory element that allows them to store information. These circuits are characterized by their state, which changes with the input signals and time. Both combinational and sequential logic circuits find many applications in digital systems, such as computers, calculators, and communication systems.。

交通用语-中英对照词典公交术语artery 干线articulated trolley bus 通道式无轨电车，铰接式无轨电车average riding distance 平均乘距average travel time 平均出行时间booking sheet 路单btanch 支线bunching 串车bus bay 港湾式车站bus shelter 候车亭carrying time 载客时间cash fare 普通票，零票city monthly ticket 市区月票city passenger flow 市区客流commuter 月票乘客compensation fare 补票cotroller 调度员cycling trip 自行车出行deadhead time for dispatch 调度空驶时间delay at stop 滞站delay time at stop 延误时间delay time at stop 滞站时间departure frequency 发车频率departure interval 发车间隔dual-powered trolley bus 双动源无轨电车dwell time 停站时间evening peak 晚高峰express line 快车线路fare-kilometre 票价里程final vehicle hour 末班车时间first vehicle hour 首班车时间fixed line 固定线路general monthly ticket 通用月票invalid ticket 废票junction station 枢纽站layover time 终点站停车时间light rail rapid transit car 快速有轨电车line section 线路断面living passenger flow 生活客流living trip 生活出行long distance bus stop 长途公共汽车站loop line 环形线路magnetic ticket 磁性车票main flow during the peak period 高峰主流向，高单向maximum section of passenger flow 客流最大断面，高断面monthly ticket 月票morning peak 早高峰non-service time 非运营时间off-peak time 非高峰时间off-running time 收车时间one-line monthly ticket 专线月票park-and-ride 驻车换乘park-and-ride place 换乘停车场parking lot 多层停车场passenger 乘客passenger attractive point 乘客吸引点passenger chartered 包车乘客passenger flow collector-distributor point 乘客集散点passenger flow diagram 客流图passholder 持证乘客peak hour 高峰小时peak time 高峰时间penalty fare 罚票platform 站台pull-in time 回场时间recreation passenger flow 文化客流recreation trip 文化出行red-time delay 灯阻时间remainder 留候乘客resident riding trips 居民乘车出行量resident trips 居民出行量revenue passenger 普票乘客ride time 乘行时间riding rate 乘车率round-trip ticket 往返票running interval 行车间隔safe driving 安全行车service frequency 行车频率service level 服务质量service monthly ticket 公用月票service time 运营时间single-trip time 单程时间skip-stop running 跳站运行slipping-stop running 放站运行station appearance 站貌station entrance-exit 车站出入口student flow 学习客流student monthly ticket 学生月票student trip 学习出行suburban line 郊区线路suburban monthly ticket 郊区月票suburban passenger flow 郊区客流temporary line 临时线路ticket 车票ticket book 本票ticket checking 查票ticket validity time 车票有效期timed stop 定时车站token 代用币touring line 游览线路tram 有轨电车transfer 换乘transfer convenience 换乘方便性transfer distance 换乘距离transfer passenger 换乘乘客transfer rate 换乘率transfer stop,transfer station 换乘站transfer time 换乘时间transit trip 公共交通出行travel time 出行时间trip 出行trip distance 出行距离trip mode 出行方式trip purpose 出行目的trip survey 出行调查turn round time 调头时间urban passenger flow 城市客流vehicle appearance 车容vehicle condition 车况violated passenger 违章乘客wait time 候乘时间waiting room 候车室waiting time 待命时间walking distance 步行距离walking time 步行时间walking trip 步行出行work passenger flow 工作客流working trip 工作出行zero fare 免费乘车accelerated run 赶点allowable speed 容许速度alternative route 比较线路area coverage 覆盖面积articulated bus 通道式公共汽车，铰接式公共汽车attendant 乘务员average kilometre of trye scrap 轮胎平均报废里程average stop spacing,average station spacing 平均站距averge distance carried 平均运距basic fare 基本票价behind the schedule 晚点，慢点bus 公共汽车bus only street(BOS) 公共汽车专用街道bus priority lane 公共汽车优先车道bus priority signal 公共汽车优先通行信号bus priority system 公共汽车优先通行系统cableway transport 索道缆车客运carrying kilometres 载客里程carrying times per shift 车班载客次数control centre 调度中心control station 调度站daily vehicle-kilometres 车日行程day and night line 昼夜线路deadhead kilometres 空驶里程deadhead speed for dispatch 调度空驶速度。

NuMicro®FamilyArm® ARM926EJ-S BasedNuMaker-HMI-N9H30User ManualEvaluation Board for NuMicro® N9H30 SeriesNUMAKER-HMI-N9H30 USER MANUALThe information described in this document is the exclusive intellectual property ofNuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.Nuvoton is providing this document only for reference purposes of NuMicro microcontroller andmicroprocessor based system design. Nuvoton assumes no responsibility for errors or omissions.All data and specifications are subject to change without notice.For additional information or questions, please contact: Nuvoton Technology Corporation.Table of Contents1OVERVIEW (5)1.1Features (7)1.1.1NuMaker-N9H30 Main Board Features (7)1.1.2NuDesign-TFT-LCD7 Extension Board Features (7)1.2Supporting Resources (8)2NUMAKER-HMI-N9H30 HARDWARE CONFIGURATION (9)2.1NuMaker-N9H30 Board － Front View (9)2.2NuMaker-N9H30 Board － Rear View (14)2.3NuDesign-TFT-LCD7 － Front View (20)2.4NuDesign-TFT-LCD7 － Rear View (21)2.5NuMaker-N9H30 and NuDesign-TFT-LCD7 PCB Placement (22)3NUMAKER-N9H30 AND NUDESIGN-TFT-LCD7 SCHEMATICS (24)3.1NuMaker-N9H30 － GPIO List Circuit (24)3.2NuMaker-N9H30 － System Block Circuit (25)3.3NuMaker-N9H30 － Power Circuit (26)3.4NuMaker-N9H30 － N9H30F61IEC Circuit (27)3.5NuMaker-N9H30 － Setting, ICE, RS-232_0, Key Circuit (28)NUMAKER-HMI-N9H30 USER MANUAL3.6NuMaker-N9H30 － Memory Circuit (29)3.7NuMaker-N9H30 － I2S, I2C_0, RS-485_6 Circuit (30)3.8NuMaker-N9H30 － RS-232_2 Circuit (31)3.9NuMaker-N9H30 － LCD Circuit (32)3.10NuMaker-N9H30 － CMOS Sensor, I2C_1, CAN_0 Circuit (33)3.11NuMaker-N9H30 － RMII_0_PF Circuit (34)3.12NuMaker-N9H30 － RMII_1_PE Circuit (35)3.13NuMaker-N9H30 － USB Circuit (36)3.14NuDesign-TFT-LCD7 － TFT-LCD7 Circuit (37)4REVISION HISTORY (38)List of FiguresFigure 1-1 Front View of NuMaker-HMI-N9H30 Evaluation Board (5)Figure 1-2 Rear View of NuMaker-HMI-N9H30 Evaluation Board (6)Figure 2-1 Front View of NuMaker-N9H30 Board (9)Figure 2-2 Rear View of NuMaker-N9H30 Board (14)Figure 2-3 Front View of NuDesign-TFT-LCD7 Board (20)Figure 2-4 Rear View of NuDesign-TFT-LCD7 Board (21)Figure 2-5 Front View of NuMaker-N9H30 PCB Placement (22)Figure 2-6 Rear View of NuMaker-N9H30 PCB Placement (22)Figure 2-7 Front View of NuDesign-TFT-LCD7 PCB Placement (23)Figure 2-8 Rear View of NuDesign-TFT-LCD7 PCB Placement (23)Figure 3-1 GPIO List Circuit (24)Figure 3-2 System Block Circuit (25)Figure 3-3 Power Circuit (26)Figure 3-4 N9H30F61IEC Circuit (27)Figure 3-5 Setting, ICE, RS-232_0, Key Circuit (28)Figure 3-6 Memory Circuit (29)Figure 3-7 I2S, I2C_0, RS-486_6 Circuit (30)Figure 3-8 RS-232_2 Circuit (31)Figure 3-9 LCD Circuit (32)NUMAKER-HMI-N9H30 USER MANUAL Figure 3-10 CMOS Sensor, I2C_1, CAN_0 Circuit (33)Figure 3-11 RMII_0_PF Circuit (34)Figure 3-12 RMII_1_PE Circuit (35)Figure 3-13 USB Circuit (36)Figure 3-14 TFT-LCD7 Circuit (37)List of TablesTable 2-1 LCD Panel Combination Connector (CON8) Pin Function (11)Table 2-2 Three Sets of Indication LED Functions (12)Table 2-3 Six Sets of User SW, Key Matrix Functions (12)Table 2-4 CMOS Sensor Connector (CON10) Function (13)Table 2-5 JTAG ICE Interface (J2) Function (14)Table 2-6 Expand Port (CON7) Function (16)Table 2-7 UART0 (J3) Function (16)Table 2-8 UART2 (J6) Function (16)Table 2-9 RS-485_6 (SW6~8) Function (17)Table 2-10 Power on Setting (SW4) Function (17)Table 2-11 Power on Setting (S2) Function (17)Table 2-12 Power on Setting (S3) Function (17)Table 2-13 Power on Setting (S4) Function (17)Table 2-14 Power on Setting (S5) Function (17)Table 2-15 Power on Setting (S7/S6) Function (18)Table 2-16 Power on Setting (S9/S8) Function (18)Table 2-17 CMOS Sensor Connector (CON9) Function (19)Table 2-18 CAN_0 (SW9~10) Function (19)NUMAKER-HMI-N9H30 USER MANUAL1 OVERVIEWThe NuMaker-HMI-N9H30 is an evaluation board for GUI application development. The NuMaker-HMI-N9H30 consists of two parts: a NuMaker-N9H30 main board and a NuDesign-TFT-LCD7 extensionboard. The NuMaker-HMI-N9H30 is designed for project evaluation, prototype development andvalidation with HMI (Human Machine Interface) function.The NuMaker-HMI-N9H30 integrates touchscreen display, voice input/output, rich serial port serviceand I/O interface, providing multiple external storage methods.The NuDesign-TFT-LCD7 can be plugged into the main board via the DIN_32x2 extension connector.The NuDesign-TFT-LCD7 includes one 7” LCD which the resolution is 800x480 with RGB-24bits andembedded the 4-wires resistive type touch panel.Figure 1-1 Front View of NuMaker-HMI-N9H30 Evaluation BoardNUMAKER-HMI-N9H30 USER MANUAL Figure 1-2 Rear View of NuMaker-HMI-N9H30 Evaluation Board1.1 Features1.1.1 NuMaker-N9H30 Main Board Features●N9H30F61IEC chip: LQFP216 pin MCP package with DDR (64 MB)●SPI Flash using W25Q256JVEQ (32 MB) booting with quad mode or storage memory●NAND Flash using W29N01HVSINA (128 MB) booting or storage memory●One Micro-SD/TF card slot served either as a SD memory card for data storage or SDIO(Wi-Fi) device●Two sets of COM ports:–One DB9 RS-232 port with UART_0 used 75C3232E transceiver chip can be servedfor function debug and system development.–One DB9 RS-232 port with UART_2 used 75C3232E transceiver chip for userapplication●22 GPIO expansion ports, including seven sets of UART functions●JTAG interface provided for software development●Microphone input and Earphone/Speaker output with 24-bit stereo audio codec(NAU88C22) for I2S interfaces●Six sets of user-configurable push button keys●Three sets of LEDs for status indication●Provides SN65HVD230 transceiver chip for CAN bus communication●Provides MAX3485 transceiver chip for RS-485 device connection●One buzzer device for program applicationNUMAKER-HMI-N9H30 USER MANUAL●Two sets of RJ45 ports with Ethernet 10/100 Mbps MAC used IP101GR PHY chip●USB_0 that can be used as Device/HOST and USB_1 that can be used as HOSTsupports pen drives, keyboards, mouse and printers●Provides over-voltage and over current protection used APL3211A chip●Retain RTC battery socket for CR2032 type and ADC0 detect battery voltage●System power could be supplied by DC-5V adaptor or USB VBUS1.1.2 NuDesign-TFT-LCD7 Extension Board Features●7” resolution 800x480 4-wire resistive touch panel for 24-bits RGB888 interface●DIN_32x2 extension connector1.2 Supporting ResourcesFor sample codes and introduction about NuMaker-N9H30, please refer to N9H30 BSP:https:///products/gui-solution/gui-platform/numaker-hmi-n9h30/?group=Software&tab=2Visit NuForum for further discussion about the NuMaker-HMI-N9H30:/viewforum.php?f=31 NUMAKER-HMI-N9H30 USER MANUALNUMAKER-HMI-N9H30 USER MANUAL2 NUMAKER-HMI-N9H30 HARDWARE CONFIGURATION2.1 NuMaker-N9H30 Board － Front View Combination Connector (CON8)6 set User SWs (K1~6)3set Indication LEDs (LED1~3)Power Supply Switch (SW_POWER1)Audio Codec(U10)Microphone(M1)NAND Flash(U9)RS-232 Transceiver(U6, U12)RS-485 Transceiver(U11)CAN Transceiver (U13)Figure 2-1 Front View of NuMaker-N9H30 BoardFigure 2-1 shows the main components and connectors from the front side of NuMaker-N9H30 board. The following lists components and connectors from the front view:NuMaker-N9H30 board and NuDesign-TFT-LCD7 board combination connector (CON8). This panel connector supports 4-/5-wire resistive touch or capacitance touch panel for 24-bits RGB888 interface.Connector GPIO pin of N9H30 FunctionCON8.1 - Power 3.3VCON8.2 - Power 3.3VCON8.3 GPD7 LCD_CSCON8.4 GPH3 LCD_BLENCON8.5 GPG9 LCD_DENCON8.7 GPG7 LCD_HSYNCCON8.8 GPG6 LCD_CLKCON8.9 GPD15 LCD_D23(R7)CON8.10 GPD14 LCD_D22(R6)CON8.11 GPD13 LCD_D21(R5)CON8.12 GPD12 LCD_D20(R4)CON8.13 GPD11 LCD_D19(R3)CON8.14 GPD10 LCD_D18(R2)CON8.15 GPD9 LCD_D17(R1)CON8.16 GPD8 LCD_D16(R0)CON8.17 GPA15 LCD_D15(G7)CON8.18 GPA14 LCD_D14(G6)CON8.19 GPA13 LCD_D13(G5)CON8.20 GPA12 LCD_D12(G4)CON8.21 GPA11 LCD_D11(G3)CON8.22 GPA10 LCD_D10(G2)CON8.23 GPA9 LCD_D9(G1) NUMAKER-HMI-N9H30 USER MANUALCON8.24 GPA8 LCD_D8(G0)CON8.25 GPA7 LCD_D7(B7)CON8.26 GPA6 LCD_D6(B6)CON8.27 GPA5 LCD_D5(B5)CON8.28 GPA4 LCD_D4(B4)CON8.29 GPA3 LCD_D3(B3)CON8.30 GPA2 LCD_D2(B2)CON8.31 GPA1 LCD_D1(B1)CON8.32 GPA0 LCD_D0(B0)CON8.33 - -CON8.34 - -CON8.35 - -CON8.36 - -CON8.37 GPB2 LCD_PWMCON8.39 - VSSCON8.40 - VSSCON8.41 ADC7 XPCON8.42 ADC3 VsenCON8.43 ADC6 XMCON8.44 ADC4 YMCON8.45 - -CON8.46 ADC5 YPCON8.47 - VSSCON8.48 - VSSCON8.49 GPG0 I2C0_CCON8.50 GPG1 I2C0_DCON8.51 GPG5 TOUCH_INTCON8.52 - -CON8.53 - -CON8.54 - -CON8.55 - -NUMAKER-HMI-N9H30 USER MANUAL CON8.56 - -CON8.57 - -CON8.58 - -CON8.59 - VSSCON8.60 - VSSCON8.61 - -CON8.62 - -CON8.63 - Power 5VCON8.64 - Power 5VTable 2-1 LCD Panel Combination Connector (CON8) Pin Function●Power supply switch (SW_POWER1): System will be powered on if the SW_POWER1button is pressed●Three sets of indication LEDs:LED Color DescriptionsLED1 Red The system power will beterminated and LED1 lightingwhen the input voltage exceeds5.7V or the current exceeds 2A.LED2 Green Power normal state.LED3 Green Controlled by GPH2 pin Table 2-2 Three Sets of Indication LED Functions●Six sets of user SW, Key Matrix for user definitionKey GPIO pin of N9H30 FunctionK1 GPF10 Row0 GPB4 Col0K2 GPF10 Row0 GPB5 Col1K3 GPE15 Row1 GPB4 Col0K4 GPE15 Row1 GPB5 Col1K5 GPE14 Row2 GPB4 Col0K6GPE14 Row2GPB5 Col1 Table 2-3 Six Sets of User SW, Key Matrix Functions●NAND Flash (128 MB) with Winbond W29N01HVS1NA (U9)●Microphone (M1): Through Nuvoton NAU88C22 chip sound input●Audio CODEC chip (U10): Nuvoton NAU88C22 chip connected to N9H30 using I2Sinterface–SW6/SW7/SW8: 1-2 short for RS-485_6 function and connected to 2P terminal (CON5and J5)–SW6/SW7/SW8: 2-3 short for I2S function and connected to NAU88C22 (U10).●CMOS Sensor connector (CON10, SW9~10)–SW9~10: 1-2 short for CAN_0 function and connected to 2P terminal (CON11)–SW9~10: 2-3 short for CMOS sensor function and connected to CMOS sensorconnector (CON10)Connector GPIO pin of N9H30 FunctionCON10.1 - VSSCON10.2 - VSSNUMAKER-HMI-N9H30 USER MANUALCON10.3 - Power 3.3VCON10.4 - Power 3.3VCON10.5 - -CON10.6 - -CON10.7 GPI4 S_PCLKCON10.8 GPI3 S_CLKCON10.9 GPI8 S_D0CON10.10 GPI9 S_D1CON10.11 GPI10 S_D2CON10.12 GPI11 S_D3CON10.13 GPI12 S_D4CON10.14 GPI13 S_D5CON10.15 GPI14 S_D6CON10.16 GPI15 S_D7CON10.17 GPI6 S_VSYNCCON10.18 GPI5 S_HSYNCCON10.19 GPI0 S_PWDNNUMAKER-HMI-N9H30 USER MANUAL CON10.20 GPI7 S_nRSTCON10.21 GPG2 I2C1_CCON10.22 GPG3 I2C1_DCON10.23 - VSSCON10.24 - VSSTable 2-4 CMOS Sensor Connector (CON10) FunctionNUMAKER-HMI-N9H30 USER MANUAL2.2NuMaker-N9H30 Board － Rear View5V In (CON1)RS-232 DB9 (CON2,CON6)Expand Port (CON7)Speaker Output (J4)Earphone Output (CON4)Buzzer (BZ1)System ResetSW (SW5)SPI Flash (U7,U8)JTAG ICE (J2)Power ProtectionIC (U1)N9H30F61IEC (U5)Micro SD Slot (CON3)RJ45 (CON12, CON13)USB1 HOST (CON15)USB0 Device/Host (CON14)CAN_0 Terminal (CON11)CMOS Sensor Connector (CON9)Power On Setting(SW4, S2~S9)RS-485_6 Terminal (CON5)RTC Battery(BT1)RMII PHY (U14,U16)Figure 2-2 Rear View of NuMaker-N9H30 BoardFigure 2-2 shows the main components and connectors from the rear side of NuMaker-N9H30 board. The following lists components and connectors from the rear view:● +5V In (CON1): Power adaptor 5V input ●JTAG ICE interface (J2) ConnectorGPIO pin of N9H30Function J2.1 - Power 3.3V J2.2 GPJ4 nTRST J2.3 GPJ2 TDI J2.4 GPJ1 TMS J2.5 GPJ0 TCK J2.6 - VSS J2.7 GPJ3 TD0 J2.8-RESETTable 2-5 JTAG ICE Interface (J2) Function●SPI Flash (32 MB) with Winbond W25Q256JVEQ (U7); only one (U7 or U8) SPI Flashcan be used●System Reset (SW5): System will be reset if the SW5 button is pressed●Buzzer (BZ1): Control by GPB3 pin of N9H30●Speaker output (J4): Through the NAU88C22 chip sound output●Earphone output (CON4): Through the NAU88C22 chip sound output●Expand port for user use (CON7):Connector GPIO pin of N9H30 FunctionCON7.1 - Power 3.3VCON7.2 - Power 3.3VCON7.3 GPE12 UART3_TXDCON7.4 GPH4 UART1_TXDCON7.5 GPE13 UART3_RXDCON7.6 GPH5 UART1_RXDCON7.7 GPB0 UART5_TXDCON7.8 GPH6 UART1_RTSCON7.9 GPB1 UART5_RXDCON7.10 GPH7 UART1_CTSCON7.11 GPI1 UART7_TXDNUMAKER-HMI-N9H30 USER MANUAL CON7.12 GPH8 UART4_TXDCON7.13 GPI2 UART7_RXDCON7.14 GPH9 UART4_RXDCON7.15 - -CON7.16 GPH10 UART4_RTSCON7.17 - -CON7.18 GPH11 UART4_CTSCON7.19 - VSSCON7.20 - VSSCON7.21 GPB12 UART10_TXDCON7.22 GPH12 UART8_TXDCON7.23 GPB13 UART10_RXDCON7.24 GPH13 UART8_RXDCON7.25 GPB14 UART10_RTSCON7.26 GPH14 UART8_RTSCON7.27 GPB15 UART10_CTSCON7.28 GPH15 UART8_CTSCON7.29 - Power 5VCON7.30 - Power 5VTable 2-6 Expand Port (CON7) Function●UART0 selection (CON2, J3):–RS-232_0 function and connected to DB9 female (CON2) for debug message output.–GPE0/GPE1 connected to 2P terminal (J3).Connector GPIO pin of N9H30 Function J3.1 GPE1 UART0_RXDJ3.2 GPE0 UART0_TXDTable 2-7 UART0 (J3) Function●UART2 selection (CON6, J6):–RS-232_2 function and connected to DB9 female (CON6) for debug message output –GPF11~14 connected to 4P terminal (J6)Connector GPIO pin of N9H30 Function J6.1 GPF11 UART2_TXDJ6.2 GPF12 UART2_RXDJ6.3 GPF13 UART2_RTSJ6.4 GPF14 UART2_CTSTable 2-8 UART2 (J6) Function●RS-485_6 selection (CON5, J5, SW6~8):–SW6~8: 1-2 short for RS-485_6 function and connected to 2P terminal (CON5 and J5) –SW6~8: 2-3 short for I2S function and connected to NAU88C22 (U10)Connector GPIO pin of N9H30 FunctionSW6:1-2 shortGPG11 RS-485_6_DISW6:2-3 short I2S_DOSW7:1-2 shortGPG12 RS-485_6_ROSW7:2-3 short I2S_DISW8:1-2 shortGPG13 RS-485_6_ENBSW8:2-3 short I2S_BCLKNUMAKER-HMI-N9H30 USER MANUALTable 2-9 RS-485_6 (SW6~8) FunctionPower on setting (SW4, S2~9).SW State FunctionSW4.2/SW4.1 ON/ON Boot from USB SW4.2/SW4.1 ON/OFF Boot from eMMC SW4.2/SW4.1 OFF/ON Boot from NAND Flash SW4.2/SW4.1 OFF/OFF Boot from SPI Flash Table 2-10 Power on Setting (SW4) FunctionSW State FunctionS2 Short System clock from 12MHzcrystalS2 Open System clock from UPLL output Table 2-11 Power on Setting (S2) FunctionSW State FunctionS3 Short Watchdog Timer OFFS3 Open Watchdog Timer ON Table 2-12 Power on Setting (S3) FunctionSW State FunctionS4 Short GPJ[4:0] used as GPIO pinS4Open GPJ[4:0] used as JTAG ICEinterfaceTable 2-13 Power on Setting (S4) FunctionSW State FunctionS5 Short UART0 debug message ONS5 Open UART0 debug message OFFTable 2-14 Power on Setting (S5) FunctionSW State FunctionS7/S6 Short/Short NAND Flash page size 2KBS7/S6 Short/Open NAND Flash page size 4KBS7/S6 Open/Short NAND Flash page size 8KBNUMAKER-HMI-N9H30 USER MANUALS7/S6 Open/Open IgnoreTable 2-15 Power on Setting (S7/S6) FunctionSW State FunctionS9/S8 Short/Short NAND Flash ECC type BCH T12S9/S8 Short/Open NAND Flash ECC type BCH T15S9/S8 Open/Short NAND Flash ECC type BCH T24S9/S8 Open/Open IgnoreTable 2-16 Power on Setting (S9/S8) FunctionCMOS Sensor connector (CON9, SW9~10)–SW9~10: 1-2 short for CAN_0 function and connected to 2P terminal (CON11).–SW9~10: 2-3 short for CMOS sensor function and connected to CMOS sensorconnector (CON9).Connector GPIO pin of N9H30 FunctionCON9.1 - VSSCON9.2 - VSSCON9.3 - Power 3.3VCON9.4 - Power 3.3V NUMAKER-HMI-N9H30 USER MANUALCON9.5 - -CON9.6 - -CON9.7 GPI4 S_PCLKCON9.8 GPI3 S_CLKCON9.9 GPI8 S_D0CON9.10 GPI9 S_D1CON9.11 GPI10 S_D2CON9.12 GPI11 S_D3CON9.13 GPI12 S_D4CON9.14 GPI13 S_D5CON9.15 GPI14 S_D6CON9.16 GPI15 S_D7CON9.17 GPI6 S_VSYNCCON9.18 GPI5 S_HSYNCCON9.19 GPI0 S_PWDNCON9.20 GPI7 S_nRSTCON9.21 GPG2 I2C1_CCON9.22 GPG3 I2C1_DCON9.23 - VSSCON9.24 - VSSTable 2-17 CMOS Sensor Connector (CON9) Function●CAN_0 Selection (CON11, SW9~10):–SW9~10: 1-2 short for CAN_0 function and connected to 2P terminal (CON11) –SW9~10: 2-3 short for CMOS sensor function and connected to CMOS sensor connector (CON9, CON10)SW GPIO pin of N9H30 FunctionSW9:1-2 shortGPI3 CAN_0_RXDSW9:2-3 short S_CLKSW10:1-2 shortGPI4 CAN_0_TXDSW10:2-3 short S_PCLKTable 2-18 CAN_0 (SW9~10) Function●USB0 Device/HOST Micro-AB connector (CON14), where CON14 pin4 ID=1 is Device,ID=0 is HOST●USB1 for USB HOST with Type-A connector (CON15)●RJ45_0 connector with LED indicator (CON12), RMII PHY with IP101GR (U14)●RJ45_1 connector with LED indicator (CON13), RMII PHY with IP101GR (U16)●Micro-SD/TF card slot (CON3)●SOC CPU: Nuvoton N9H30F61IEC (U5)●Battery power for RTC 3.3V powered (BT1, J1), can detect voltage by ADC0●RTC power has 3 sources:–Share with 3.3V I/O power–Battery socket for CR2032 (BT1)–External connector (J1)●Board version 2.1NUMAKER-HMI-N9H30 USER MANUAL2.3 NuDesign-TFT-LCD7 －Front ViewFigure 2-3 Front View of NuDesign-TFT-LCD7 BoardFigure 2-3 shows the main components and connectors from the Front side of NuDesign-TFT-LCD7board.7” resolution 800x480 4-W resistive touch panel for 24-bits RGB888 interface2.4 NuDesign-TFT-LCD7 －Rear ViewFigure 2-4 Rear View of NuDesign-TFT-LCD7 BoardFigure 2-4 shows the main components and connectors from the rear side of NuDesign-TFT-LCD7board.NuMaker-N9H30 and NuDesign-TFT-LCD7 combination connector (CON1).NUMAKER-HMI-N9H30 USER MANUAL 2.5 NuMaker-N9H30 and NuDesign-TFT-LCD7 PCB PlacementFigure 2-5 Front View of NuMaker-N9H30 PCB PlacementFigure 2-6 Rear View of NuMaker-N9H30 PCB PlacementNUMAKER-HMI-N9H30 USER MANUALFigure 2-7 Front View of NuDesign-TFT-LCD7 PCB PlacementFigure 2-8 Rear View of NuDesign-TFT-LCD7 PCB Placement3 NUMAKER-N9H30 AND NUDESIGN-TFT-LCD7 SCHEMATICS3.1 NuMaker-N9H30 － GPIO List CircuitFigure 3-1 shows the N9H30F61IEC GPIO list circuit.Figure 3-1 GPIO List Circuit NUMAKER-HMI-N9H30 USER MANUAL3.2 NuMaker-N9H30 － System Block CircuitFigure 3-2 shows the System Block Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-2 System Block Circuit3.3 NuMaker-N9H30 － Power CircuitFigure 3-3 shows the Power Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-3 Power Circuit3.4 NuMaker-N9H30 － N9H30F61IEC CircuitFigure 3-4 shows the N9H30F61IEC Circuit.Figure 3-4 N9H30F61IEC CircuitNUMAKER-HMI-N9H30 USER MANUAL3.5 NuMaker-N9H30 － Setting, ICE, RS-232_0, Key CircuitFigure 3-5 shows the Setting, ICE, RS-232_0, Key Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-5 Setting, ICE, RS-232_0, Key Circuit3.6 NuMaker-N9H30 － Memory CircuitFigure 3-6 shows the Memory Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-6 Memory Circuit3.7 NuMaker-N9H30 － I2S, I2C_0, RS-485_6 CircuitFigure 3-7 shows the I2S, I2C_0, RS-486_6 Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-7 I2S, I2C_0, RS-486_6 Circuit3.8 NuMaker-N9H30 － RS-232_2 CircuitFigure 3-8 shows the RS-232_2 Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-8 RS-232_2 Circuit3.9 NuMaker-N9H30 － LCD CircuitFigure 3-9 shows the LCD Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-9 LCD Circuit3.10 NuMaker-N9H30 － CMOS Sensor, I2C_1, CAN_0 CircuitFigure 3-10 shows the CMOS Sensor,I2C_1, CAN_0 Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-10 CMOS Sensor, I2C_1, CAN_0 Circuit3.11 NuMaker-N9H30 － RMII_0_PF CircuitFigure 3-11 shows the RMII_0_RF Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-11 RMII_0_PF Circuit3.12 NuMaker-N9H30 － RMII_1_PE CircuitFigure 3-12 shows the RMII_1_PE Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-12 RMII_1_PE Circuit3.13 NuMaker-N9H30 － USB CircuitFigure 3-13 shows the USB Circuit.NUMAKER-HMI-N9H30 USER MANUALFigure 3-13 USB Circuit3.14 NuDesign-TFT-LCD7 － TFT-LCD7 CircuitFigure 3-14 shows the TFT-LCD7 Circuit.Figure 3-14 TFT-LCD7 CircuitNUMAKER-HMI-N9H30 USER MANUAL4 REVISION HISTORYDate Revision Description2022.03.24 1.00 Initial version NUMAKER-HMI-N9H30 USER MANUALNUMAKER-HMI-N9H30 USER MANUALImportant NoticeNuvoton Products are neither intended nor warranted for usage in systems or equipment, anymalfunction or failure of which may cause loss of human life, bodily injury or severe propertydamage. Such applications are deemed, “Insecure Usage”.Insecure usage includes, but is not limited to: equipment for surgical implementation, atomicenergy control instruments, airplane or spaceship instruments, the control or operation ofdynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all typesof safety devices, and other applications intended to support or sustain life.All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claimsto Nuvoton as a result of customer’s Insecure Usage, custome r shall indemnify the damagesand liabilities thus incurred by Nuvoton.。

专利名称：Self-timed CMOS static logic circuit发明人：Christopher McCall Durham,Peter JuergenKlim申请号：US09067153申请日：19980427公开号：US06522170B1公开日：20030218专利内容由知识产权出版社提供专利附图：摘要：A Self-Timed CMOS Static Circuit Technique has been invented that provides full handshaking to the source circuits; prevention of input data loss by virtue off interlocking both internal and incoming signals; full handshaking between the circuit and sink self-timed circuitry; prevention of lost access operation information by virtue of an internal lock-out for the output data information; and plug-in compatibility for some classes of dynamic self-timed systems. The net result of the overall system is that static CMOS circuits can now be used to generate a self-timed system. This is in contrast to existing self-timed systems that rely on dynamic circuits. Thus, the qualities of the static circuitry can be preserved and utilized to their fullest advantage.申请人：INTERNATIONAL BUSINESS MACHINES CORPORATION代理机构：Winstead Sechrest & Minick P.C.代理人：Kelly K. Kordzik,Robert M. Carwell更多信息请下载全文后查看。

城市公共交通常用名词术语一、基本术语1.1城市公共交通urban public transport城市中供公众乘用的、经济方便的各种交通方式的总称。

1.2公共交通方式public transport mode按公共交通工具类型划分的各种客运形式。

1.3城市公共交通系统urban public transport system由多种城市公共交通方式组成的有机总体。

1.4大运量客讼低?br> mass transit system城市公共交通中，运送大量乘客的有机总体。

1.5快速轨道交通rail rapid transit(RRT)通常以电能为动力，采取轮轨运黑心方式的快速大运量公共交通之总称。

1.6地下铁道，地铁subway由于城市中的一种速度快、运量大、行车间隔小的电动有轨客运系统，其部分线路设一地下隧道内。

1.7单轨运输系统monorail transit system车厢跨骑或悬持在架空的单轨上，由电力驱动的轨道客运系统。

1.8新交通系统new transport system新开发的具有高速、准点、舒适和污染小的交通方式及其运行服务系统的总体。

1.9垂直运送系统vertical transit system沿铅直方向运送乘客的有机整体。

1.10应急公共交通系统emergency public transport system在非常时期为应变而组成的临时公共交通系统。

1.11城市客渡urban ferry在城市区域及邻近郊县内，以运送乘客为主，横渡江河、湖泊的水上交通方式。

1.12索道缆车客运cableway transport在以架空钢索为轨道的线路上，以电能为动力由钢索牵引载客工具的运输方式。

1.13轨道缆车客运funicular railway transport在坡面铺设的轨道上，以电能为动力由钢索牵引载客工具的运输方式。

1.14公共交通信息系统public transport information system与公共交通服务有关的信号、数据、显示等所构成的有机整体。

防破解技术这里我们探讨一下可加强微控制器保护能力的技术。

如果某个项目能被分解成几部分，就可以把每部分放在不同的微控制器中。

那破解者就不得不对整个设备的所有部分进行反向工程。

但是，这种方法对于成本敏感的大批量产品来讲，不是个好方法。

从基于微控制器的设计转向 CPLD/FPGA 可能是个好的选择，因为破解 CPLD/FPGA 需要花费更多。

即使是将重要部分放在“不安全”的基于 SRAM 的 FPGA 中，其破解难度也相当大。

使用多层板和 BGA 封装也可以增大破解难度，因为肉眼无法看到内部互联，并且不可能直接访问 BGA 的引脚来进行分析。

为了能够访问引脚，芯片必须焊下来，放在特殊的测试适配器上。

这就需要特殊的工具和训练有素的工程师。

此外，BGA 的封装不同于 DIP SOIC 和QFP 之类，它的封装更难被打开。

常用的保护敏感信息的方法是加密数据。

但是，更应该需要关注密钥的存储和管理。

如果密钥是可编程的或能被随时修改，这非常类似于保存在 EEFPROM 中的情形。

把无格式的信息放在可编程的存储器中，对于系统的安全是个威胁。

半侵入式攻击和缺陷注入式攻击，给微控制器芯片的硬件安全带来巨大威胁，所以我们就研究一些方法来阻止这些攻击。

可以用自同步双线电路（Self-timed dual-rail circuit）设计技术，那样逻辑“1”或“0”不是被解码成在单线上的高或低电平，而是一对线上的‘HL’或‘LH’。

组合信号‘HH’会产生报警，导致处理器复位。

电路可以被设计成即使单个晶体管失效也不会导致安全问题。

这种技术会增加功耗分析攻击的难度。

当然，要平衡所需安全等级和保护技术的开销。

注：在使用 8031 的年代，不得不外扩 ROM／RAM。

当时有人使用到地址线／数据线的位交错技术，也就是某两位或更多的位线相互对掉。

这需要在画板子和写程序的时候同时使用。

1 不印字，重新印字和重新封装对付低级的攻击，业内广泛使用抹掉印字的方法，但它不能阻止信心坚定的对手。

低功耗高效的D触发器电路摘要本文列举了低功耗高速率D触发器的设计。

它提出了各种技术，以尽量减少次临界漏电功率与CMOS电路的功耗。

本文提出的D触发器的一种设计以提高系统的整体速率，与其他电路相比。

这种技术可以让电路来实现最低功耗和最小的晶体管数量。

1.引言晶体管特征尺寸的缩放技术已经提供了一个在过去三十年中硅行业的显著的创新方法。

设计师们正努力使硅面积更小，更高速率,低功耗和可靠性，由于便携式电子产品的需求不断增加和普及。

动态功耗是数字系统的功耗主要因素之一。

为了减少动态功耗，已经取得了更小的几何尺寸，结果影响了静态功耗。

动态功耗与电源电压的平方成正比，因此显著降低电压以降低能耗。

器件尺寸的连续缩放，导致今天的超大规模集成电路的阈值电压显着增加，亚阈值漏电流成倍增长。

这大大增加了整体的总功耗。

在最近的纳米CMOS技术，如 90-、45-nm, 漏电流是几乎占了一半的总功耗这是并不少见。

在90nm节点，漏功率可高达35％的芯片功率。

由于便携式设备的使用和无线系统日益增强，减少这种功耗是非常必要的。

这些设备比单一的超大规模集成电路芯片的复杂得多。

他们有几个组成部分，可能是数字的或非数字的。

延长电池寿命为嵌入式应用，是在系统级完成的。

高功耗减少了电池使用寿命。

因此，电源最优化技术应适用于不同层次的数字化设计。

这些技术之一是使用低功耗的逻辑模式，这应该运用在逻辑锁存器和触发器的设计中。

2.简单文献回顾图1显示了单阈值传输门触发器。

D触发器采用CMOS传输门的构造如图2所示。

第一阶段（主）, 由时钟信号驱动，而第二阶段（从）是由倒时钟信号驱动。

因此，主阶段是正电平感应而从阶段是负电平感应。

图1：单阈值传输门触发器图2：CMOS D型触发器的实现时钟为高电平时，D输入主传输门，而从传输门保持有以前的值。

当时钟, 从逻辑“1”变化到逻辑“0”时，主锁存器停止采样输入，存储在时钟过渡期间的D值。

在同一时间，从锁存器变得透明，传递存储的主Qm值到从传输门的输出。

公交车术语artery干线articulated trolley bus 通道式无轨电车，铰接式无轨电车average riding distance 平均乘距average travel time 平均出行时间booking sheet 路单btanch 支线bunching 串车bus bay 港湾式车站bus shelter候车亭carrying time 载客时间cash fare普通票，零票city monthly ticket 市区月票city passenger flow 市区客流commuter月票乘客compensation fare补票cotroller 调度员cycling trip 自行车出行deadhead time for dispatch调度空驶时间delay at stop 滞站delay time at stop 延误时间delay time at stop 滞站时间departure frequency发车频率departure interval发车间隔dual-powered trolley bus 双动源无轨电车dwell time 停站时间evening peak 晚高峰express line 快车线路fare-kilometre 票价里程final vehicle hour 末班车时间first vehicle hour 首班车时间fixed line 固定线路general monthly ticket 通用月票invalid ticket 废票junction station 枢纽站layover time 终点站停车时间light rail rapid transit car 快速有轨电车line section 线路断面living passenger flow 生活客流living trip 生活出行long distance bus stop 长途公共汽车站loop line 环形线路magnetic ticket 磁性车票main flow during the peak period 高峰主流向，高单向maximum section of passenger flow 客流最大断面，高断面monthly ticket 月票morning peak 早高峰non-service time 非运营时间off-peak time 非高峰时间off-running time 收车时间one-line monthly ticket 专线月票park-and-ride 驻车换乘park-and-ride place 换乘停车场parking lot 多层停车场passenger 乘客passenger attractive point 乘客吸引点passenger chartered 包车乘客passenger flow collector-distributor point 乘客集散点passenger flow diagram客流图passholder 持证乘客peak hour 高峰小时peak time 高峰时间penalty fare罚票platform站台pull-in time 回场时间recreation passenger flow 文化客流recreation trip 文化出行red-time delay灯阻时间remainder留候乘客resident riding trips 居民乘车出行量resident trips 居民出行量revenue passenger 普票乘客ride time 乘行时间riding rate 乘车率round-trip ticket 往返票running interval行车间隔safe driving 安全行车service frequency行车频率service level 服务质量service monthly ticket 公用月票service time 运营时间single-trip time 单程时间skip-stop running 跳站运行slipping-stop running 放站运行station appearance站貌station entrance-exit 车站出入口student flow 学习客流student monthly ticket 学生月票student trip 学习出行suburban line 郊区线路suburban monthly ticket 郊区月票suburban passenger flow 郊区客流temporary line 临时线路ticket 车票ticket book 本票ticket checking 查票ticket validity time 车票有效期timed stop 定时车站token 代用币touring line 游览线路tram 有轨电车transfer换乘transfer convenience换乘方便性transfer distance 换乘距离transfer passenger 换乘乘客transfer rate 换乘率transfer stop,transfer station 换乘站transfer time 换乘时间transit trip 公共交通出行travel time 出行时间trip 出行trip distance 出行距离trip mode出行方式trip purpose 出行目的trip survey出行调查turn round time 调头时间urban passenger flow 城市客流vehicle appearance车容vehicle condition 车况violated passenger 违章乘客wait time 候乘时间waiting room 候车室waiting time 待命时间walking distance 步行距离walking time 步行时间walking trip 步行出行work passenger flow 工作客流working trip 工作出行zero fare免费乘车accelerated run 赶点allowable speed 容许速度alternative route比较线路area coverage 覆盖面积articulated bus 通道式公共汽车，铰接式公共汽车attendant乘务员average kilometre of trye scrap轮胎平均报废里程average stop spacing,average station spacing 平均站距averge distance carried 平均运距basic fare基本票价behind the schedule 晚点，慢点bus 公共汽车bus only street(BOS) 公共汽车专用街道bus priority lane 公共汽车优先车道bus priority signal公共汽车优先通行信号bus priority system 公共汽车优先通行系统cableway transport索道缆车客运carrying kilometres 载客里程carrying times per shift车班载客次数control centre 调度中心control station 调度站daily vehicle-kilometres 车日行程day and night line 昼夜线路deadhead kilometres 空驶里程deadhead speed for dispatch调度空驶速度。

专利名称：SELF-TIMED PULSE CONTROL CIRCUIT发明人：PARTOVI, Hamid,HOLST, John, Christian,BEN-MEIR, Amos申请号：EP97945362.0申请日：19970929公开号：EP0929939A1公开日：19990721专利内容由知识产权出版社提供摘要：A Self-Timed Pulse Control circuit and operating method is highly useful for adjusting delays of timing circuits to prevent logic races. In an illustrative example, the STPC circuit is used to adjust timing in self-timed sense amplifiers. The Self-Timed Pulse Control (STPC) circuit is integrated onto an integrated circuit chip along with the circuit structures that are timed using timing structures that are adjusted using STPC. The STPC is also advantageously used to modify the duty cycle of clocks, determine critical timing paths so that overall circuit speed is optimized, and adjusting dynamic circuit timing so that inoperable circuits become useful.申请人：ADVANCED MICRO DEVICES INC.地址：One AMD Place, P.O. Box 3453 Sunnyvale, California 94088-3453 US国籍：US代理机构：Sanders, Peter Colin Christopher更多信息请下载全文后查看。

Lecture 14: Asynchronous Logiccompare machines operating at a point where they achieve as high throughput as possible without significantly increasing latency.We will take synchronous designs as a baseline. A static flop-based system has a cycle time:T = t logic-static + t clk->Q + t setup + t skew(EQ 1) A skew-tolerant domino system has a cycle timeT = t logic-domino(EQ 2)Both baselines involve t logic, either static or domino. The flop-based system adds three sources of overhead, while the skew-tolerant domino system is better because it has no overhead.In the next sections, we will look at how several asynchronous circuit techniques work and at what overhead appears in the cycle time.2.0 Asynchronous Design PrinciplesAsynchronous designs replace clocks, which nominally reach all parts of a chip simulta-neously, with control signals which only enforce sequence relationships between commu-nicating blocks which they control.Key concepts of asynchronous design include events and Muller C-elements which com-bine events. They are described in Sutherland’s micropipeline paper.3.0 MicropipelinesSutherland describes micropipelines in his classic paper, so the discussion will not be repeated. There are numerous ways that micropipelined control circuits can be used to sequence logic. The choices are analogous to using clocks to control flip-flops, two-phase latches, and pulsed latches. The technique presented in Figure 17 of the micropipeline paper corresponds to synchronous flop-based design.The control path uses the delay line plus the delay of two C-elements and some wiring to try to match the delay of data through the datapath logic and registers. The registers are very similar to master-slave flip-flops, but are turned on and off by events on “Capture” and “Pass” control lines rather than by rising edges of a clock.The latency of each stage may be different, but throughput is set by the slowest stage. This stage ideally has a delay of t logic-static + t clk->Q + t setup, i.e. the delay of the logic plus the delay of the register. To achieve this delay, the control circuit delays would have to be per-fectly tuned to match the logic delay. If the control ran too fast, it would cause registers to capture incorrect data. Tuning the control to the data delays is a classic delay-matchingLecture 14: Asynchronous Logicproblem and requires extra margin on the control delays to guarantee they are always long enough. This margin may be 30 - 50% of the nominal delay, depending on how well the matching elements track data delays and how well the designer wants to sleep at night. Hence, actual cycle time is:T = t logic-static + t clk->Q + t setup + t margin(EQ 3) 4.0 Asynchronous Domino LogicDual-rail domino logic is very well-suited for building asynchronous circuits because it solves the problem of determining when a block of logic is done. Single-rail domino and static circuits often require large margin on a delay element which must indicate when the logic is done. Dual-rail domino automatically signals when the logic is done because out-puts switch from both rails being 0 to one rail being 1.A block of dual-rail domino gates consists of one or more domino gates using the same control signal to trigger precharge and evaluation. Blocks correspond to phases of logic in synchronous skew-tolerant domino. A completion detector circuit easily can be built for dual-rail domino blocks. When the block has only one output, completion is signaled by the OR of the two rails carrying the output. When a block has multiple outputs, it is com-plete when the latest output completes. If outputs complete at the same time or one is more critical than the others, only one output must be examined. If any of several outputs might be most critical in a data-dependent fashion, completion must be detected for each output, then completion for the block is indicated as the AND of completion of each block. Given signals indicating the completion of each block, we can write rules determining when a block is allowed to precharge and evaluate:1.a block may not precharge until the next block has evaluated and the previous blockprecharged2.a block may not evaluate until the next block has precharged and the previous block hasevaluatedA block may not precharge until its results have been consumed. This consumption is indi-cated by the next block signaling completion. Once the next block has used the inputs, the current block no longer must hold them. This is similar to the concept that the last gate in one phase of skew-tolerant domino may precharge when the first gate in the next phase has evaluated and consumed the result. No latches are needed between blocks or phases to hold data as long as the consumption before precharge rule is enforced.The block also should not precharge until its predecessor has precharged. This prevents racethrough which could occur if the predecessor remained in evaluation while the current block precharges, reenters evaluation, and incorrectly evaluates using the stale data from the predecessor.Similarly, a block must not evaluate until the next block has precharged to prevent racethrough. Finally, a block should not evaluate unless its inputs are valid. A conservativeLecture 14: Asynchronous LogicLecture 14: Asynchronous LogicLecture 14: Asynchronous LogicLecture 14: Asynchronous LogicLecture 14: Asynchronous Logicchronous domino can have overhead, but when cleverly designed to overlap clocks, achieves zero overhead in much the same way as skew-tolerant domino.Hence, arguments to use asynchronous logic for higher performance on general-purpose logic are mostly misleading. Nevertheless, there are special cases, mostly already in wide use, where asynchronous circuits are important. Self-timed RAMs and PLAs take advan-tage of the regularity of the structures to generate control signals exactly when needed by the logic. Long operations like with different best and worst-case delays can also benefit from signalling completion. Communication between systems with unrelated clocks inherently requires asynchronous techniques.Many of the advantages claimed by asynchronous circuits are not a result of asynchronous control, but rather just good design practices. For example, zero-overhead self-timed dom-ino logic was faster than slow synchronous pipelines constructed of static logic and flip-flops. The essential improvement, however, was not eliminating clocks, but rather using fast domino gates and guaranteeing that gates are in evaluation before the data arrives. Similarly, some asynchronous circuits are recommended for low power, but the essential advantage is that the activity factor is reduced by avoiding unnecessary switching. Syn-chronous systems can gain much of this advantage by gating clocks to unused blocks. Synchronous circuit design faces challenges in the future, especially from clock distribu-tion and skew. Instead of discarding all the advantages of clocks, however, it may be more effective to continue borrowing ideas from asynchronous design and integrating them intoa clocked framework.7.0 ReferencesThis lecture has taken a somewhat doubtful attitude toward asynchronous design. For a contrasting perspective, consider some of these references by authors with experience con-structing practical asynchronous systems.I. Sutherland, “Micropipelines,” Communications of the ACM, vol. 32, no. 6, pp. 720-738, June 1989.C. Mead and L. Conway, Introduction to VLSI Systems Addison-Wesley: Reading, MA, 1980 (esp. Ch. 7 on System Timing by Chuck Seitz).T. Williams, Self-timed rings and their application to division, Ph.D. dissertation, Stanford University, Stanford, CA, May 1991.T. Williams, “Performance of Iterative Computations in Self-Timed Rings,” J. VLSI Sig. Proc., no. 7, pp. 17-31, Feb. 1994.T. Williams and M. Horowitz, “A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider,” IEEE J. Solid-State Circuits, vol. 26, no. 11, pp. 1651-1661, Nov. 1991.。

地铁车辆逻辑控制单元可靠性分析1　引言随着我国经济快速发展、城市化进程快速推进，城市轨道交通也在快速发展，为有效地保证地铁建设、运营的安全，促进城市轨道交通健康发展；在轨道交通建设中，在不同领域、不同程度上运用了RAMS管理技术[1]，并对轨道交通装备的可靠性、可用性和安全性提出更高的要求。

目前既有线路地铁车辆大多采用继电器硬线逻辑控制，列车控制系统存在故障率较高、可靠性较低、维护成本偏高等诸多缺点，现在地铁车辆普遍采用逻辑控制系统代替传统逻辑控制方案，以满足智能化、网络化、高可靠性、低维护成本和长寿命的要求[2]。

2　列车LCU配置方案LCU（logic control unit 逻辑控制单元）是针对轨道车辆逻辑控制而设计的车载系统，采用系统稳定、成熟可靠的分布式网络技术，通过光耦和场效应管等无触点电路替代列车传统的中间继电器、时间继电器、双稳态继电器等有触点控制电路，实现列车逻辑控制、列车网络通信和故障诊断等功能。

极大简化车辆整车控制电路、提升整车智能化水平，具有直接输人直流信号、输出大电流驱动负载的能力，还具有控制方式灵活、编程方便、布线简洁、检修方便等特点。

2.1　LCU拓扑结构图LCU是专门为在轨道交通环境下应用而设计的数字逻辑控制装置，采集司机控制器、按键开关组、隔离开关、接触器辅助触点等DC110V的信号，经逻辑计算后，输出驱动车辆各类负载，完成指定的时序控制功能[3-4]。

南宁轨道交通4号线车辆为6节编组，采用LCU控制电路方案，整车配置4套LCU，采用分布式结构，其中Tc1、Tc2、Mp1、Mp2车各安装1套LCU，M1、M2车不安装LCU。

其中，Tc1、Tc2车采用司机室3U机箱，Mp1、Mp2车采用客室3U机箱，各节车LCU之间通过CAN网络实现数据共享，Tc车的LCU通过MVB网关与TCMS建立数据连接，以实现整车逻辑控制、列车网络通信和故障诊断等功能，整车LCU拓扑结构图如图1所示。

英语作文-探索集成电路设计中的数字电路与模拟电路技术Integrated circuit design is a fascinating field that bridges the gap between electrical engineering and computer science. It involves the creation of complex electronic systems through the integration of thousands, or even millions, of tiny components onto a single chip. At the heart of this discipline lie two fundamental technologies: digital and analog circuits. Each serves a unique purpose and presents distinct challenges and opportunities for engineers.Digital circuits are the backbone of modern computing and communication systems. They operate using discrete signals, typically representing binary values of 0 and 1. These circuits are designed to perform logical operations and process data in the form of bits. The precision and reliability of digital circuits make them ideal for applications where accuracy and consistency are paramount.On the other hand, analog circuits deal with continuous signals that can represent a wide range of values. They are essential in interfacing with the real world, as they can process the complex and variable signals that our environment and biological systems produce. Analog circuits are used in sensors, audio and video equipment, and radio frequency (RF) communication systems.The design of integrated circuits requires a deep understanding of both digital and analog techniques. Digital circuit designers must be adept at creating complex logic systems that can perform a variety of tasks while minimizing power consumption and maximizing speed. They often use hardware description languages (HDLs) like VHDL or Verilog to model and simulate their designs before fabrication.Analog circuit designers, meanwhile, must contend with issues such as noise, distortion, and signal integrity. They need a strong grasp of physics and materials science to create circuits that can accurately amplify, filter, and convert signals. The designprocess for analog circuits is often more art than science, requiring intuition and experience to achieve the desired performance.The convergence of digital and analog circuit design is most evident in mixed-signal integrated circuits. These chips contain both digital and analog components, allowing them to interact with the digital data processing and the analog real world. Mixed-signal ICs are crucial in applications like mobile phones, where they handle tasks such as digitizing voice signals for transmission and processing digital data from the network.As technology advances, the line between digital and analog circuits continues to blur. Newer design methodologies, such as digitally-assisted analog design, leverage digital components to calibrate and control analog circuits, enhancing their performance and capabilities. Similarly, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are becoming increasingly sophisticated, enabling higher precision and faster speeds.In conclusion, the exploration of digital and analog circuit technologies in integrated circuit design is a dynamic and ever-evolving field. It requires a blend of theoretical knowledge, practical skills, and creative problem-solving. As we push the boundaries of what's possible with electronic devices, the synergy between digital and analog circuits will continue to be a key driver of innovation. This synergy is not just about combining two different technologies; it's about creating a harmonious system that leverages the strengths of each to achieve something greater than the sum of its parts. 。

数字电路面试题Digital Circuit Interview QuestionsIntroduction:In today's technological era, digital circuits serve as the cornerstone of various electronic devices and systems. It is essential for individuals involved in the field of electrical engineering to possess a comprehensive understanding of digital circuits. This article presents a selection of frequently asked interview questions regarding digital circuits, providing insights into key concepts, design methodologies, and problem-solving abilities.Question 1: What is a digital circuit?A digital circuit is a network of interconnected electronic components designed to process digital signals or information in the form of "bits" - binary digits. These circuits utilize logic gates, flip-flops, registers, and other building blocks to perform operations such as arithmetic, logic, and memory functions.Question 2: Differentiate between combinational and sequential logic circuits.Combinational logic circuits generate an output based solely on the current input values. They lack memory elements, ensuring that the output is solely determined by the present inputs. Conversely, sequential logic circuits output not only depend on the present inputs but also on the past inputs and stored information, using memory elements such as flip-flops.Question 3: How can you convert a given logic circuit into its corresponding truth table?To convert a logic circuit into a truth table, one needs to consider all possible input combinations. For each combination, determine the output based on the circuit's logic gates and connections. The resulting truth table will list all possible input combinations alongside their corresponding output values.Question 4: Explain the concept of propagation delay in digital circuits.Propagation delay refers to the time taken for the output of a logic gate to change in response to a change in its input. It is caused by the finite speed of signal transmission within digital circuits due to factors such as gate delays and interconnect lengths. Minimizing propagation delays is crucial to ensure proper circuit operation and timing.Question 5: What is Moore's law, and how does it relate to digital circuits?Moore's law, formulated by Gordon Moore, states that the number of transistors in an integrated circuit doubles approximately every two years. This observation highlights the trend of exponentially increasing computational power and efficiency in digital circuits over time. Integrated circuits incorporating more transistors enable the design and implementation of complex digital systems.Question 6: Describe the concept of clock skew in clock distribution networks.Clock skew refers to the variation in arrival times of clock signals across different components or clock distribution lines within a digital circuit. It can lead to synchronization issues and affect the proper functioning of sequential logic circuits. Minimizing clock skew is crucial to maintain accurate timing and prevent data corruption.Question 7: What are the commonly used design methodologies for digital circuits?Several design methodologies are employed in digital circuit design, including the following:1. RTL (Register Transfer Level) Design: Describing the circuit's behavior using high-level abstractions, focusing on the flow of data between registers.2. Gate-Level Design: Utilizing predefined standard cells and logic gates to implement the circuit's functionality.3. Behavioral Design: Describing the circuit's behavior using programming languages such as VHDL or Verilog to simulate and synthesize the design.4. Physical Design: Involves designing the layout and placement of components, considering factors such as power consumption, noise, and heat dissipation.Question 8: Discuss the concept of hazard in digital circuits.In digital circuits, a hazard refers to a temporary glitch or deviation in the expected output caused by a transition in the input signals. Hazards canoccur due to circuit delays, complex combinational paths, or improper synchronization. Designers must identify and eliminate hazards through techniques such as hazard coverings or hazard-free logic restructuring.Question 9: Explain the advantages and disadvantages of using FPGA (Field-Programmable Gate Array) in digital circuit design.Advantages:1. Versatility: FPGA allows rapid prototyping and design alterations, eliminating the need for fabricating custom integrated circuits.2. Flexibility: Designs can be modified or reprogrammed as required, providing flexibility in adapting to changing requirements.3. Time-to-Market: FPGA-based designs can be developed and deployed quickly, reducing the time required to bring a product or solution to market.4. Cost-Efficiency: FPGA eliminates the high upfront costs associated with ASIC (Application-Specific Integrated Circuit) production.Disadvantages:1. Power Consumption: FPGA can consume more power compared to ASIC, impacting battery-powered devices.2. Limited Scalability: FPGA designs may face limitations in terms of size, complexity, and performance compared to ASIC designs.3. Higher Unit Cost: While FPGA offers cost benefits for low to medium volume production, it may become costlier for high-volume production due to per-unit costs.Question 10: How do you mitigate hazards caused by glitches in digital circuits?To mitigate hazards caused by glitches, designers can employ the following techniques:1. Use Gate Delay Elements: Introduce specialized elements within the circuit to ensure uniform delays and minimize glitches.2. Hazard Covering: Introduce additional logic elements to detect and fix hazards.3. Logic Restructuring: Optimize the circuit's logic gates and structural elements to eliminate or reduce potential hazards.4. Pipeline the Circuit: Introduce pipeline stages to divide the circuit into smaller sections, ensuring proper synchronization and reducing hazards.Conclusion:Digital circuit knowledge and problem-solving skills are crucial for individuals seeking a career in electrical engineering or related fields. By understanding the fundamental concepts, design methodologies, and problem-solving approaches, one can confidently tackle digital circuit interview questions, paving the way for success in this domain. Remember to stay updated with the latest advancements and continuously enhance your skills as digital circuit technology continues to evolve.。

© 2008 © 2008 © 2008© 2008Gated SR Latch(a) Circuit(b) Characteristic table(c) Graphical symbol© 2008 香港中文大學電子工程學系ELE 2120数字电路与系统(d) Timing diagram-Entire control (enable)-As CT indicated-Enable by clock signal-Gated latches with control-Gated RS latches-Outputs as complements-Set (Q=1), reset (Q=0)-Graphical symbolGated SR Latch with NAND Gates © 2008 香港中文大學電子工程學系ELE 2120数字电路与系统SRClkQQ-Clk is gated by NAND gates-S & R inputs are reversed-Fewer transistors than AND gates-Gated SR Latches with NAND: standard(a)Circuit (b)Characteristic table (c) Graphical© 2008 電子工程學系ELE 2120数字电路与系统(a) Circuit(b) Characteristic tablesymbol(d) Timing diagram© 2008 ()Ci it (b)G hi l b l© 2008 電子工程學系ELE 2120数字电路与系统(a) Circuit(b) Graphical symbol (c) Timing diagramFlip-flop denotes a storageelement that changes its © 2008 Level Level--Sensitive vs. Edge Sensitive vs. Edge--Triggered© 2008 香港中文大學電子工程學系ELE 2120数字电路与系统© 2008 © 2008 © 2008 © 2008 © 2008 Positive-Edge-Triggered D Flip-Flop with Clear and Preset© 2008 accomplished by the circuit shown on next page.。

0 1 0 10 1 0 10 1 0 10 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 00 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 10 1 0 1 0 1 0 10 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0Gefran SoftwareProfi leGF_PACK BLOW is Gefran’s solution for complete control of a blowing machine with continuous extrusion or with accumulation head.GF_PACK BLOW provides integrated Parison control for management of production profi le.Parison control means the generation and control of the “tubular preform”, which is the main element of blower production.GF_PACK BLOW is supplied as a software solution in which Gefran has inserted a series of standard preconfi gured functions.The blowing machine control logic and custom functions are programmed by using dedicated confi guration fi les or by working on the programme code.In special cases, or for dedicated confi gurations, you have to use the Gefran Automation Builder (G.A.B.) programming environment.GF_PACK BLOW consists of standard hardware and software modules:• Operator interface with terminals and Gefran Industrial PCs, 10.4”, 12.1” and 15” colour monitors and touch screen • Gefran GILOGIK II I/O modules with digital and analogue inputs and outputs, position sensors • Temperature control modules, Gefran Geflex single loop and multiloop, with on-board SSRs • Series TF machine control keyboardThe GF_PACK BLOW solution contains all typical functions for management of a blowing machine.- Management of single-carriage continuous extrusion blowers - Management of double-carriage continuous extrusion blowers - Management of blowers with accumulation head- Automatic control of extrusion screw speed based on Parison controlgf_pack blow2Functions» Thermoregulation• Max 96 configurable temperature control zones• Division of temperature control zones into groups• Parameterisation and configuration of temperature control loop from dedicated application pages• Distributed temperature control with Geflex controllers• Centralized temperature control with GILOGIK II R-TC8 modules» Parison management• Up to 6 shared or independent Parison profiles• Graphic or tabular configuration of Parison profiles• Up to 300 interpolation points for Parison profile• Graphic display of Parison profile with real values and target values• Refresh of Parison target points < 1ms• Availability of 1 “off-line” profile for test phases with copy, paste or text exchange functions• Configuration of marker points for Parison profile orientation• 3 different interpolation curves available (linear, sinusoidal, stepped)• Configuration of weight on shared or independent Parison profiles• Control of Parison execution in open or closed loop• Selection of divergent or convergent profile control• Max 4 fast intercept points on profile» Machine movement• Proportional control of module movement• Proportional control of carriage movement• Proportional control of nozzle movement• Configuration of movements with position control at braking• Configuration of movements with timed acceleration with linear, quadratic or cosine curve selectionAs default, machine movement control signals are managed with analogue values (-10 / +10 Vdc).For use of drives in Fieldbus (CANopen) connection, reference values can be managed with read/write on the bus.» Other functionalityIn addition to machine control functions, the packet offers:• Recipe management (exportable via USB port)• Trends for temperatures and basic production values• Printing of configurable parameters and pages• Videocamera via Ethernet (Netcam) for real time remote control of system “hot points”• Tele-assistance via modem, Internet and text message• Complete diagnostics of hardware (PLC) with function state and information on version of configured I/O modules• Multilanguages management with UNICODE support (standard Italian and English)• Password level management for access to pages or change of data items • Easy access to system from local and remote by Ethernet (centralisation, diagnostics, upgrade)•Availability of a user setting loggf_pack blow3The following diagram shows a continuous extrusion blowing machine, highlighting its main functions with specific reference to use of devices in the Gefran catalogue.SupplyGF_PACK BLOW is supplied on a DVD, with which you can install the data and information needed to programme a blowing machine line.The installation DVD contains the following:• User manual with information on functions and operation of pages used to manage a blowing machine• Configuration manual with information on source software structure and instructions for possible changes. A list of available data/variables and of standard functions is included• General electrical diagram for connecting the operator panel, I/Os and possible connection in case of distributed temperature control• Graphic utility for guided configuration of structure for passage to various application pages. The utility is also used to configure access levels for page call• Java software for programming user interface pages • Standard machine cycle software developed in IEC1131• Programming software for machine movement, library and system functions To programme and implement special functions, the development PC requires the configuration tools contained in Gefran Automation Builder (G.A.B.).By using the programming languages contained in G.A.B., you can change the standard functions contained in GF_PACK BLOW to adapt them to specific machine needs.The information and data on the DVD to be installed on the development PC are subject to a user license that is inserted with the supply.gf_pack blow4Operator interface based on the following terminals of the GF_VEDO ML CK seriesTechnical DataThe automation architecture required for the GF_PACK BLOW solution calls for:Operator interface based on the following terminals of the GF_VEDO ML seriesModel GF_VEDO ML 104GF_VEDO ML 121GF_VEDO ML 150Type262K TFT colorsDimension10.4”12.1”15”ResolutionSVGA(800x600)SVGA(800x600)XGA(1024x768) Processor Type Geode LX900 / Frequency 600MHz / Core x86Standard2 x Ethernet 10/100 Mbps4 x USB 2.0 Host1 x RS4852 x PS21 x TF keyboardModel GF_VEDO ML 65CK GF_VEDO ML 104CKType262K TFT colors - no touch screenDimension 6.5”10.4”ResolutionVGA(640x480)SVGA(800x600) Processor Type Geode LX900 / Frequency 600MHz / Core x86Standard2 x Ethernet 10/100 Mbps4 x USB 2.0 Host1 x RS4852 x PS21 x TF keyboardgf_pack blow5Operator interface based on the following terminals of the GF_VEDO HL seriesModelGF_VEDO HL 121GF_VEDO HL 150Type 262K TFT colorsDimension 12.1”15”Resolution SVGA (800x600)XGA (1024x768)ProcessorType Intel Pentium Celeron - Intel Celeron Mobile / Frequency 600 - 1500MHzStandard2 x Ethernet 10/100 Mbps2 x USB 1.1 Host 1 x RS4852 x PS21 x TF keyboardMachine movement interface with use of the following optional keyboardsOperator interface based on the following terminals of the GTC seriesModelGTCType 262K TFT colorsDimension 10” / 12.1”Resolution SVGA (800x600)Processor Intel Celeron Mobile / Frequency 600 - 1500MHzStandard1 x Ethernet 10/100 Mbps;2 x USB 1.1 Host; 2 Serial (RS485 - RS232);2 x PS2; 1 x TF keyboard; 1 parallel portTF32-65Combined with GF_VEDO ML 65, requires 32 keys and 32 LEDs confi gured as movementsTF32-104Combined with GF_VEDO ML 104, requires 32 keys and 32 LEDs confi gured as movementsTF48-121Combined with GF_VEDO ML 121, requires 48 keys and 48 LEDs confi gured as movementsTF64-150Combined with GF_VEDO ML 150, requires 64 keys and 64 LEDs confi gured as movementsgf_pack blow6Geflex controllersModel GFX GFXTERMO4GFX4Characteristics1 channel (hot/cold)Solid state relay embedded DIN rail mounting 4 channels (hot/cold)Solid state relay command DIN rail mounting 4 channels (hot/cold)Solid state relay embedded DIN rail mountingGILOGIK II series remote I/O modules with GDNet (Ethernet) connection to operator interfaceCodeR-E16R-U16R-EU16R-A/D8R-D/A4R-D/A8R-MA6R-TC8R-C3Characteristics,Channels number 24Vdc PNP digital inputs 16824Vdc 2APNP digital outputs 16816mA, V analog inputs,potentiometer , strain gauge (16bit)86mA, V analog outputs (16bit)4 - 86Temperature inputs (18bit) (J, K)8Counter inputs1(5KHz)3 (250KHz)All Input / Output signals are optically isolated.gf_pack blow7Distributed solutionGF_VEDOGEFLEXGILOGIK IIModbus RS485Centralized control using R-TC8 modules in the GILOGIK II series, with GDNet (Ethernet) connection to operator interfaceCentralized solutionGF_VEDOGILOGIK IIR-TC8 temperature controlDistributed control using Gefl ex controllers, with serial Modbus connection to operator interfacegf_pack blowGEFRAN spa Via Sebina, 7425050 Provaglio d’Iseo (BS) - ItalyPh. +39 030 9888.1 - Fax +39 030 9839063Email:*******************:Order codeF043302BLOW_CONTOpen application software package for blow-molding continuous machines (single-double).Includes G.A.B. [Gefran Automation Builder], programming environment for PLC and HMI, and 3 days technical training in our headquarter in Provaglio d’Iseo (Italy) (travel and lodgings expenses excluded).DTS_GF_PACK-BLOW_1209_ENG。

交通行业术语（中英文对照）Stop—line--停车线A congested link——阻塞路段Weighting factor——权重因子Controller-- 控制器Emissions Model——排气仿真the traffic pattern-—交通方式Controller-—信号机Amber——黄灯Start-up delay——启动延误Lost time-—损失时间Off—peak——非高峰期The morning peak——早高峰Pedestrian crossing——人行横道Coordinated control systems——协调控制系统On—line——实时Two—way—-双向交通Absolute Offset-—绝对相位差Overlapping Phase——搭接相位Critical Phase——关键相位Change Interval——绿灯间隔时间Flow Ratio——流量比Arterial Intersection Control 干线信号协调控制Fixed-time Control——固定式信号控制Real-time Adaptive Traffic Control——实时自适应信号控制Green Ratio-—绿信比Through movement——直行车流Congestion——阻塞,拥挤The percentage congestion——阻塞率The degree of saturation——饱和度The effective green time——有效绿灯时间The maximum queue value——最大排队长度Flow Profiles——车流图示Double cycling—-双周期Single cycling-—单周期Peak—-高峰期The evening peak periods——晚高峰Siemens——西门子Pelican—-人行横道Fixed time plans-- 固定配时方案One—way traffic—-单向交通Green Ratio-—绿信比Relative Offset--相对相位差Non-overlapping Phase——非搭接相位Critical Movement-—关键车流Saturation Flow Rate——饱和流率Isolated Intersection Control——单点信号控制（点控）Area—wide Control——区域信号协调控制Vehicle Actuated （V A)——感应式信号控制The Minimum Green Time—-最小绿灯时间Unit Extension Time——单位绿灯延长时间The Maximum Green Time——最大绿灯时间Opposing traffic——对向交通（车流）Actuation—-Control——感应控制方式Pre-timed Control——定周期控制方式Remote Control——有缆线控方式Self－Inductfanse——环形线圈检测器Signal—- spacing-—信号间距Though-traffic lane-—直行车道Inbound—-正向Outbound—-反向第一章交通工程—— Traffic Engineering运输工程—- Transportation Engineering铁路交通—- Rail Transportation航空交通—- Air Transportation水上交通-— Water Transportation管道交通—— Pipeline Transportation交通系统-— Traffic System交通特性—— Traffic Characteristics人的特性-— Human Characteristics车辆特性—— Vehicular Characteristics交通流特性-— Traffic Flow Characteristics道路特性—— Roadway Characteristics交通调查-— Traffic Survey交通流理论—— Traffic Flow Theory交通管理-— Traffic Management交通环境保护-—Traffic Environment Protection 交通设计—— Traffic Design交通统计学-— Traffic Statistics交通心理学—— Traffic Psychology汽车力学—— Automobile Mechanics交通经济学—— Traffic Economics汽车工程—— Automobile Engineering人类工程—- Human Engineering环境工程—— Environment Engineering自动控制—— Automatic Control应用数学-— Applied Mathematics电子计算机-— Electric Computer第二章公共汽车—- Bus无轨电车—- Trolley Bus有轨电车-— Tram Car大客车—— Coach小轿车—— Sedan载货卡车—- Truck拖挂车—— Trailer平板车—— Flat—bed Truck动力特性—— Driving Force Characteristics牵引力-— Tractive Force空气阻力—— Air Resistance滚动阻力—— Rolling Resistance坡度阻力-- Grade Resistance加速阻力—- Acceleration Resistance附着力-- Adhesive Force汽车的制动力-— Braking of Motor Vehicle自行车流特性—— Bicycle flow Characteristics 驾驶员特性—— Driver Characteristics刺激-- Stimulation感觉-— Sense判断—— Judgment行动—— Action视觉—— Visual Sense听觉—— Hearing Sense嗅觉—- Sense of Smell味觉—— Sense of Touch视觉特性—— Visual Characteristics视力—— Vision视野-— Field of Vision色彩感觉-— Color Sense眩目时的视力—- Glare Vision视力恢复—— Return Time of Vision动视力—— Visual in Motion亮度—— Luminance照度-— Luminance反应特性—— Reactive Characteristics刺激信息-- Stimulant Information驾驶员疲劳与兴奋—— Driving Fating and Excitability 交通量—— Traffic V olume交通密度—— Traffic Density地点车速—— Spot Speed瞬时车速—— Instantaneous Speed时间平均车速—— Time mean Speed空间平均车速—— Space mean speed车头时距—- Time headway车头间距-— Space headway0交通流模型-— Traffic flow model自由行驶车速-— Free flow speed阻塞密度—— Jam density速度－密度曲线—— Speed—density curve 流量－密度曲线—- Flow—density curve最佳密度—— Optimum concentration流量-—速度曲线—— Flow—speed curve最佳速度—— Optimum speed连续流—— Uninterrupted traffic间断流—- Interrupted traffic第三章交通调查分析—— Traffic survey and analysis 交通流调查—— Traffic volume survey车速调查-- Speed survey通行能力调查—- Capacity survey车辆耗油调查—— Energy Consumption Survey居民出行调查—— Trip Survey车辆出行调查-- Vehicle Trip Survey停车场调查—- Parking Area Survey交通事故调查—— Traffic Accident Survey交通噪声调查—- Traffic Noise Survey车辆废气调查—— Vehicle Emission Survey平均日交通量—— Average Daily Traffic(ADT)周平均日交通量—— Week Average Daily Traffic月平均日交通量—— Month Average Daily Traffic年平均日交通量—— Annual Average Daily Traffic高峰小时交通量—— Peak hour V olume年最大小时交通量—-Highest Annual Hourly V olume年第30位最高小时交通量——Thirtieth Highest Annual Hourly V olume 高峰小时比率—— Peak Ratio时间变化—— Time Variation空间变化-— Spatial Variation样本选择—- Selection Sample样本大小-- Size of Sample自由度—- Freedom车速分布—— Speed Distribution组中值—— Mid-Class Mark累计频率—— Cumulative Frequency频率分布直方图——Frequency Distribution Histogram85%位车速-— 85% Percentile Speed限制车速-— Regulation Speed服务水平—- Level of Service牌照对号法-— License Number Matching Method跟车测速-- Car Following Method浮动车测速法—-Moving Observer Speed Method通行能力调查—— Capacity Studies饱和流量—— Saturation Flow第四章泊松分布—— Poisson Distribution交通特性的统计分布——Statistical Distribution of Traffic Characteristics驾驶员处理信息的特性Driver Information Processing Characteristics 跟车理论—- Car Following Theory交通流模拟-- Simulation of Traffic Flow间隔分布—— Interval Distribution二项分布—— Binomial Distribution拟合—— Fitting移位负指数分布—— Shifted Exponential Distribution排队论—— Queuing Theory运筹学—— Operations Research加速骚扰-— Acceleration Noise停车波—— Stopping Wave起动波—- Starting Wave第五章城市交通规划—— Urban Traffic Planning土地利用—— Land—Use可达性-— Accessibility起讫点调查—— Origin –Destination Survey出行端点—— Trip End期望线—- Desire Line主流倾向线—— Major Directional Desire Line 调查区境界线—— Cordon Line分隔查核线-— Screen Line样本量-- Sample Size出行发生-- Trip Generation出行产生—- Trip Production出行吸引—— Trip Attraction发生率法—— Generation Rate Method回归发生模型—— Regression Generation Model 类型发生模型—— Category Generation Model 出行分布—— Trip Distribution现在型式法-- Present Pattern Method重力模型法—— Gravity Model Method行程时间模型-- Travel Time Model相互影响模型—- Interactive Model分布系数模型-— Distribution Factor Model交通方式划分—— Model Split ，Mode Choice转移曲线—— Diversion Curve交通量分配—— Traffic Assignment最短路径分配（全有全无) Shortest Path Assignment(All-or—Nothing）多路线概率分配Probabilistic Multi—Route Assignment线权-— Link Weight点权—— Point Weight费用——效益分析-— Cost –benefit Analysis现值法—— Present Value Method第六章交通安全—— Traffic Safety交通事故—— Traffic Accident交通死亡事故率-— Traffic Fatal-Accident Rate交通法规—- Traffic Law多发事故地点—— High accident Location交通条例-— Traffic Regulation交通监视-— Traffic Surveillance事故报告—— Accident Report冲撞形式—— Collision Manner财产损失—— Property Damage事故档案—- Accident File事故报表—— Accident Inventory固定目标—— Fixed Object事故率—- Accident Ratelxy事故数法——Accident Number Method质量控制法——Quality Control Method人行横道-—Pedestrian Crosswalk行人过街道信号-—Pedestrian Crossing Beacon人行天桥——Passenger Foot—Bridge人行地道——Passenger Subway栅栏-—Gate立体交叉——Underpass(Overpass)标线——Marking无信号控制交叉口--Uncontrolled Intersection让路标志——Yield Sign停车标志——Stop Sign渠化交通—-Channelization traffic 单向交通——One-Way 禁止转弯—-No Turn Regulation 禁止进入——No—Entry 禁止超车——Prohibitory Overtaking 禁止停车——Prohibitory Parking 禁止通行——Road Closed 安全带--Life Belt第七章交通控制与管理——Traffic Control and Management 交通信号—-Traffic Signal 单点定时信号-—Isolated Pre-timed Signal 信号相位——Signal Phase 周期长度——Cycle Length 绿信比--Split 优先控制-—Priority Control 延误—-Delay 流量比——Flow Ratio 有效绿灯时间—-Effective Green Time 损失时间——Loss Time 绿灯间隔时间—-Intergreen Interval 信号配时——Signal Timing (or Signal Setting) 交通感应信号——Traffic Actuated Signal 城市交通控制系统——Urban Traffic Control System 联动控制-—Coordinated Control 区域控制——Area Control 时差—— Offset同时联动控制——Simultaneous Coordinated Control交变联动控制—— Alternate Coordinated Control绿波带——Green Wave连续通行联动控制-— Progressive Coordinated Control中心控制器—— Master Controller局部控制器—— Local——Controller实时-- Real Time联机—— On-line脱机-— Off-line爬山法--Hill—Climbing“小型高效”区域控制系统——Compact Urban Traffic Control System 道路控制系统—— Corridor Control System交通仿真—— Traffic Simulation时间扫描法—- Time Scanning事件扫描法—- Event Scanning。

英语作文-揭秘集成电路设计中的时钟与数据恢复技术与应用In the realm of integrated circuit (IC) design, the interplay between clocking and data recovery techniques is pivotal. These elements form the backbone of synchronous digital systems, ensuring that data is transmitted and processed reliably and efficiently.Clocking in IC design refers to the use of a clock signal to coordinate the timing of circuit operations. This clock signal, typically generated by an oscillator, serves as a heartbeat for the system, synchronizing the activities of various components. The precision of this clock signal is crucial, as it determines the system's maximum operating speed and influences its susceptibility to timing-related errors.Data recovery, on the other hand, is the process of accurately extracting data from a noisy or distorted signal. In high-speed communication systems, data recovery circuits, often referred to as Clock and Data Recovery (CDR) circuits, are essential. They recover the timing information (clock) from the incoming data stream and use it to regenerate a clean version of the data, free from transmission-induced imperfections.The integration of clocking and data recovery technologies is especially significant in serial communication protocols such as PCI Express, USB, and SATA. These protocols rely on high-speed serial links, where data is sent one bit at a time over a single channel. The absence of a separate clock line necessitates the use of sophisticated CDR circuits to extract timing information from the serial data itself.One of the key challenges in designing CDR circuits is dealing with jitter, which is the deviation from true periodicity of a presumed periodic signal. Jitter can be introduced by a variety of sources, including thermal noise, power supply variations, and electromagnetic interference. Effective CDR circuits must be able to tolerate a certain amount of jitter while still recovering the original data accurately.Another aspect of clocking in IC design is the distribution of the clock signal throughout the chip. As ICs become more complex and operate at higher speeds, the challenge of delivering a consistent clock signal to all parts of the chip increases. Techniques such as clock tree synthesis and the use of phase-locked loops (PLLs) are employed to mitigate issues like clock skew, which is the difference in timing of the clock signal's arrival at different parts of the circuit.In conclusion, the synergy between clocking and data recovery techniques is a cornerstone of modern IC design. It enables the creation of systems that are not only fast and powerful but also resilient to the imperfections inherent in electronic communication. As technology marches forward, the evolution of these techniques will continue to be a critical area of research and development, pushing the boundaries of what is possible in the world of electronics. 。