IS93C46B-3GI中文资料

gc0403 规格书英文回答：The GC0403 is a 1/4-inch CMOS digital image sensor witha resolution of 1280 x 1024 pixels. It has a sensitivity of1.0 V/lux-sec and a dynamic range of 70 dB. The GC0403 is available in a variety of package options, including LGA, QFN, and CSP.Here are some of the key features of the GC0403:1/4-inch CMOS digital image sensor.Resolution: 1280 x 1024 pixels.Sensitivity: 1.0 V/lux-sec.Dynamic range: 70 dB.Available in a variety of package options.The GC0403 is a versatile image sensor that can be used in a variety of applications, including:Security cameras.Surveillance cameras.Automotive cameras.Medical imaging.Industrial inspection.中文回答：GC0403 是一款 1/4 英寸 CMOS 数码图像传感器，分辨率为1280 x 1024 像素。

它的灵敏度为 1.0 V/lux-sec，动态范围为 70 dB。

GC0403 有多种封装选项，包括 LGA、QFN 和 CSP。

以下是 GC0403 的一些主要特性：1/4 英寸 CMOS 数码图像传感器。

SEMiX ®4sTrench IGBT ModulesSEMiX604GB176HDsFeatures•Homogeneous Si•Trench = Trenchgate technology •V CE(sat) with positive temperature coefficient•UL recognised file no. E63532Typical Applications*•AC inverter drives •UPS•Electronic weldersAbsolute Maximum Ratings SymbolConditions Values UnitIGBT V CES 1700V I C T j =150°CT c =25°C 567A T c =80°C402A I Cnom 400A I CRMI CRM = 2xI Cnom 800A V GES -20...20V t psc V CC =1000V V GE ≤ 20V V CES ≤ 1700VT j =125°C10µs T j-55...150°C Inverse diode I F T j =150°CT c =25°C 740A T c =80°C 496A I Fnom400A I FRM I FRM = 2xI Fnom800A I FSM t p =10ms, sin 180°, T j =25°C2700A T j -40 (150)°C Module I t(RMS)T terminal =80°C600A T stg -40...125°C V isolAC sinus 50Hz, t =1min4000VCharacteristics SymbolConditions min.typ.max.UnitIGBT V CE(sat)I C =400A V GE =15V chiplevelT j =25°C 2 2.45V T j =125°C 2.5 2.9V V CE0T j =25°C 1 1.2V T j =125°C0.9 1.1V r CE V GE =15VT j =25°C 2.5 3.1m ΩT j =125°C3.94.5m ΩV GE(th)V GE =V CE , I C =16mA5.25.86.4V I CES V GE =0V V CE =1700V T j =25°C 0.124mA T j =125°C mA C ies V CE =25V V GE =0Vf =1MHz 35.3nF C oes f =1MHz 1.46nF C res f =1MHz1.17nF Q G V GE =- 8 V...+ 15 V 3732nC R Gint T j =25°C 1.88Ωt d(on)V CC =1200V I C =400A V GE =±15V R G on =3ΩR G off =3ΩT j =125°C 360ns t r T j =125°C 65ns E on T j =125°C 215mJ t d(off)T j =125°C 900ns t f T j =125°C 165ns E off T j =125°C165mJ R th(j-c)per IGBT 0.058K/WCharacteristics SymbolConditionsmin.typ.max.UnitInverse diodeV F = V EC I F =400AV GE =0V chipT j =25°C 1.5 1.70V T j =125°C 1.4 1.6V V F0T j =25°C 0.9 1.1 1.3V T j =125°C0.70.9 1.1V r FT j =25°C 1.0 1.0 1.0m ΩT j =125°C1.31.3 1.3m ΩI RRM I F =400A di/dt off =6600A/µs V GE =-15VV CC =1200VT j =125°C 560A Q rr T j=125°C131µC E rr T j =125°C 95mJR th(j-c)per diode0.081K/WModule L CE 22nH R CC'+EE'res., terminal-chip T C =25°C 0.7m ΩT C =125°C1m ΩR th(c-s)per module 0.03K/W M s to heat sink (M5)35Nm M tto terminals (M6)2.55Nm Nmw400gTemperatur Sensor R 100T c =100°C (R 25=5 k Ω)493 ± 5%ΩB 100/125R (T)=R 100exp[B 100/125(1/T-1/T 100)]; T[K];3550 ±2%K SEMiX ® 4sTrench IGBT ModulesSEMiX604GB176HDsFeatures•Homogeneous Si•Trench = Trenchgate technology •V CE(sat) with positive temperature coefficient•UL recognised file no. E63532Typical Applications*•AC inverter drives •UPS•Electronic weldersFig. 1: Typ. output characteristic, inclusive R CC'+ EE'Fig. 2: Rated current vs. temperature I C = f (T C )Fig. 3: Typ. turn-on /-off energy = f (I C )Fig. 4: Typ. turn-on /-off energy = f (R G )Fig. 5: Typ. transfer characteristic Fig. 6: Typ. gate charge characteristicFig. 7: Typ. switching times vs. I C Fig. 8: Typ. switching times vs. gate resistor R GFig. 9: Typ. transient thermal impedance Fig. 10: Typ. CAL diode forward charact., incl. R CC'+EE'Fig. 11: Typ. CAL diode peak reverse recovery current Fig. 12: Typ. CAL diode recovery chargeThis is an electrostatic discharge sensitive device (ESDS), international standard IEC 60747-1, Chapter IX* The specifications of our components may not be considered as an assurance of component characteristics. Components have to be tested for the respective application. Adjustments may be necessary. The use of SEMIKRON products in life support appliances and systems is subject to prior specification and written approval by SEMIKRON. We therefore strongly recommend prior consultation of our staff.spring configuration。

®Product Specification 03370(RevisionJ, 11/2022)ProTech ‐GIIOverspeed Protection Device(Triple Modular Redundant)DescriptionThe ProTech-GII is an overspeed safety device designed to safely shut down steam, gas, and hydro turbines of all sizes upon sensing an overspeed or over-acceleration event. This device accurately monitors turbine rotor speed and acceleration via active or passive magnetic pickups (MPUs) and issues ashutdown command to the turbine’s trip valve(s) or corresponding trip system. Depending on the system design, the ProTech-GII can be purchased with two dual-redundant trip relay outputs using a 2-out-of-3 voted architecture, or with three independent non-voted trip relay outputs. Individual alarm relays, 4–20 mA speed readouts, and Modbus ® * communications make this overspeed device easy to integrate into any turbine safety system.*—Modbus is a trademark of Schneider Automation Inc.The ProTech-GII is available in flush-mount models designed to be installed within a standard 24” (610 mm) cabinet front door, or models designed to be bulkhead mounted on a wall or skid near the turbine set. Designed for harsh environments when installed within an enclosure, this device has an ingress protection rating of IP56 (protected against dust and completely protected against jets of water of similar force to heavy seas).Designed for high reliability, each ProTech-GII module (A, B, C), depending on the purchased model, accepts two high-voltage power inputs (90–240 Vac / 100–150 Vdc) or one high-voltage power input (90–240 Vac / 100–150 Vdc) and one low-voltage power input (18–32 Vdc). This design works on a high-signal-select basis, allowing the unit to fully operate with either or both power sources available.ApplicationsThe ProTech-GII is designed to safely shut down steam, gas, and hydro turbines upon sensing a turbine overspeed or over-acceleration event. The device’s 12 millisecond response time and 0.5 to 80 000 rpm speed range make it ideal for application on all types and sizes of turbines.∙ IEC61508 SIL-3Certified ∙ API670 & API612Compliant ∙ 2-out-of-3 voting ∙ High availability(TMR) ∙ Accelerationprotection ∙ On-line testing ∙ On-line repair ∙ Overspeed tripand test logs ∙ Modbuscommunications ∙ Password securityprotection ∙ 12 millisecondresponse time (independent voted output models) ∙ Internal frequencygenerator ∙ Optional Ethernetcommunication gatewayReleasedThe ProTech-GII models with two dual-redundant relay outputs are design to be applied with simplex or dual-redundant trip block assemblies or trip systems. The ProTech-GII models with three independent non-voted output models are designed to be applied with special turbine trip block assemblies that perform the 2-out-of-3 voting within their design.This fast acting overspeed protection device is designed to be applied in conjunction with a turbine control or trip system to safely shut down the turbine. Interface with related control systems or plant Distributed Control Systems (DCSs) can be performed via the ProTech-GII’s redundant hard-wired input and output signals or through its triple-redundant serial Modbus communications ports. Optionally, Ethernet gateways can be purchased to easily interface with plant Ethernet networks.Certified as an IEC61508 SIL-3 (Safety Integrity Level Three) safety device, the ProTech-GII can easily be applied within an IEC61508 or IEC61511 based safety system. A thorough product manual is provided to instruct users on how to apply the ProTech-GII to meet IEC based requirements.Designed for system-critical applications, the ProTech-GII’s triple-modular architecture coupled with its on-line testing and on-line repair capabilities give it one of the highest availability and reliability ratings in the industry. FunctionalityOn-line Testing—Each ProTech-GII module can be tested manually from the module’s front panel, Modbus communications port, or automatically via its auto-test routine function. The ProTech-GII allows users to configure an overspeed test to be performed automatically on a periodic basis, testing each module (A, B, C) one at a time, and logging the result of each test or halting the test for a sensed error.On-line Repair—The ProTech-GII’s triple-modular design allows users to easily replace one of its modules (A, B, C) while the turbine is on-line and operating normally. Ease of replacement is enhanced by the unit’s backplane plug-and-operate structure, and its module-to-module learning function.Trip, Alarm, & Overspeed Logs—The ProTech-GII log function logs (saves to memory) all trips, alarms, trip valve response times, and overspeed events. The trip-log function uses a scrolling buffer and records the last 50 sensed trip or alarm events and the last 20 overspeed events to memory, with associated times. Each log file can be viewed from the unit’s front panel, or downloaded to a computer via the ProTech-GII service tool program. Each module utilizes non-volatile memory to ensure that all logged events are saved, even on loss of power.Real Time Clock—Each ProTech-GII module utilizes a real-time clock to ensure accurate time logging. A special time-averaging function is utilized between modules to ensure module-to-module clock synchronization.FeaturesAcceleration Detection—Optionally, the ProTech-GII can also be configured to protect a turbine from high acceleration events. The derivative of the speed signal is used to detect turbine acceleration and issue an associated trip command. MPU Detection—Each module’s speed sensor input uses special MPU open-wire detection circuitry to validate that the MPU is properly connected before turbine operation, and special loss-of-speed detection logic to validate MPU functionality during turbine operation.Automatic Overspeed Test Routine—Optionally, the ProTech-GII can be configured to routinely perform an overspeed test of each module, then log and report the test results. With this test routine, each module goes through its test sequence using an internal frequency generator to simulate an overspeed condition.Sulfur Contamination Resistant—The ProTech-GII utilizes a special conformal coating material that has demonstrated excellent long-term protection against H2S and SO2 gases at levels classified in international standard IEC 721-3-3 1994 - environment Class 3C2.ConfigurabilityThe ProTech-GII can be configured (programmed) through its front-panel keypad or via a software service tool operating on a site computer or laptop. For ease of use, all configuration settings, alarm/trip and overspeed logs are viewable via each module’s high-resolution 4.2” (107 mm) color display. A special module-to-module learning function can be utilized to reduce configuration time and mistakes. Different levels of password security are utilized to protect unit configuration settings as well as limit access to device test functions.Installation Information∙Approximate dimensions, including faceplate: 330 x 445 x 159 mm (13 x 17.5 x 6.25”).∙Depending on part number ordered, designed to be bulkhead mounted on a wall or skid, or flush-mounted vertically within a panel or cabinet.∙Rated for IP56 (ingress protection level 5-6) based locations.∙Operating / storage temperature range: –20 to +60 °C.Input SignalsPower Source (two redundant)∙High voltage power supply (88–264 Vac/47–63 Hz; 90–150 Vdc) @ 90 W∙Low voltage power supply (18–32 Vdc) @ 100 WSpeed Signals (1/module, three total)Inputs can be configurable to accept signals from:∙MPUs (100–32 000 Hz) @ (1–35 Vrms)∙Proximity probes (0.5–25 000 Hz) @ 24 Vdc∙Gear tooth range (1–320 teeth)Discrete Inputs (3/module, nine total)∙Alarm/trip reset commandcommand∙ Start∙Speed fail override commandOutput SignalsDiscrete Output RelaysVoted Relay Models∙Shutdown relay output (2 total, 2-out-of-3 voted)o Rated for 8 A @ 220 Vac or 8 A @ 24 Vdc∙Alarm relay output (1/module, 3 total)o Rated for 2 A @ 24 Vdc4–20 mA Analog Output (1/module, 3 total)∙Dedicated to function as a speed meter readoutCommunication Ports (1/module, 3 total)∙Serial RS-232, RS-422, RS-485 Modbus portRegulatory ComplianceNorth American Compliance:∙CSA certified for Class I, Division 2, Groups A, B, C, and D, T4 at 60 °C ambient for use in Canada and the United States.European Compliance:∙EMC Directive: 2014/30/EU∙ATEX Directive: 2014/34/EU, II 3 G, Ex ec nC IIC T4 Gc (-20°C ≤ Tamb ≤ +60°C)∙LVD Directive : 2014/35/EU2011/65/EU∙ RoHS:Woodward turbomachinery systems products are intended exclusively for sale and use only as a part of Large ScaleFixed Installations per the meaning of Art.2.4(e) of directive 2011/65/EU. This fulfills the requirements stated in Art.2.4(c), and as such, the product is excluded from the scope of RoHS2.UKCA Compliance:Regulations 2016 : S.I. 2016 No. 1091∙ ElectromagneticCompatibility∙Equipment and Protective Systems Intended for use in Potentially Explosive Atmospheres Regulations 2016 : S.I. 2016 No. 1107 as II 3 G, Ex ec nC IIC T4 Gc (-20°C ≤ Tamb ≤ +60°C)∙The Electrical Equipment (Safety) Regulations 2016 : S.I. 2016 No. 1101Other International Compliance:∙IECEx: Certified for use in explosive atmospheres per IECEx Certificate TUR 21.0042X as Ex ec nC IIC T4 Gc (-20°C ≤Tamb ≤ +60°C)∙SIL: TÜV certified for SIL-3 per IEC 61508 Parts 1-7∙RCM (Australia & New Zealand): Compliance is limited to application for those units bearing the Regulatory Compliance Mark (RCM). Only EMC is applicable in virtually all Woodward intended applications.∙IEC60068-2-60:1995 Part 2.60 Methods 1 and 4 (conformal coating)∙API670 & API612 compliantMPU or ProxReset Start OverrideTrip Relay Output 1Output 2Single Module Functional Diagram2-out-of-3 Voted Application DiagramIndependent Voted Application DiagramFor more information contact:1041 Woodward Way, Fort Collins CO 80524Tel.: +1 (970) 482-5811Distributors & ServiceWoodward has an international network of distributors and service facilities.For your nearest representative, call the Fort Collins plant or see theWorldwide Directory on our website.This document is distributed for informational purposes only. It is not to be construed ascreating or becoming part of any Woodward contractual or warranty obligation unlessexpressly stated in a written sales contract.Copyright © Woodward 2009–2022, All Rights Reserved。

FEATURES•Single supply with operation down to 2.5V •Low power CMOS technology - 1 mA active current (typical)- 1 µ A standby current (maximum)•128 x 8 bit organization (93LC46A)•64 x 16 bit organization (93LC46B)•Self-timed ERASE and WRITE cycles (including auto-erase)•Automatic ERAL before WRAL•Power on/off data protection circuitry •Industry standard 3-wire serial interface•Device status signal during ERASE/WRITE cycles •Sequential READ function•1,000,000 E/W cycles guaranteed •Data retention > 200 years•8-pin PDIP/SOIC and 8-pin TSSOP packages •Available for the following temperature ranges: DESCRIPTIONThe Microchip T echnology Inc. 93LC46AX/BX are 1K-bit, low voltage serial Electrically Erasable PROMs. The device memory is configured as x8 (93LC46A) or x16 bits (93LC46B). Advanced CMOS technology makes these devices ideal for low power nonvolatile memory applications. The 93LC46AX/BX is available in standard 8-pin DIP , 8-pin surface mount SOIC, and TSSOP packages. The 93LC46AX/BX are offered only in a 150-mil SOIC package.-Commercial (C):0 ° C to +70 ° C -Industrial (I): -40 ° C to +85 °C元器件交易网93LC46A/B1.0ELECTRICALCHARACTERISTICS1.1Maximum Ratings* Vcc...................................................................................7.0V All inputs and outputs w.r.t. Vss ................-0.6V to Vcc +1.0V Storage temperature.....................................-65°C to +150°C Ambient temp. with power applied.................-65°C to +125°C Soldering temperature of leads (10 seconds).............+300°C ESD protection on all pins................................................4 kV*Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri-ods may affect device reliability.TABLE 1-1PIN FUNCTION TABLE Name FunctionCS Chip SelectCLK Serial Data ClockDI Serial Data InputDO Serial Data OutputV SS GroundNC No ConnectV CC Power SupplyTABLE 1-2DC AND AC ELECTRICAL CHARACTERISTICSAll parameters apply over the specified operating ranges unless otherwise noted Commercial (C): V CC = +2.5V to +6.0V Tamb = 0°C to +70°C Industrial (I):V CC = +2.5V to +6.0V Tamb = -40°C to +85°CParameter Symbol Min.Max.Units ConditionsHigh level input voltage V IH1 2.0Vcc +1V 2.7V < V CC≤ 5.5V (Note 2) V IH20.7 V CC Vcc +1V V CC < 2.7VLow level input voltage V IL1-0.30.8V V CC > 2.7V (Note 2) V IL2-0.30.2 Vcc V V CC < 2.7VLow level output voltage V OL1—0.4V I OL = 2.1 mA; Vcc = 4.5VV OL2—0.2V I OL =100 µA; Vcc = Vcc Min.High level output voltage V OH1 2.4—V I OH = -400 µA; Vcc = 4.5VV OH2V CC-0.2—V I OH = -100 µA; Vcc = Vcc Min.Input leakage current I LI-1010µA V IN = V SS to Vcc Output leakage current I LO-1010µA V OUT = V SS to VccPin capacitance (all inputs/outputs)C IN, C OUT—7pFV IN/V OUT = 0 V (Notes 1 & 2)Tamb = +25°C, F CLK = 1 MHzOperating current I CC write— 1.5mAI CC read— 1500mAµAF CLK = 2 MHz; Vcc = 6.0VF CLK = 1 MHz; Vcc = 3.0VStandby current I CCS—1µA CS = VssClock frequency F CLK—21MHzMHzV CC > 4.5VV CC < 4.5VClock high time T CKH250—nsClock low time T CKL250—nsChip select setup time T CSS50—ns Relative to CLK Chip select hold time T CSH0—ns Relative to CLK Chip select low time T CSL250—nsData input setup time T DIS100—ns Relative to CLK Data input hold time T DIH100—ns Relative to CLK Data output delay time T PD—400ns C L = 100 pFData output disable time T CZ—100ns C L = 100 pF (Note 2) Status valid time T SV—500ns C L = 100 pFProgram cycle time T WC—6ms ERASE/WRITE mode T EC—6ms ERAL modeT WL—15ms WRAL modeEndurance—1M—cycles25°C, V CC = 5.0V, Block Mode (Note 3)Note 1:This parameter is tested at T amb = 25°C and Fclk = 1 MHz.2:This parameter is periodically sampled and not 100% tested.3:This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which may be obtained on Microchip’s BBS or website.元器件交易网93LC46A/B2.0PIN DESCRIPTION2.1Chip Select (CS)A high level selects the device; a low level deselects the device and forces it into standby mode. However, a pro-gramming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the pro-gramming cycle is completed.CS must be low for 250 ns minimum (T CSL) between consecutive instructions. If CS is low, the internal con-trol logic is held in a RESET status.2.2Serial Clock (CLK)The Serial Clock is used to synchronize the communi-cation between a master device and the 93LC46AX/ BX. Opcodes, address, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK.CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (T CKH) and clock low time (T CKL). This gives the controlling master freedom in preparing opcode, address, and data.CLK is a “Don't Care” if CS is low (device deselected). If CS is high, but the START condition has not been detected, any number of clock cycles can be received by the device without changing its status (i.e., waiting for a ST ART condition).CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle.After detection of a ST ART condition the specified num-ber of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address, and data bits before an instruction is executed (T able 2-1 and T able 2-2). CLK and DI then become don't care inputs waiting for a new ST ART condition to be detected.2.3Data In (DI)Data In (DI) is used to clock in a ST ART bit, opcode, address, and data synchronously with the CLK input.2.4Data Out (DO)Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (T PD after the posi-tive edge of CLK).This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY sta-tus information is available on the DO pin if CS is brought high after being low for minimum chip select low time (T CSL) and an ERASE or WRITE operation has been initiated.The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready.TABLE 2-1INSTRUCTION SET FOR 93LC46AInstruction SB Opcode Address Data In Data Out Req. CLK CyclesERASE111A6A5A4A3A2A1A0—(RDY/BSY)10ERAL10010X X X X X—(RDY/BSY)10EWDS10000X X X X X—HIGH-Z10EWEN10011X X X X X—HIGH-Z10READ110A6A5A4A3A2A1A0—D7 - D018WRITE101A6A5A4A3A2A1A0D7 - D0(RDY/BSY)18WRAL10001X X X X X D7 - D0(RDY/BSY)18 TABLE 2-2INSTRUCTION SET FOR 93LC46BInstruction SB Opcode Address Data In Data Out Req. CLK CyclesERASE111A5A4A3A2A1A0—(RDY/BSY)9ERAL10010X X X X—(RDY/BSY)9EWDS10000X X X X—HIGH-Z9EWEN10011X X X X—HIGH-Z9READ110A5A4A3A2A1A0—D15 - D025WRITE101A5A4A3A2A1A0D15 - D0(RDY/BSY)25WRAL10001X X X X D15 - D0(RDY/BSY)25元器件交易网93LC46A/B3.0FUNCTIONAL DESCRIPTION Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS.3.1START ConditionThe ST ART bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time.Before a ST ART condition is detected, CS, CLK, and DI may change in any combination (except to that of a ST ART condition), without resulting in any device oper-ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, and WRAL). As soon as CS is high, the device is no longer in the standby mode.An instruction following a START condition will only be executed if the required amount of opcodes, addresses, and data bits for any particular instruction is clocked in.After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new ST ART condition is detected.3.2Data In (DI) and Data Out (DO)It is possible to connect the Data In (DI) and Data Out (DO) pins together. However, with this configuration, if A0 is a logic-high level, it is possible for a “bus conflict”to occur during the “dummy zero” that precedes the READ operation. Under such a condition the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driv-ing A0. The higher the current sourcing capability of A0, the higher the voltage at the DO pin.3.3Data ProtectionDuring power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 2.2V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 2.2V at nominal conditions.The ERASE/WRITE Disable (EWDS) and ERASE/ WRITE Enable (EWDS) commands give additional pro-tection against accidentally programming during nor-mal operation.After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.元器件交易网93LC46A/B3.4ERASEThe ERASE instruction forces all data bits of the spec-ified address to the logical “1” state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle.The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (T CSL). DO at logical “0” indicates that program-ming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction.3.5Erase All (ERAL)The Erase All (ERAL) instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle.The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (T CSL) and before the entire ERAL cycle is com-plete.元器件交易网93LC46A/B3.6ERASE/WRITE Disable and Enable(EWDS/EWEN)The 93LC46A/B powers up in the ERASE/WRITE Dis-able (EWDS) state. All programming modes must be preceded by an ERASE/WRITE Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruc-tion is executed or Vcc is removed from the device. T o protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow all programming opera-tions. Execution of a READ instruction is independent of both the EWEN and EWDS instructions.3.7READThe READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (93LC46A) or 16-bit (93LC46B) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (T PD). Sequential read is possible when CS is held high. The memory data will automati-cally cycle to the next register and output sequentially.FIGURE 3-6:READ TIMING CSCLKDI DO110An•••A0HIGH-Z0Dx•••D0Dx•••D0•••Dx D0元器件交易网93LC46A/B3.8WRITEThe WRITE instruction is followed by 8 bits (93LC46A) or 16 bits (93LC46B) of data which are written into the specified address. After the last data bit is put on the DI pin, the falling edge of CS initiates the self-timed auto-erase and programming cycle.The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (T CSL) and before the entire write cycle is complete. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written with the data specified and the device is ready for another instruc-tion.3.9Write All (WRAL)The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and com-mences at the falling edge of the CS. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction but the chip must be in the EWEN status.The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (T CSL).元器件交易网元器件交易网93LC46A/B Array NOTES:元器件交易网93LC46A/B Array NOTES:元器件交易网93LC46A/B Array NOTES:93LC46A/B93LC46A/B PRODUCT IDENTIFICATION SYSTEMSales and SupportData SheetsProducts supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1. Y our local Microchip sales office.2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).元器件交易网AMERICASCorporate OfficeMicrochip Technology Inc.2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: AtlantaMicrochip T echnology Inc.500 Sugar Mill Road, Suite 200B Atlanta, GA 30350Tel: 770-640-0034 Fax: 770-640-0307 BostonMicrochip Technology Inc.5 Mount Royal AvenueMarlborough, MA 01752T el: 508-480-9990 Fax: 508-480-8575 ChicagoMicrochip Technology Inc.333 Pierce Road, Suite 180Itasca, IL 60143Tel: 630-285-0071 Fax: 630-285-0075 DallasMicrochip T echnology Inc.14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809Tel: 972-991-7177 Fax: 972-991-8588 DaytonMicrochip T echnology Inc.Two Prestige Place, Suite 150 Miamisburg, OH 45342Tel: 937-291-1654 Fax: 937-291-9175 Los AngelesMicrochip Technology Inc.18201 Von Karman, Suite 1090Irvine, CA 92612Tel: 714-263-1888 Fax: 714-263-1338 New YorkMicrochip T echnology Inc.150 Motor Parkway, Suite 416 Hauppauge, NY 11788T el: 516-273-5305 Fax: 516-273-5335 San JoseMicrochip Technology Inc.2107 North First Street, Suite 590San Jose, CA 95131T el: 408-436-7950 Fax: 408-436-7955 TorontoMicrochip Technology Inc.5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253ASIA/PACIFICHong KongMicrochip Asia PacificRM 3801B, Tower T woMetroplaza223 Hing Fong RoadKwai Fong, N.T., Hong KongTel: 852-2-401-1200 Fax: 852-2-401-3431IndiaMicrochip Technology IndiaNo. 6, Legacy, Convent RoadBangalore 560 025, IndiaT el: 91-80-229-0061 Fax: 91-80-229-0062KoreaMicrochip Technology Korea168-1, Y oungbo Bldg. 3 FloorSamsung-Dong, Kangnam-KuSeoul, KoreaTel: 82-2-554-7200 Fax: 82-2-558-5934ShanghaiMicrochip TechnologyRM 406 Shanghai Golden Bridge Bldg.2077 Y an’an Road West, Hongiao DistrictShanghai, PRC 200335T el: 86-21-6275-5700Fax: 86 21-6275-5060SingaporeMicrochip T echnology TaiwanSingapore Branch200 Middle Road#10-03 Prime CentreSingapore 188980T el: 65-334-8870 Fax: 65-334-8850Taiwan, R.O.CMicrochip Technology Taiwan10F-1C 207Tung Hua North RoadTaipei, Taiwan, ROCT el: 886 2-717-7175 Fax: 886-2-545-0139EUROPEUnited KingdomArizona Microchip Technology Ltd.Unit 6, The CourtyardMeadow Bank, Furlong RoadBourne End, Buckinghamshire SL8 5AJTel: 44-1628-851077 Fax: 44-1628-850259FranceArizona Microchip Technology SARLZone Industrielle de la Bonde2 Rue du Buisson aux Fraises91300 Massy, FranceTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79GermanyArizona Microchip Technology GmbHGustav-Heinemann-Ring 125D-81739 Müchen, GermanyTel: 49-89-627-144 0 Fax: 49-89-627-144-44ItalyArizona Microchip Technology SRLCentro Direzionale ColleonePalazzo Taurus 1 V. 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BC546/547/548/549/550NPN Epitaxial Silicon TransistorAbsolute Maximum Ratings T a =25°C unless otherwise notedElectrical Characteristics T a =25°C unless otherwise notedh FE ClassificationSymbol ParameterValue Units V CBOCollector-Base Voltage : BC546: BC547/550: BC548/549 805030V V V V CEOCollector-Emitter Voltage : BC546: BC547/550: BC548/549654530V V V V EBO Emitter-Base Voltage : BC546/547: BC548/549/55065V V I C Collector Current (DC)100mA P C Collector Power Dissipation 500mW T J Junction Temperature 150°C T STGStorage Temperature-65 ~ 150°CSymbol ParameterTest ConditionMin.Typ.Max.Units I CBO Collector Cut-off Current V CB =30V, I E =015nAh FE DC Current GainV CE =5V, I C =2mA 110800V CE (sat)Collector-Emitter Saturation Voltage I C =10mA, I B =0.5mA I C =100mA, I B =5mA 90200250600mV mV V BE (sat)Base-Emitter Saturation Voltage I C =10mA, I B =0.5mA I C =100mA, I B =5mA 700900mV mV V BE (on)Base-Emitter On Voltage V CE =5V, I C =2mA V CE =5V, I C =10mA580660700720mV mV f T Current Gain Bandwidth Product V CE =5V, I C =10mA, f=100MHz 300MHz C ob Output Capacitance V CB =10V, I E =0, f=1MHz 3.56pF C ib Input CapacitanceV EB =0.5V, I C =0, f=1MHz 9pF NFNoise Figure : BC546/547/548: BC549/550: BC549: BC550V CE =5V, I C =200µA f=1KHz, R G =2K ΩV CE =5V, I C =200µAR G =2K Ω, f=30~15000MHz21.21.41.410443dB dB dB dB ClassificationA B C h FE110 ~ 220200 ~ 450420 ~ 800BC546/547/548/549/550Switching and Applications•High Voltage: BC546, V CEO =65V •Low Noise: BC549, BC550•Complement to BC556 ... BC5601. Collector2. Base3. EmitterTO-921BC546/547/548/549/550BC546/547/548/549/550TRADEMARKSThe following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body,or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of TermsDatasheet Identification Product Status DefinitionAdvance InformationFormative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.PreliminaryFirst ProductionThis datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.No Identification Needed Full ProductionThis datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.Obsolete Not In ProductionThis datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.FACT™FACT Quiet series™FAST ®FASTr™FRFET™GlobalOptoisolator™GTO™HiSeC™I 2C™ImpliedDisconnect™ISOPLANAR™LittleFET™MicroFET™MicroPak™MICROWIRE™MSX™MSXPro™OCX™OCXPro™OPTOLOGIC ®OPTOPLANAR™PACMAN™POP™Power247™PowerTrench ®QFET™QS™QT Optoelectronics™Quiet Series™RapidConfigure™RapidConnect™SILENT SWITCHER ®SMART START™SPM™Stealth™SuperSOT™-3SuperSOT™-6SuperSOT™-8SyncFET™TinyLogic™TruTranslation™UHC™UltraFET ®VCX™ACEx™ActiveArray™Bottomless™CoolFET™CROSSVOLT ™DOME™EcoSPARK™E 2CMOS™EnSigna™Across the board. Around the world.™The Power Franchise™Programmable Active Droop™分销商库存信息: FAIRCHILDBC547B_J35Z。

产品数据手册嵌入式工业计算机基本参数CPU ARM926EJ,主频为300MHz内存64MB DDR2高性能内存Nand Flash SLC Nand Flash 板载为128MByte SLC Flash 网口1个100M/10M 以太网接口支持AUTO MDI/MDIX 双级抗雷防护支持GB/T 17626.5-2008标准中10/700uS 测试的3级2KV 防护±15kV Human Body Model±15kV IEC1000-4-2Air DischargeRS485接口2个全隔离RS485接口（支持收发指示灯）RS485采用三级防护支持GB/T 17626.5-2008标准中10/700uS 测试的最高等级4KV 防护±15kV Human Body Model±15kV IEC1000-4-2Air DischargeRS232接口2个全隔离RS232接口(2个全隔离RS232接口与RS485为复用关系)±15kV Human Body Model±15kV IEC1000-4-2Air Discharge电源接口支持2种电源接口标准5.08mm 间距3PIN 欧式端子接口DC 座5.5*2.1mm输入电压:直流DC 9~36V 交流AC 9～24V电源防护GB/T 17626.5-2008标准4级(4KV)8/20uS 雷击测试防反接保护过压保护抗脉冲群保护抗静电:±15kV Human Body Model±15kV IEC1000-4-2Air Discharge高性能Linux 工业计算机，ARM 高速处理器，主频达200M，64M 内存，一站式实现现场数据采集、自动控制、远程通信等功能，并支持云服务器，实现实时数据同步及远程控制功能，无需额外DTU 等外围设备。

应用领域：用于设备监控，给排水设备监控，水处理设备监控，智能照明控制系统，冷冻站和换热站系统，以及其它控制设备。

全系列常用三极管型号参数资料三极管是一种常见的电子器件，广泛应用于电子电路中。

它具有放大和开关功能，在各个领域中都有重要的作用。

下面是一些常用的三极管型号及其参数资料。

1. BC547(BJT NPN Transistor)：-最大电流：0.2A-最大功率：0.625W-最大电压：45V-最高频率：200MHz-封装类型：TO-922. BC557(BJT PNP Transistor)：-最大电流：0.2A-最大功率：0.625W-最大电压：45V-最高频率：200MHz-封装类型：TO-923. 2N3904(BJT NPN Transistor)：-最大电流：0.2A-最大功率：0.625W-最大电压：40V-最高频率：100MHz-封装类型：TO-924. 2N3906(BJT PNP Transistor)：-最大电流：0.2A-最大功率：0.625W-最大电压：40V-最高频率：100MHz-封装类型：TO-925. 2N2222(BJT NPN Transistor)：-最大电流：0.8A-最大功率：0.5W-最大电压：40V-最高频率：300MHz-封装类型：TO-926. 2N2907(BJT PNP Transistor)：-最大电流：0.6A-最大功率：0.625W-最大电压：40V-最高频率：200MHz-封装类型：TO-92以上是一些常用的三极管型号及其参数资料，供参考使用。

不同型号的三极管参数可能会有所不同，具体使用时可以根据需要选择合适的型号。

三极管的参数资料可以在厂商的官方网站或者器件手册中找到。

广州鼎甲计算机科技有限公司热线：4000-033-191 电话：+86 20 28219262/263传真：+86 20 28219284 网站：地址：广州市天河区东圃大观中路492号广州天河软件园岭南科技中心2楼邮编：510660Infokist产品特点：■ 软硬一体化Infokist集大容量存储、备份管理与监控、以及高性能服务器于一体。

硬件的选配是鼎甲技术团队通过反复测试和调整而取得的一系列最优化配置组合。

■ 配置专业合理Infokist是鼎甲技术团队针对数据备份、数据保护、数据高可用对存储硬件的特殊要求而设计的高性能专业存储备份产品。

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Infokist技术优势■ 支持异构环境下的文件保护支持对不同操作系统平台下的文件的备份、同步和恢复，包括Windows、Linux、AIX、Solaris、HP-UX以及龙芯和飞腾架构下中标麒麟操作系统等。

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■ 支持对正在被使用的文件的备份通过快照技术对正在被使用的文件进行备份，以确保备份数据的一致性。

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■ 支持磁盘到磁盘到云(D2D2C)的数据保护模式在优化的D2D备份恢复上增加了具有源端加密和重复数据删除功能的云复制，进一步保证了备份数据的安全性和可靠性。

SMOKE DETECTOR WITH INTERCONNECTThe A5364CA is a low-current, CMOS circuit providing all of the required features for an ionization-type smoke detector. A networking capability allows as many as 125 units to be interconnected so that if any unit senses smoke, all units will sound an alarm. In addition,special features are incorporated to facilitate alignment and test of the finished smoke detector. This device is designed to comply with Underwriters Laboratories Specification UL217.The internal oscillator and timing circuitry keeps standby power to a minimum by powering down the device for 1.66 seconds and sensing smoke for only 10 ms. Every 24 on/off cycles, a check is made for low battery condition. By substituting other types of sensors, or a switch for the ionization detector, this very-low power device can be used in numerous other battery-operated safety/security applications.The A5364CA is supplied in a low-cost, 16-pin dual in-line plastic package. It is rated for continuous operation over the temperaturerange of 0°C to +50°C. Similar devices. with an internal timer to allow for a period of reduced sensitivity (“hush”), are available as the A5368CA.Always order by complete part number: A5364CA .Data Sheet 26110.7AFEATURESI Interconnect Up to 125 Detectors I Piezoelectric Horn DriverI Guard Outputs for Detector Input I Pulse Testing for Low Battery I Power-ON ResetI Internal Reverse Battery ProtectionI Built-In Hysteresis Reduces False Triggering ITemporal Horn Pattern53645364SMOKE DETECTOR WITHINTERCONNECT115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000Copyright © 1998, 1999 Allegro MicroSystems, Inc.9 VGUARD GUARD +V581110712691415165364SMOKE DETECTOR WITH INTERCONNECTTestLimitsCharacteristic Pin Test Conditions Min.Typ.Max.Units Supply Voltage Range 6Operating6.09.012V Detector Input Current 150 to 40% RH, V IN = 0 to 9.0 V ——±1.0pA Input Offset Voltage14-15Active Guard ——±100mV 16-15Active Guard ——±100mV 15-13Detect Comparator ——±50mV Hysteresis13No Alarm to Alarm 90130170mV Common Mode Range14-15Guard Amplifier 2.0—V DD - 0.5V 13-15Smoke Comparator 0.5—V DD - 2.0V Active Guard Impedance14to V SS —10—k Ω16to V SS —500—k Ω Oscillator Period12No Alarm 1.34 1.67 2.00s Alarm324048ms Oscillator Pulse Width 48.01012ms Low Voltage Threshold 6T A = 0 to 50°C7.2—7.8V Sensitivity Adj. Voltage 13V 13/V DD , pin 13 open circuit 48.55051.5% Horn Output Voltage10-11I OUT = 16 mA, V DD = 9.0 V —0.10.5V I OUT = 16 mA, V DD = 7.2 V ——0.9V I OUT = -16 mA, V DD = 9.0 V 8.58.8—V I OUT = -16 mA, V DD = 7.2 V6.3——V Horn Output ON Time10-11Alarm (see figure, time “A”)450500550ms Low Battery8.01012ms Horn Output OFF Time10-11Alarm (see figure, time “B”)450500550ms Alarm (see figure, time “C”)135015001650ms Low Battery324048s LED Output ON Current 5V DD = 7.2 V, V OUT = 1.0 V 10——mA LED Output ON Time 5No Local Alarm; Not Latched 8.01012ms LED Output OFF Time5No Alarm, In Standby324048sELECTRICAL CHARACTERISTICS at T A = +25°C, V DD = 9.0 V, V SS = 0 V, C 12 = 0.1 µF,R 7 = 8.2 M Ω (unless otherwise noted).Continued next page . . .NOTE 1:Negative current is defined as coming out of (sourcing) the specified device pin.NOTE 2:Alarm (Smoke) Condition is defined as V 15 < V 13; No Alarm (No Smoke) Condition as V 15 > V 13.5364SMOKE DETECTOR WITH INTERCONNECT115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000I/O Current2No Alarm, V I/O = V DD - 2.0 V 25—60µA Alarm, V I/O = V DD - 2.0 V-7.5——mA I/O Alarm Voltage 2External “Alarm” In 3.0——V I/O Delay 2“Alarm” Out— 3.0—s Supply Current6V DD = 9.0 V, No Alarm, No Loads — 5.09.0µA V DD = 12 V, No Alarm, No Loads——12µATestLimitsCharacteristic Pin Test Conditions Min.Typ.Max.Units ELECTRICAL CHARACTERISTICS (continued)CIRCUIT DESCRIPTIONThe A5364CA is a low-current CMOS circuit providing all of the required features for an ionization-type smoke detector.Oscillator. An internal oscillator operates with a period of 1.67 seconds during no-smoke conditions. Every 1.67 seconds,internal power is applied to the entire circuit and a check is made for smoke. Every 24clock cycles (40 seconds), the LED is pulsed and a check is made for low battery by comparing V DD to an internal reference.Because very-low currents are used in the device, the oscillator capacitor at pin 12should be a low-leakage type (PTFE, polysty-rene, or polypropylene).Detector Circuitry. When smoke isdetected, the resistor divider network that sets the sensitivity (smoke trip point) is altered to increase the sensitivity set voltage (pin 13) by typically 130 mV with no external connec-tions to pins 3 or 13. This provides hysteresis and reduces false triggering. An active guard is provided on both pins adjacent to the detector input (pin 15). The voltage at pins 14 and 16 will be within 100 mV of the input.This will keep surface leakage currents to a minimum and provide a method of measuring the input voltage without loading the ionization chamber. The active guard amplifier is not power strobed and thus provides constant protection from surface leakage currents. The detector input has internal diode protection against static damage.Alarm Circuitry. If smoke is detected, the oscillator period changes to 40 ms and the horn is enabled. The horn output is typically 0.5 s ON, 0.5 s OFF, 0.5 s ON, 0.5 s OFF, 0.5 s ON, 1.5 s OFF (temporal horn pattern). During the OFF time, smoke is checked and will inhibit further alarm output if smoke is not sensed. During smoke conditions the low battery alarm is inhibited and the LED is driven at a 1 Hz rate.Sensitivity Adjust. The detector sensitivity to smoke is set inter-nally by a voltage divider connected between V DD and V SS . Thesensitivity can be externally adjusted to the individual characteristics of the ionization chamber by connecting a resistor between pin 13 and V DD , or between pin 13 and V SS .Low Battery. The low battery threshold is set internally by a voltage divider connected between V DD and V SS . The threshold can be in-creased by connecting a resistor between pin 3 and V DD . The threshold can be decreased by connecting a resistor between pin 3 and V SS . The battery voltage level is checked every 40 seconds during the 10 mA,10 ms LED pulse. If an LED is not used, it should be replaced with an equivalent resistor (typically 500 Ω to 1000 Ω) such that the battery loading remains at 10 mA.NOTE 1:Negative current is defined as coming out of (sourcing) the specified device pin.NOTE 2:Alarm (Smoke) Condition is defined as V 15 < V 13; No Alarm (No Smoke) Condition as V 15 > V 13.5364SMOKE DETECTOR WITH INTERCONNECTV12OSC. CAPINTERNAL CLOCKLED SMOKE COMPARATORSMOKE CHAMBERHORNDwg. WC-003-3I/OI/O. A connection is provided at pin 2 to allow multiple smoke detectors to becommoned. If any single unit detects smoke (I/O is driven high), all connected units will sound their associated horns after a nominal 3second delay. The LED is suppressed when an alarm is signaled from an interconnected unit.Testing. On power up, all internal counters are reset. Internal test circuitry allows for low battery check by holding pins 8 and 12low during power up, then reducing V DD and monitoring HORN 1 (pin 10). All functional tests can be accelerated by driving pin 12with a 2 kHz square wave. The 10 ms strobe period must be maintained for proper opera-tion of the comparator circuitry.313TIMING DIAGRAM IN TYPICAL APPLICATION5364SMOKE DETECTOR WITHINTERCONNECT115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000I/O OPERATIONINTERNAL CLOCKHORNV2 IN I/OV2 OUT I/OINTERNAL CLOCKDwg. WC-004-2HORN5364SMOKE DETECTOR WITH INTERCONNECTDimensions in Inches(controlling dimensions)Dimensions in Millimeters(for reference only)NOTES:1.Lead thickness is measured at seating plane or below.2.Lead spacing tolerance is non-cumulative.3.Exact body and lead configuration at vendor’s option within limits shown.Dwg. MA-001-16A in1618Dwg. MA-001-16A mm16185364SMOKE DETECTOR WITHINTERCONNECT115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000The products described here are manufactured under one or more U.S. patents or U.S. patents pending.Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, ormanufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi-bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.SAFETY & SECURITY ICsPart Number FunctionA3054KU/SU Multiplexed two-wire Hall-effect sensorA5348CA Ionization-type smoke detector with interconnect, timer, and reverse-battery protection A5349CA Ionization-type smoke detector with interconnect and timer for ac line operation A5350CA Ionization-type smoke detector with interconnect and reverse-battery protection A5354CA Ionization-type smoke detector with interconnect and reverse-battery protection A5358CA Photoelectric-type smoke detector with interconnect and timerA5364CA Ionization-type smoke detector with interconnect, reverse-battery protection,and temporal horn patternA5368CAIonization-type smoke detector with interconnect, timer, reverse-battery protection,and temporal horn pattern。

CAT93C46/56/57/66/861K/2K/2K/4K/16K-Bit Microwire Serial EEPROM FEATURESs High speed operation:– 93C56/57/66: 1MHz – 93C46/86: 3MHzs Low power CMOS technology s 1.8 to 6.0 volt operations Selectable x8 or x16 memory organization s Self-timed write cycle with auto-clear s Hardware and software write protections Power-up inadvertant write protection s 1,000,000 Program/erase cycles s 100 year data retentions Commercial, industrial and automotivetemperature rangess Sequential read (except CAT93C46)s Program enable (PE) pin (CAT93C86 only)s Available in new lead-free packagesPIN CONFIGURATIONDIP Package (P, L)SOIC Package (J,W)CMOS EEPROM floating gate technology. The devices are designed to endure 1,000,000 program/erase cycles and have a data retention of 100 years. The devices are available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP packages.DESCRIPTIONThe CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit Serial EEPROM memory devices which are configured as either registers of 16 bits (ORG pin at V CC ) or 8 bits (ORG pin at GND). Each register can be written (or read)serially by using the DI (or DO) pin. The CAT93C46/56/57/66/86 are manufactured using Catalyst’s advancedSOIC Package (S,V)93C46/56/57/66/86F01PIN FUNCTIONSPin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output V CC +1.8 to 6.0V Power Supply GND GroundORG Memory Organization NC No Connection PE*Program EnableBLOCK DIAGRAMNote:When the ORG pin is connected to VCC, the X16 organization is selected. When it is connected to ground, the X8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the X16 organization.SOIC Package (K,X)© 2002 by Catalyst Semiconductor, Inc.Characteristics subject to change without notice.TSSOP Package (U,Y)*Only For 93C86CS SK DI DOV CC NC (PE*)ORGGNDCS SK DI DOV CCORG GNDV CC CS SK ORG GND DO DICS SK DI DOV CC ORG GND NC (PE*)NC (PE*)V CC ORG GNDDI SK DONC (PE*)V SKCS DI ORGGNDDoc. No. 1023, Rev. CLEAD-FREE PACK AGE OPTION293C46/56/57/66/86Doc. No. 1023, Rev. CABSOLUTE MAXIMUM RATINGS*Temperature Under Bias ..................-55°C to +125°C Storage Temperature........................-65°C to +150°C Voltage on any Pin withRespect to Ground (1).............-2.0V to +V CC +2.0V V CC with Respect to Ground ................-2.0V to +7.0V Package Power DissipationCapability (Ta = 25°C)...................................1.0W Lead Soldering Temperature (10 secs)............300°C Output Short Circuit Current (2)........................100 mA *COMMENTStresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.RELIABILITY CHARACTERISTICSSymbol Parameter Reference Test Method Min TypMaxUnits N END (3)Endurance MIL-STD-883, Test Method 10331,000,000Cycles/Byte T DR (3)Data Retention MIL-STD-883, Test Method 1008100Years V ZAP (3)ESD SusceptibilityMIL-STD-883, Test Method 30152000Volts I LTH (3)(4)Latch-UpJEDEC Standard 17100mANote:(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DCvoltage on output pins is V CC +0.5V, which may overshoot to V CC +2.0V for periods of less than 20 ns.(2)Output shorted for no more than one second. No more than one output shorted at a time.(3)This parameter is tested initially and after a design or process change that affects the parameter.(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V CC +1V.(5) Standby Current (ISB 2)=0µA (<900nA) for 93C46/56/57/66, (ISB 2)=2µA for 93C86.D.C. OPERATING CHARACTERISTICSV CC = +1.8V to +6.0V, unless otherwise specified.Symbol Parameter Test Conditions MinTypMax Units I CC1Power Supply Current f SK = 1MHz 3mA (Operating Write)V CC = 5.0V I CC2Power Supply Current f SK = 1MHz 500µA (Operating Read)V CC = 5.0V I SB1Power Supply Current CS = 0V 10µA (Standby) (x8 Mode)ORG=GND I SB2(5)Power Supply Current CS=0V0µA (Standby) (x16Mode)ORG=Float or V CC I LI Input Leakage Current V IN = 0V to V CC 1µA I LO Output Leakage Current V OUT = 0V to V CC ,1µA (Including ORG pin)CS = 0V V IL1Input Low Voltage 4.5V ≤V CC <5.5V-0.10.8V V IH1Input High Voltage 2V CC +1V V IL2Input Low Voltage 1.8V ≤V CC <2.7V 0V CC X0.2V V IH2Input High Voltage V CC X0.7V CC +1V V OL1Output Low Voltage 4.5V ≤V CC <5.5V 0.4V V OH1Output High Voltage I OL = 2.1mA 2.4V I OH = -400µA V OL2Output Low Voltage 1.8V ≤V CC <2.7V 0.2V V OH2Output High VoltageI OL = 1mA V CC -0.2VI OH = -100µA393C46/56/57/66/86Doc. No. 1023, Rev. CPIN CAPACITANCE Symbol TestConditions MinTypMax Units C OUT (3)OUTPUT CAPACITANCE (DO)V OUT =0V 5pF C IN (3)INPUT CAPACITANCE (CS, SK, DI, ORG)V IN =0V5pFNote:(1)Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITEand ERASE commands.(2)Applicable only to 93C86(3)This parameter is tested initially and after a design or process change that affects the parameter.INSTRUCTION SET Instruction DeviceStart Opcode Address Data CommentsPE (2)Type Bit x8x16x8x16READ93C46110A6-A0A5-A0 Read Address AN–A093C56(1)110A8-A0A7-A093C66110A8-A0A7-A093C57110A7-A0A6-A093C86110A10-A0A9-A0XERASE93C46111A6-A0A5-A0 Clear Address AN–A093C56(1)111A8-A0A7-A093C66111A8-A0A7-A093C57111A7-A0A6-A093C86111A10-A0A9-A0IWRITE93C46101A6-A0A5-A0D7-D0D15-D0Write Address AN–A093C56(1)101A8-A0A7-A0D7-D0D15-D093C66101A8-A0A7-A0D7-D0D15-D093C57101A7-A0A6-A0D7-D0D15-D093C86101A10-A0A9-A0D7-D0D15-D0IEWEN93C4610011XXXXX 11XXXX Write Enable93C5610011XXXXXXX 11XXXXXX 93C6610011XXXXXXX 11XXXXXX 93C5710011XXXXXX 11XXXXX 93C8610011XXXXXXXXX 11XXXXXXXX XEWDS93C4610000XXXXX 00XXXX Write Disable93C5610000XXXXXXX 00XXXXXX 93C6610000XXXXXXX 00XXXXXX 93C5710000XXXXXX 00XXXXX 93C8610000XXXXXXXXX 00XXXXXXXX XERAL93C4610010XXXXX 10XXXX Clear All Addresses93C5610010XXXXXXX 10XXXXXX 93C6610010XXXXXXX 10XXXXXX 93C5710010XXXXXX 10XXXXX 93C8610010XXXXXXXXX 10XXXXXXXX IWRAL93C4610001XXXXX 01XXXX D7-D0D15-D0Write All Addresses93C5610001XXXXXXX 01XXXXXX D7-D0D15-D093C6610001XXXXXXX 01XXXXXX D7-D0D15-D093C5710001XXXXXX 01XXXXX D7-D0D15-D093C8610001XXXXXXXXX 01XXXXXXXXD7-D0D15-D0I元器件交易网4Doc. No. 1023, Rev. C元器件交易网593C46/56/57/66/86Doc. No. 1023, Rev. C元器件交易网6Doc. No. 1023, Rev. C元器件交易网793C46/56/57/66/86Doc. No. 1023, Rev. C元器件交易网8Doc. No. 1023, Rev. C元器件交易网993C46/56/57/66/86Doc. No. 1023, Rev. C元器件交易网Copyrights, Trademarks and PatentsTrademarks and registered trademarks of Catalyst Semiconductor include each of the following:DPP ™AE2 ™Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur.Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.Catalyst Semiconductor, Inc.Corporate Headquarters1250 Borregas AvenueSunnyvale, CA 94089Phone: 408.542.1000Fax: 408.542.1200 Publication #:1023 Revison:CIssue date:05/17/02 Type:Final元器件交易网。

FEATURES•Single supply 5.0V operation •Low power CMOS technology - 1 mA active current (typical)- 1 µ A standby current (maximum)•64 x 16 bit organization•Self-timed ERASE and WRITE cycles (including auto-erase)•Automatic ERAL before WRAL•Power on/off data protection circuitry •Industry standard 3-wire serial interface•Device status signal during ERASE/WRITE cycles •Sequential READ function•1,000,000 E/W cycles guaranteed •Data retention > 200 years•8-pin PDIP/SOIC and 8-pin TSSOP packages •Available for the following temperature ranges: DESCRIPTIONThe Microchip T echnology Inc. 93C46B is a 1K-bit,low-voltage serial Electrically Erasable PROM. The device memory is configured as 64 x 16 bits. Advanced CMOS technology makes this device ideal for low-power, nonvolatile memory applications. The 93C46B is available in standard 8-pin DIP , surface mount SOIC, and TSSOP packages. The 93C46BX are only offered in a 150 mil SOIC package.-Commercial (C):0 ° C to +70 ° C -Industrial (I): -40 ° C to +85 ° C -Automotive (E): -40 ° C to +125 °C元器件交易网93C46B1.0ELECTRICALCHARACTERISTICS1.1Maximum Ratings*V CC...................................................................................7.0V All inputs and outputs w.r.t. V SS...............-0.6V to V CC +1.0V Storage temperature.....................................-65°C to +150°C Ambient temp. with power applied.................-65°C to +125°C Soldering temperature of leads (10 seconds).............+300°C ESD protection on all pins................................................4 kV *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri-ods may affect device reliability.TABLE 1-1PIN FUNCTION TABLE Name FunctionCS Chip SelectCLK Serial Data ClockDI Serial Data InputDO Serial Data OutputV SS GroundNC No ConnectV CC Power SupplyTABLE 1-2DC AND AC ELECTRICAL CHARACTERISTICSAll parameters apply over the specified operating ranges unless otherwise noted Commercial (C) V CC = +4.5V to +5.5V T amb = 0°C to +70°C Industrial (I)V CC = +4.5V to +5.5V T amb = -40°C to +85°C Automotive (E)V CC = +4.5V to +5.5V T amb = -40°C to +125°CParameter Symbol Min.Max.Units Conditions High level input voltage V IH 2.0V CC +1V(Note 2)Low level input voltage V IL-0.30.8VLow level output voltage V OL—0.4V I OL = 2.1 mA; V CC = 4.5V High level output voltage V OH 2.4—V I OH = -400 µA; V CC = 4.5V Input leakage current I LI-1010µA V IN = V SS to V CCOutput leakage current I LO-1010µA V OUT = V SS to V CCPin capacitance (all inputs/outputs)C IN, C OUT—7pFV IN/V OUT = 0 V (Notes 1 & 2)T amb = +25°C, F CLK = 1 MHz I CC read — 1 mAOperating current I CC write— 1.5mAStandby current I CCS—1µA CS = V SSClock frequency F CLK—2MHz V CC = 4.5VClock high time T CKH250—nsClock low time T CKL250—nsChip select setup time T CSS50—ns Relative to CLK Chip select hold time T CSH0—ns Relative to CLK Chip select low time T CSL250—nsData input setup time T DIS100—ns Relative to CLK Data input hold time T DIH100—ns Relative to CLK Data output delay time T PD—400ns C L = 100 pFData output disable time T CZ—100ns C L = 100 pF (Note 2) Status valid time T SV—500ns C L = 100 pFProgram cycle time T WC—2ms ERASE/WRITE mode T EC—6ms ERAL modeT WL—15ms WRAL modeEndurance—1M—cycles25°C, V CC = 5.0V, Block Mode (Note 3)Note 1:This parameter is tested at Tamb = 25°C and F CLK = 1 MHz.2:This parameter is periodically sampled and not 100% tested.3:This application is not tested but guaranteed by characterization. For endurance estimates in a specific appli-cation, please consult the T otal Endurance Model which may be obtained on Microchip’s BBS or website.元器件交易网93C46B2.0PIN DESCRIPTION2.1Chip Select (CS)A high level selects the device; a low level deselects the device and forces it into standby mode. However, a pro-gramming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into standby mode as soon as the pro-gramming cycle is completed.CS must be low for 250 ns minimum (T CSL) between consecutive instructions. If CS is low, the internal con-trol logic is held in a RESET status.2.2Serial Clock (CLK)The Serial Clock (CLK) is used to synchronize the com-munication between a master device and the 93C46B. Opcodes, addresses, and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK.CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (T CKH) and clock low time (T CKL). This gives the controlling master freedom in preparing the opcode, address, and data. CLK is a “Don't Care” if CS is low (device deselected). If CS is high, but ST ART condition has not been detected, any number of clock cycles can be received by the device, without changing its status (i.e., waiting for a ST ART condition).CLK cycles are not required during the self-timed WRITE (i.e., auto ERASE/WRITE) cycle.After detecting a ST ART condition, the specified num-ber of clock cycles (respectively low to high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcodes, addresses, and data bits before an instruction is executed (T able 2-1). CLK and DI then become don't care inputs waiting for a new ST ART condition to be detected.2.3Data In (DI)Data In (DI) is used to clock in a ST ART bit, opcode, address, and data synchronously with the CLK input.2.4Data Out (DO)Data Out (DO) is used in the READ mode to output data synchronously with the CLK input (T PD after the posi-tive edge of CLK).This pin also provides READY/BUSY status information during ERASE and WRITE cycles. READY/BUSY sta-tus information is available on the DO pin if CS is brought high after being low for minimum chip select low time (T CSL) and an ERASE or WRITE operation has been initiated.The status signal is not available on DO, if CS is held low during the entire ERASE or WRITE cycle. In this case, DO is in the HIGH-Z mode. If status is checked after the ERASE/WRITE cycle, the data line will be high to indicate the device is ready.TABLE 2-1INSTRUCTION SET FOR 93C46BInstruction SB Opcode Address Data In Data Out Req. CLK CyclesERASE111A5A4A3A2A1A0—(RDY/BSY)9ERAL10010X X X X—(RDY/BSY)9EWDS10000X X X X—HIGH-Z9EWEN10011X X X X—HIGH-Z9READ110A5A4A3A2A1A0—D15 - D025WRITE101A5A4A3A2A1A0D15 - D0(RDY/BSY)25WRAL10001X X X X D15 - D0(RDY/BSY)25元器件交易网93C46B3.0FUNCTIONAL DESCRIPTION Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a HIGH-Z state except when reading data from the device, or when checking the READY/BUSY status during a programming operation. The READY/BUSY status can be verified during an ERASE/WRITE operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. The DO will enter the HIGH-Z state on the falling edge of the CS.3.1START ConditionThe ST ART bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time.Before a ST ART condition is detected, CS, CLK, and DI may change in any combination (except to that of a ST ART condition), without resulting in any device oper-ation (ERASE, ERAL, EWDS, EWEN, READ, WRITE, and WRAL). As soon as CS is high, the device is no longer in the standby mode.An instruction following a START condition will only be executed if the required amount of opcodes, addresses, and data bits for any particular instruction is clocked in.After execution of an instruction (i.e., clock in or out of the last required address or data bit) CLK and DI become don't care bits until a new ST ART condition is detected.3.2Data In (DI) and Data Out (DO)It is possible to connect the Data In (DI)and Data Out (DO) pins together. However, with this configuration, if A0 is a logic-high level, it is possible for a “bus conflict”to occur during the “dummy zero” that precedes the READ operation. Under such a condition, the voltage level seen at DO is undefined and will depend upon the relative impedances of DO and the signal source driv-ing A0. The higher the current sourcing capability of A0, the higher the voltage at the DO pin.3.3Data ProtectionDuring power-up, all programming modes of operation are inhibited until Vcc has reached a level greater than 3.8V. During power-down, the source data protection circuitry acts to inhibit all programming modes when Vcc has fallen below 3.8V at nominal conditions.The ERASE/SRITE Disable (EWDS) and ERASE/ WRITE Enable (EWEN) commands give additional pro-tection against accidental programming during normal operation.After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before any ERASE or WRITE instruction can be executed.元器件交易网93C46B3.4ERASEThe ERASE instruction forces all data bits of the spec-ified address to the logical “1” state. This cycle begins on the rising clock edge of the last address bit.The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (T CSL). DO at logical “0” indicates that program-ming is still in progress. DO at logical “1” indicates that the register at the specified address has been erased and the device is ready for another instruction.3.5Erase All (ERAL)The Erase All (ERAL) instruction will erase the entire memory array to the logical “1” state. The ERAL cycle is identical to the ERASE cycle, except for the different opcode. The ERAL cycle is completely self-timed and commences at the rising clock edge of the last address bit. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle.The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (T CSL) and before the entire ERAL cycle is complete.元器件交易网93C46B3.6ERASE/WRITE Disable and Enable(EWDS/EWEN)The device powers up in the ERASE/WRITE Disable (EWDS) state. All programming modes must be pre-ceded by an Erase/Write Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or Vcc is removed from the device. T o protect against accidental data disturbance, the EWDS instruction can be used to disable all ERASE/WRITE functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWDS and EWEN instructions.3.7READThe READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 16-bit output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (T PD). Sequen-tial read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially.FIGURE 3-6:READ TIMING CSCLKDI DO110An•••A0HIGH-Z0Dx•••D0Dx•••D0•••Dx D0元器件交易网93C46B3.8WRITEThe WRITE instruction is followed by 16 bits of data, which are written into the specified address. After the last data bit is clocked into the DI pin, the self-timed auto-erase and programming cycle begins.The DO pin indicates the READY/BUSY status of the device, if CS is brought high after a minimum of 250 ns low (T CSL) and before the entire write cycle is complete. DO at logical “0” indicates that programming is still in progress. DO at logical “1” indicates that the register at the specified address has been written with the data specified and the device is ready for another instruc-tion.3.9Write All (WRAL)The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. The WRAL cycle is completely self-timed and com-mences at the rising clock edge of the last data bit. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL com-mand does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction, but the chip must be in the EWEN status.The DO pin indicates the READY/BUSY status of the device if CS is brought high after a minimum of 250 ns low (T CSL).元器件交易网元器件交易网93C46B Array NOTES:元器件交易网93C46B Array NOTES:元器件交易网93C46B Array NOTES:93C46B93C46B PRODUCT IDENTIFICATION SYSTEMT o order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.Sales and SupportData SheetsProducts supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1.Y our local Microchip sales office.2.The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.3.The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).元器件交易网AMERICASCorporate OfficeMicrochip Technology Inc.2355 West Chandler Blvd.Chandler, AZ 85224-6199Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: AtlantaMicrochip T echnology Inc.500 Sugar Mill Road, Suite 200B Atlanta, GA 30350Tel: 770-640-0034 Fax: 770-640-0307 BostonMicrochip Technology Inc.5 Mount Royal AvenueMarlborough, MA 01752T el: 508-480-9990 Fax: 508-480-8575 ChicagoMicrochip Technology Inc.333 Pierce Road, Suite 180Itasca, IL 60143Tel: 630-285-0071 Fax: 630-285-0075 DallasMicrochip T echnology Inc.14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809Tel: 972-991-7177 Fax: 972-991-8588 DaytonMicrochip T echnology Inc.Two Prestige Place, Suite 150 Miamisburg, OH 45342Tel: 937-291-1654 Fax: 937-291-9175 Los AngelesMicrochip Technology Inc.18201 Von Karman, Suite 1090Irvine, CA 92612Tel: 714-263-1888 Fax: 714-263-1338 New YorkMicrochip T echnology Inc.150 Motor Parkway, Suite 416 Hauppauge, NY 11788T el: 516-273-5305 Fax: 516-273-5335 San JoseMicrochip Technology Inc.2107 North First Street, Suite 590San Jose, CA 95131T el: 408-436-7950 Fax: 408-436-7955 TorontoMicrochip Technology Inc.5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253ASIA/PACIFICHong KongMicrochip Asia PacificRM 3801B, Tower T woMetroplaza223 Hing Fong RoadKwai Fong, N.T., Hong KongTel: 852-2-401-1200 Fax: 852-2-401-3431IndiaMicrochip Technology IndiaNo. 6, Legacy, Convent RoadBangalore 560 025, IndiaT el: 91-80-229-0061 Fax: 91-80-229-0062KoreaMicrochip Technology Korea168-1, Y oungbo Bldg. 3 FloorSamsung-Dong, Kangnam-KuSeoul, KoreaTel: 82-2-554-7200 Fax: 82-2-558-5934ShanghaiMicrochip TechnologyRM 406 Shanghai Golden Bridge Bldg.2077 Y an’an Road West, Hongiao DistrictShanghai, PRC 200335T el: 86-21-6275-5700Fax: 86 21-6275-5060SingaporeMicrochip T echnology TaiwanSingapore Branch200 Middle Road#10-03 Prime CentreSingapore 188980T el: 65-334-8870 Fax: 65-334-8850Taiwan, R.O.CMicrochip Technology Taiwan10F-1C 207Tung Hua North RoadTaipei, Taiwan, ROCT el: 886 2-717-7175 Fax: 886-2-545-0139EUROPEUnited KingdomArizona Microchip Technology Ltd.Unit 6, The CourtyardMeadow Bank, Furlong RoadBourne End, Buckinghamshire SL8 5AJTel: 44-1628-851077 Fax: 44-1628-850259FranceArizona Microchip Technology SARLZone Industrielle de la Bonde2 Rue du Buisson aux Fraises91300 Massy, FranceTel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79GermanyArizona Microchip Technology GmbHGustav-Heinemann-Ring 125D-81739 Müchen, GermanyTel: 49-89-627-144 0 Fax: 49-89-627-144-44ItalyArizona Microchip Technology SRLCentro Direzionale ColleonePalazzo Taurus 1 V. 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常见集成运放型号大全LF351 BI-FET单运算放大器NSLF353 BI-FET双运算放大器NSLF356 BI-FET单运算放大器NSLF357 BI-FET单运算放大器NSCA3130高输入阻抗运算放大器IntersilCA3140 高输入阻抗运算放大器CD4573 四可编程运算放大器MC14573ICL7650斩波稳零放大器LF347(NS[DATA]) 带宽四运算放大器KA347LF398 采样保持放大器NS[DATA]LF411 BI-FET单运算放大器NS[DATA]LF412 BI-FET双运放大器NS[DATA]LM318 高速运算放大器NS[DATA]LM324四运算放大器NS[DATA]HA17324,/LM324(TI)LM348四运算放大器NLM358NS[DATA] 通用型双运算放大器HA17358/LM358P(TI)LM380 音频功率放大器NS[DATA]LM386-1 NS[DATA] 音频放大器NJM386D,UTC386LM386-3 音频放大器NS[DATA]LM386-4 音频放大器NS[DATA]LM3886 音频大功率放大器NS[DATA]LM3900 四运算放大器LM124 低功耗四运算放大器(军用档) NS[DATA]/TI[DATA]LM1458 双运算放大器NS[DATA]LM148 四运算放大器NS[DATA]LM224J 低功耗四运算放大器(工业档) NS[DATA]/TI[DATA]LM2902 四运算放大器NS[DATA]/TI[DATA]LM2904 双运放大器NS[DATA]/TI[DATA]LM301 运算放大器NS[DATA]LM308 运算放大器NS[DATA]LM308H 运算放大器（金属封装）NS[DATA]LM725 高精度运算放大器NS[DATA]LM733 带宽运算放大器LM741 NS[DATA] 通用型运算放大器HA17741TBA820M 小功率音频放大器ST[DATA]TL061 BI-FET单运算放大器TI[DATA]TL062 BI-FET双运算放大器TI[DATA]TL064 BI-FET四运算放大器TI[DATA]TL072 BI-FET双运算放大器TI[DATA]TL074 BI-FET四运算放大器TI[DATA]TL081 BI-FET单运算放大器TI[DATA]TL082 BI-FET双运算放大器TI[DATA]TL084 BI-FET四运算放大器TI[DATA]MC34119 小功率音频放大器NE592 视频放大器OP07-CP精密运算放大器TI[DATA]OP07-DP 精密运算放大器TI[NE5532 高速低噪声双运算放大器TI 双运放NE5534 高速低噪声单运算放大器TI 单运放OPA602 高速高精度运放（无OPA2602）OPA604单OPA2604双低噪声运放OPA132单OPA2132双OPA4132四高速低噪运放OPA227 OPA2227 OPA4227 OPA228 OPA2228 OPA4228 高精度低噪声运放AD844：60MHz、2000V/us单芯片运算放大器高带宽、非常快速的大信号响应特性常用的压控放大器：AD603 VCA810 VCA820AD603：低噪声电压控制增益运放90MHz带宽VCA810：35MHz高增益可调节范围宽带压控放大器25mV/dB(-40dB~40dB)VCA820：150MHz增益可调运放(-20~+20dB)已经申得的样片：TLV5616- 12 位3us DAC 串行输入可编程设置时间/功耗，电压O/P 范围= 2x 基准电压TLV5616CDTLC2543- 12 位66kSPS ADC 串行输出，可编程MSB/LSB 优先，可编程断电/输出数据长度，11 通道TLC2543CDBOPA690- 具有禁用功能的宽带电压反馈运算放大器OPA690IDVCA810- 高增益可调节范围宽带压控放大器VCA810IDOPA2604- 双路FET 输入、低失真运算放大器OPA2604APTLC2543 - 12 位66kSPS ADC 串行输出，可编程MSB/LSB 优先，可编程断电/输出数据长度，11 通道TLC2543CNTLV5616 - 12 位3us DAC 串行输入可编程设置时间/功耗，电压O/P 范围= 2x 基准电压TLV5616CPVCA810 - 高增益可调节范围宽带压控放大器VCA810IDTLV5638 - 12 位、1 或3.5us DAC，具有串行输入、双路DAC、可编程内部参考和稳定时间、功耗TLV5638CDAD526精确程控放大器ADI公司，AD603，低噪声、90 MHz可变增益放大器.，ADI公司，AD605双通道、低噪声、单电源可变增益放大器，ADI公司，AD620低漂移、低功耗仪表放大器，增益设置范围1～10000 ADI公司， AD783，采样保持电路，ADI公司，AD811高性能视频运算放大器（电流反馈型宽带运放），ADI公司，AD818高速低噪声电压反馈型运放，ADI公司，AD8011 300 MHz、1 mA 电流反馈放大器，ADI公司，AD8056双路、低成本、300 MHz电压反馈型放大器ADI公司，AD8564，四路7 ns单电源高速比较器，ADI公司，AC524/AC525 5~500 MHz级联放大器，teledyne 公司，BUF634，250mA高速缓冲器，TI公司，/cnCA3140单运算直流放大器，Intersil Corporation，HFA1100 850MHz、低失真电流反馈放大器，Intersil Corporation，INA118精密低功耗仪表放大器，TI公司，/cnLF356 JFET输入运算放大器，National Semiconductor Corpora，LM311具有选通信号的差动比较器，National Semiconductor Corpora， LF356，JFET输入运算放大器，National Semiconductor Corpora，LM393电压比较器，National Semiconductor Corpora，LM7171高速电压反馈运算放大器，National Semiconductor Corpora， LM358/LM158/LM258/LM2904双运算放大器，National Semiconductor Corpora，LM2902,LM324/LM324A,LM224/ LM224A四运算放大器，National Semiconductor Corpora，LT1210 1.1A，35MHz电流反馈放大器，linear公司，/product/LT12 MAX4256，UCSP封装、单电源、低噪声、低失真、满摆幅运算放大器，Maxim公司，MAX912, MAX913单/双路、超高速、低功耗、精密的TTL比较器，Maxim公司，MAX477 ，300MHz、高速运算放大器，Maxim公司，MAX427/ MAX437低噪声、高精度运算放大器，Maxim公司MAX900高速、低功耗、电压比较器，Maxim公司NE5532双路低噪声高速音频运算放大器，TI公司，/cnNE5534低噪声高速音频运算放大器，TI公司，/cnOP27低噪声、精密运算放大器ADI公司，OP37低噪声、精密运算放大器ADI公司，OPA637，精密、高速、低漂移、高增益放大器，TI公司，/cn OPA637，精密、高速、低漂移高增益放大器，TI公司，/cn OPA642高速低噪声电压反馈型运放，TI公司，/cnOPA690，宽带50MHz、电压反馈运算放大器，TI公司，/cnOPA690 高速、电压反馈型运放（大于等于50MHz），TI公司，/cn PGA202KP，数字可编程仪表放大器，TI公司，/cnTHS3091单路高压低失真电流反馈运算放大器，TI公司，/cnTHS3092高压低失真电流反馈运算放大器，TI公司，/cnTL084，JFET 输入运算放大器，TI公司，/cnµA741标准线性放大器，TI公司，/cn。

1/31August 2004M93C86, M93C76, M93C66M93C56, M93C4616Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit (8-bit or 16-bit wide)MICROWIRE® Serial Access EEPROMFEATURES SUMMARYs Industry Standard MICROWIRE Bus sSingle Supply Voltage:– 4.5 to 5.5V for M93Cx6– 2.5 to 5.5V for M93Cx6-W – 1.8 to 5.5V for M93Cx6-Rs Dual Organization: by Word (x16) or Byte (x8) s Programming Instructions that work on: Byte, Word or Entire Memorys Self-timed Programming Cycle with Auto-Erases sSpeed:–1MHz Clock Rate, 10ms Write Time(Current product, identified by process identification letter F or M)–2MHz Clock Rate, 5ms Write Time (NewProduct, identified by process identification letter W or G or S) s Sequential Read Operations Enhanced ESD/Latch-Up Behaviour s More than 1 Million Erase/Write Cycles sMore than 40 Year Data RetentionTable 1. Product ListReferencePart Number ReferencePart Number M93C86M93C86M93C56M93C56M93C86-W M93C56-W M93C86-R M93C56-R M93C76M93C76M93C46M93C46M93C76-W M93C46-W M93C76-R M93C46-RM93C66M93C66M93C66-W M93C66-RM93C86, M93C76, M93C66, M93C56, M93C46TABLE OF CONTENTSFEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Table 1.Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Figure 2.Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 2.Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 3.Memory Size versus Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Table 4.Instruction Set for the M93Cx6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Figure 3.DIP, SO, TSSOP and MLP Connections (Top View). . . . . . . . . . . . . . . . . . . . . . . . . . . . .5MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 POWER-ON DATA PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..5INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 5.Instruction Set for the M93C46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 6.Instruction Set for the M93C56 and M93C66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Table 7.Instruction Set for the M93C76 and M93C86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Erase/Write Enable and Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 4.READ, WRITE, EWEN, EWDS Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Erase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 5.ERASE, ERAL Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Erase All. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Write All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Figure 6.WRAL Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10READY/BUSY STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 COMMON I/O OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11CLOCK PULSE COUNTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Figure 7.Write Sequence with One Clock Glitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 8.Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 9.Operating Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 10.Operating Conditions (M93Cx6-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 11.Operating Conditions (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 12.AC Measurement Conditions (M93Cx6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 13.AC Measurement Conditions (M93Cx6-W and M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . .14 Figure 8.AC Testing Input Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142/31M93C86, M93C76, M93C66, M93C56, M93C46Table 14.Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 15.DC Characteristics (M93Cx6, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 16.DC Characteristics (M93Cx6, Device Grade 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Table 17.DC Characteristics (M93Cx6-W, Device Grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Table 18.DC Characteristics (M93Cx6-W, Device Grade 7 or 3). . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 19.DC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 20.AC Characteristics (M93Cx6, Device Grade 6, 7 or 3) . . . . . . . . . . . . . . . . . . . . . . . . . .18 Table 21.AC Characteristics (M93Cx6-W, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table 22.AC Characteristics (M93Cx6-W, Device Grade 7 or 3). . . . . . . . . . . . . . . . . . . . . . . . . .20 Table 23.AC Characteristics (M93Cx6-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Figure 9.Synchronous Timing (Start and Op-Code Input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 10.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Figure 11.Synchronous Timing (Read or Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . .23 Table 24.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data. . . . . . . . . .23 Figure 13.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . .24 Table 25.SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data 24Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Outline 25Table 26.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm², Data.25Figure 15.TSSOP8 3x3mm²– 8 lead Thin Shrink Small Outline, 3x3mm² body size, Package Outline 26Table 27.TSSOP8 3x3mm²– 8 lead Thin Shrink Small Outline, 3x3mm² body size, Mechanical Data 26Figure 16.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . .27 Table 28.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data. . . . . . . . . . . .27PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 29.Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Table 30.How to Identify Current and New Products by the Process Identification Letter. . . . . . .29REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Table 31.Document Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303/31M93C86, M93C76, M93C66, M93C56, M93C464/31SUMMARY DESCRIPTIONThese electrically erasable programmable memo-ry (EEPROM) devices are accessed through a Se-rial Data Input (D) and Serial Data Output (Q)using the MICROWIRE bus protocol.Table 2. Signal NamesThe memory array organization may be divided into either bytes (x8) or words (x16) which may be selected by a signal applied on Organization Se-lect (ORG). The bit, byte and word sizes of the memories are as shown in Table 3..Table 3. Memory Size versus OrganizationThe M93Cx6 is accessed by a set of instructions,as summarized in Table 4., and in more detail in Table 5. to Table 7.).Table 4. Instruction Set for the M93Cx6A Read Data from Memory (READ) instruction loads the address of the first byte or word to be read in an internal address register. The data at this address is then clocked out serially. The ad-dress register is automatically incremented after the data is output and, if Chip Select Input (S) is held High, the M93Cx6 can output a sequential stream of data bytes or words. In this way, the memory can be read as a data stream from eight to 16384 bits long (in the case of the M93C86), or continuously (the address counter automatically rolls over to 00h when the highest address is reached).Programming is internally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle) and does not require an Erase cycle prior to the Write instruction. The Write instruction writes 8 or 16 bits at a time into one of the byte or word locations of the M93Cx6. After the start of the programming cy-cle, a Busy/Ready signal is available on Serial Data Output (Q) when Chip Select Input (S) is driv-en High.S Chip Select Input D Serial Data Input Q Serial Data Output C Serial Clock ORG Organisation Select V CC Supply Voltage V SSGroundDevice Number of Bits Number of 8-bit Bytes Number of 16-bit Words M93C861638420481024M93C7681921024512M93C664096512256M93C562048256128M93C46102412864Instruction Description Data READ Read Data from Memory Byte or Word WRITEWrite Data to Memory Byte or WordEWEN Erase/Write Enable EWDS Erase/Write Disable ERASE Erase Byte or Word Byte or WordERAL Erase All Memory WRALWrite All Memory with same DataM93C86, M93C76, M93C66, M93C56, M93C46An internal Power-on Data Protection mechanism in the M93Cx6 inhibits the device when the supply is too low.Figure 3. DIP, SO, TSSOP and MLPNote: 1.See PACKAGE MECHANICAL section for package di-mensions, and how to identify pin-1.2.DU = Don’t Use.The DU (Don’t Use) pin does not contribute to the normal operation of the device. It is reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be con-nected to V CC or V SS. Direct connection of DU to V SS is recommended for the lowest stand-by pow-er consumption.MEMORY ORGANIZATIONThe M93Cx6 memory is organized either as bytes (x8) or as words (x16). If Organization Select (ORG) is left unconnected (or connected to V CC) the x16 organization is selected; when Organiza-tion Select (ORG) is connected to Ground (V SS) the x8 organization is selected. When the M93Cx6 is in stand-by mode, Organization Select (ORG) should be set either to V SS or V CC for minimum power consumption. Any voltage between V SS and V CC applied to Organization Select (ORG) may increase the stand-by current.POWER-ON DATA PROTECTIONTo prevent data corruption and inadvertent write operations during power-up, a Power-On Reset (POR) circuit resets all internal programming cir-cuitry, and sets the device in the Write Disable mode.–At Power-up and Power-down, the device must not be selected (that is, Chip Select Input (S) must be driven Low) until the supplyvoltage reaches the operating value V CCspecified in Table 9. to Table 11..–When V CC reaches its valid level, the device is properly reset (in the Write Disable mode) and is ready to decode and execute incominginstructions.For the M93Cx6 devices (5V range) the POR threshold voltage is around 3V. For the M93Cx6-W (3V range) and M93Cx6-R (2V range) the POR threshold voltage is around 1.5V.5/31M93C86, M93C76, M93C66, M93C56, M93C466/31INSTRUCTIONSThe instruction set of the M93Cx6 devices con-tains seven instructions, as summarized in Table 5. to Table 7.. Each instruction consists of the fol-lowing parts, as shown in Figure 4.:s Each instruction is preceded by a rising edgeon Chip Select Input (S) with Serial Clock (C) being held Low.s A start bit, which is the first ‘1’ read on SerialData Input (D) during the rising edge of Serial Clock (C).s Two op-code bits, read on Serial Data Input(D) during the rising edge of Serial Clock (C). (Some instructions also use the first two bits of the address to define the op-code).sThe address bits of the byte or word that is to be accessed. For the M93C46, the address is made up of 6 bits for the x16 organization or 7 bits for the x8 organization (see Table 5.). For the M93C56 and M93C66, the address is made up of 8 bits for the x16 organization or 9 bits for the x8 organization (see Table 6.). For the M93C76 and M93C86, the address is made up of 10 bits for the x16 organization or 11 bits for the x8 organization (see Table 7.).The M93Cx6 devices are fabricated in CMOS technology and are therefore able to run as slow as 0Hz (static input signals) or as fast as the max-imum ratings specified in Table 20. to Table 23..Table 5. Instruction Set for the M93C46Note: 1.X = Don ’t Care bit.Instruc tionDescriptionStart bit Op-Codex8 Origination (ORG = 0)x16 Origination (ORG = 1)Address 1DataRequiredClock CyclesAddress 1DataRequired Clock CyclesREAD Read Data from Memory 110A6-A0Q7-Q0A5-A0Q15-Q0WRITE Write Data to Memory101A6-A0D7-D018A5-A0D15-D025EWEN Erase/Write Enable 10011X XXXX 1011 XXXX 9EWDS Erase/Write Disable 10000X XXXX 1000 XXXX 9ERASE Erase Byte or Word 111A6-A010A5-A09ERAL Erase All Memory 10010X XXXX 1010 XXXX 9WRALWrite All Memory with same Data10001X XXXXD7-D01801 XXXXD15-D0257/31M93C86, M93C76, M93C66, M93C56, M93C46Table 6. Instruction Set for the M93C56 and M93C66Note: 1.X = Don ’t Care bit.2.Address bit A8 is not decoded by the M93C56.3.Address bit A7 is not decoded by the M93C56.Table 7. Instruction Set for the M93C76 and M93C86Note: 1.X = Don ’t Care bit.2.Address bit A10 is not decoded by the M93C76.3.Address bit A9 is not decoded by the M93C76.Instruc tionDescriptionStart bit Op-Codex8 Origination (ORG = 0)x16 Origination (ORG = 1)Address 1,2DataRequiredClock CyclesAddress 1,3DataRequired Clock CyclesREAD Read Data from Memory 110A8-A0Q7-Q0A7-A0Q15-Q0WRITE Write Data to Memory101A8-A0D7-D020A7-A0D15-D027EWEN Erase/Write Enable 100 1 1XXXXXXX 1211XX XXXX 11EWDS Erase/Write Disable 1000 0XXX XXXX 1200XX XXXX 11ERASE Erase Byte or Word 111A8-A012A7-A011ERAL Erase All Memory 100 1 0XXX XXXX 1210XX XXXX 11WRALWrite All Memory with same Data1000 1XXX XXXXD7-D02001XX XXXXD15-D027Instruc tionDescriptionStart bit Op-Codex8 Origination (ORG = 0)x16 Origination (ORG = 1)Address1,2DataRequiredClock CyclesAddress 1,3DataRequiredClock CyclesREAD Read Data from Memory 110A10-A0Q7-Q0A9-A0Q15-Q0WRITE Write Data to Memory101A10-A0D7-D022A9-A0D15-D029EWEN Erase/Write Enable 10011X XXXX XXXX 1411 XXXX XXXX 13EWDS Erase/Write Disable 10000X XXXX XXXX 1400 XXXX XXXX 13ERASE Erase Byte or Word 111A10-A014A9-A013ERAL Erase All Memory 10010X XXXX XXXX 1410 XXXX XXXX 13WRALWrite All Memory with same Data10001X XXXX XXXXD7-D02201 XXXX XXXXD15-D029M93C86, M93C76, M93C66, M93C56, M93C468/31ReadThe Read Data from Memory (READ) instruction outputs data on Serial Data Output (Q). When the instruction is received, the op-code and address are decoded, and the data from the memory is transferred to an output shift register. A dummy 0bit is output first, followed by the 8-bit byte or 16-bit word, with the most significant bit first. Output data changes are triggered by the rising edge of Serial Clock (C). The M93Cx6 automatically incre-ments the internal address register and clocks out the next byte (or word) as long as the Chip Select Input (S) is held High. In this case, the dummy 0 bit is not output between bytes (or words) and a con-tinuous stream of data can be read.Erase/Write Enable and DisableThe Erase/Write Enable (EWEN) instruction en-ables the future execution of erase or write instruc-tions, and the Erase/Write Disable (EWDS)instruction disables it. When power is first applied,the M93Cx6 initializes itself so that erase and write instructions are disabled. After an Erase/Write En-able (EWEN) instruction has been executed, eras-ing and writing remains enabled until an Erase/Write Disable (EWDS) instruction is executed, or until V CC falls below the power-on reset threshold voltage. To protect the memory contents from ac-cidental corruption, it is advisable to issue the Erase/Write Disable (EWDS) instruction after ev-ery write cycle. The Read Data from Memory (READ) instruction is not affected by the Erase/Write Enable (EWEN) or Erase/Write Disable (EWDS) instructions.M93C86, M93C76, M93C66, M93C56, M93C46EraseThe Erase Byte or Word (ERASE) instruction sets the bits of the addressed memory byte (or word) to 1. Once the address has been correctly decoded, the falling edge of the Chip Select Input (S) starts the self-timed Erase cycle. The completion of the cycle can be detected by monitoring the Ready/READY/BUSY STA-TUS section.WriteFor the Write Data to Memory (WRITE) instruction, 8 or 16 data bits follow the op-code and address bits. These form the byte or word that is to be writ-ten. As with the other bits, Serial Data Input (D) is sampled on the rising edge of Serial Clock (C).After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or after this specific time frame, the self-timed programming cycle will not be started, and the addressed location will not be programmed. The completion of the cycle can be described later in this document.Once the Write cycle has been started, it is inter-nally self-timed (the external clock signal on Serial Clock (C) may be stopped or left running after the start of a Write cycle). The cycle is automatically preceded by an Erase cycle, so it is unnecessary to execute an explicit erase instruction before a Write Data to Memory (WRITE) instruction.9/31M93C86, M93C76, M93C66, M93C56, M93C4610/31Erase AllThe Erase All Memory (ERAL) instruction erases the whole memory (all memory bits are set to 1).The format of the instruction requires that a dum-my address be provided. The Erase cycle is con-ducted in the same way as the Erase instruction (ERASE). The completion of the cycle can be de-scribed in the READY/BUSY STATUS section.Write AllAs with the Erase All Memory (ERAL) instruction,the format of the Write All Memory with same Data (WRAL) instruction requires that a dummy ad-dress be provided. As with the Write Data to Mem-ory (WRITE) instruction, the format of the Write All Memory with same Data (WRAL) instruction re-quires that an 8-bit data byte, or 16-bit data word,be provided. This value is written to all the ad-dresses of the memory device. The completion of the cycle can be detected by monitoring theNote:For the meanings of Xn and Dn, please see Table 5., Table 6. and Table 7..READY/BUSY STATUSWhile the Write or Erase cycle is underway, for a WRITE, ERASE, WRAL or ERAL instruction, the Busy signal (Q=0) is returned whenever Chip Se-lect Input (S) is driven High. (Please note, though, that there is an initial delay, of t SLSH, before this status information becomes available). In this state, the M93Cx6 ignores any data on the bus. When the Write cycle is completed, and Chip Se-lect Input (S) is driven High, the Ready signal (Q=1) indicates that the M93Cx6 is ready to re-ceive the next instruction. Serial Data Output (Q) remains set to 1 until the Chip Select Input (S) is brought Low or until a new start bit is decoded. COMMON I/O OPERATIONSerial Data Output (Q) and Serial Data Input (D) can be connected together, through a current lim-iting resistor, to form a common, single-wire data bus. Some precautions must be taken when oper-ating the memory in this way, mostly to prevent a short circuit current from flowing when the last ad-dress bit (A0) clashes with the first data bit on Se-rial Data Output (Q). Please see the application note AN394 for details. CLOCK PULSE COUNTERIn a noisy environment, the number of pulses re-ceived on Serial Clock (C) may be greater than the number delivered by the master (the microcontrol-ler). This can lead to a misalignment of the instruc-tion of one or more bits (as shown in Figure 7.) and may lead to the writing of erroneous data at an er-roneous address.To combat this problem, the M93Cx6 has an on-chip counter that counts the clock pulses from the start bit until the falling edge of the Chip Select In-put (S). If the number of clock pulses received is not the number expected, the WRITE, ERASE, ERAL or WRAL instruction is aborted, and the contents of the memory are not modified.The number of clock cycles expected for each in-struction, and for each member of the M93Cx6 family, are summarized in Table 5. to Table 7.. For example, a Write Data to Memory (WRITE) in-struction on the M93C56 (or M93C66) expects 20 clock cycles (for the x8 organization) from the start bit to the falling edge of Chip Select Input (S). That is:1 Start bit+ 2 Op-code bits+ 9 Address bits+ 8 Data bitsMAXIMUM RATINGStressing the device above the rating listed in the Absolute Maximum Ratings" table may cause per-manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im-plied. Exposure to Absolute Maximum Rating con-ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu-ments.Table 8. Absolute Maximum RatingsNote: pliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK ® 7191395 specification, andthe European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2.JEDEC Std JESD22-A114A (C1=100pF, R1=1500 Ω, R2=500 Ω)Symbol ParameterMin.Max.Unit T STG Storage Temperature–65150°C T LEAD Lead T emperature during Soldering See note 1°C V OUT Output range (Q = V OH or Hi-Z)–0.50V CC +0.5V V IN Input range –0.50V CC +1V V CC Supply Voltage–0.50 6.5V V ESDElectrostatic Discharge Voltage (Human Body model) 2–40004000VDC AND AC PARAMETERSThis section summarizes the operating and mea-surement conditions, and the DC and AC charac-teristics of the device. The parameters in the DC and AC Characteristic tables that follow are de-rived from tests performed under the Measure-ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame-ters.Table 9. Operating Conditions (M93Cx6)Table 10. Operating Conditions (M93Cx6-W)Table 11. Operating Conditions (M93Cx6-R)Symbol ParameterMin.Max.Unit V CCSupply Voltage4.55.5V T AAmbient Operating Temperature (Device Grade 6)–4085°C Ambient Operating Temperature (Device Grade 7)–40105°C Ambient Operating Temperature (Device Grade 3)–40125°CSymbol ParameterMin.Max.Unit V CCSupply Voltage2.5 5.5V T AAmbient Operating Temperature (Device Grade 6)–4085°C Ambient Operating Temperature (Device Grade 7)–40105°C Ambient Operating Temperature (Device Grade 3)–40125°CSymbol ParameterMin.Max.Unit V CC Supply Voltage1.8 5.5V T AAmbient Operating Temperature (Device Grade 6)–4085°CTable 12. AC Measurement Conditions (M93Cx6)Note: 1.Output Hi-Z is defined as the point where data out is no longer driven.Table 13. AC Measurement Conditions (M93Cx6-W and M93Cx6-R)Note: 1.Output Hi-Z is defined as the point where data out is no longer driven.Table 14. CapacitanceNote:Sampled only, not 100% tested, at T A =25°C and a frequency of 1MHz.Symbol Parameter Min.Max.Unit C LLoad Capacitance 100pFInput Rise and Fall Times 50ns Input Pulse Voltages0.4V to 2.4V V Input Timing Reference Voltages 1.0V and 2.0V V Output Timing Reference Voltages0.8V and 2.0VVSymbol Parameter Min.Max.Unit C LLoad Capacitance 100pFInput Rise and Fall Times 50ns Input Pulse Voltages0.2V CC to 0.8V CC V Input Timing Reference Voltages 0.3V CC to 0.7V CC V Output Timing Reference Voltages0.3V CC to 0.7V CCVSymbol ParameterTest Condition MinMax Unit C OUT OutputCapacitance V OUT = 0V 5pF C INInputCapacitanceV IN = 0V5pFNote: 1.Current product: identified by Process Identification letter F or M.2.New product: identified by Process Identification letter W or G or S.Table 16. DC Characteristics (M93Cx6, Device Grade 7 or 3)Note: 1.Current product: identified by Process Identification letter F or M.2.New product: identified by Process Identification letter W or G or S.I LI Input Leakage Current 0V ≤ V IN ≤ V CC±2.5 µA I LOOutput Leakage Current0V ≤ V OUT ≤ V CC , Q in Hi-Z ±2.5 µA I CCSupply CurrentV CC = 5V, S = V IH , f = 1 MHz, CurrentProduct 11.5 mA V CC = 5V, S = V IH , f = 2 MHz, NewProduct 22 mA I CC1Supply Current (Stand-by)V CC = 5V , S = V SS , C = V SS ,ORG = V SS or V CC , Current Product 150µAV CC = 5V , S = V SS , C = V SS , ORG = V SS or V CC , New Product 215 µAV IL Input Low Voltage V CC = 5V ± 10%–0.450.8 V V IH Input High Voltage V CC = 5V ± 10%2V CC + 1 V V OL Output Low Voltage V CC = 5V, I OL = 2.1mA 0.4 V V OHOutput High VoltageV CC = 5V , I OH = –400µA2.4VSymbol ParameterTest Condition Min.Max.Unit I LI Input Leakage Current 0V ≤ V IN ≤ V CC±2.5 µA I LOOutput Leakage Current0V ≤ V OUT ≤ V CC , Q in Hi-Z ±2.5µAI CCSupply CurrentV CC = 5V, S = V IH , f = 1 MHz, CurrentProduct 11.5 mA V CC = 5V, S = V IH , f = 2 MHz, NewProduct 22 mA I CC1Supply Current (Stand-by)V CC = 5V , S = V SS , C = V SS ,ORG = V SS or V CC , Current Product 150 µA V CC = 5V , S = V SS , C = V SS , ORG = V SS or V CC , New Product 215 µA V IL Input Low Voltage V CC = 5V ± 10%–0.450.8 V V IH Input High Voltage V CC = 5V ± 10%2V CC + 1 V V OL Output Low Voltage V CC = 5V, I OL = 2.1mA 0.4 V V OHOutput High VoltageV CC = 5V , I OH = –400µA2.4V。