DesignCon 2011
Signal and Power Integrity for a 1600 Mbps DDR3 PHY in Wirebond Package June Feng, Rambus Inc.
[Email: jfeng@https://www.doczj.com/doc/3d945998.html,]
Ralf Schmitt, Rambus Inc.
Hai Lan, Rambus Inc.
Yi Lu, Rambus Inc.
Abstract
A DDR3 interface for a data rate of 1600MHz using a wirebond package and a low-cost system environment typical for consumer electronics products was implemented. In this environment crosstalk and supply noise are serious challenges and have to be carefully optimized to meet the data rate target. We are presenting the signal and power integrity analysis used to optimize the interface design and guarantee reliable system operation at the performance target under high-volume manufacturing conditions. The resulting DDR3 PHY was implemented in a test chip and achieves reliable memory operations at 1600MHz and beyond.
Authors Biography
June Feng received her MS from University of California at Davis, and BS from Beijing University in China. From 1998 to 2000, she was with Amkor Technology, Chandler, AZ. She was responsible for BGA package substrate modeling and design and PCB characterization. In 2000, she joined Rambus Inc and is currently a senior member of technical staff. She is in charge of performing detailed analysis, modeling, design and characterization in a variety of areas including high-speed, low cost PCB layout and device packaging. Her interests include high-speed interconnects modeling, channel VT budget simulation, power delivery network modeling and high-frequency measurements.
Ralf Schmitt received his Ph.D. in Electrical Engineering from the Technical University of Berlin, Germany. Since 2002, he is with Rambus Inc, Los Altos, California, where he is a Senior Manager leading the SI/PI group, responsible for designing, modeling, and implementing Rambus multi-gigahertz signaling technologies. His professional interests include signal integrity, power integrity, clock distribution, and high-speed signaling technologies.
Hai Lan is a Senior Member of Technical Staff at Rambus Inc., where he has been working on on-chip power integrity and jitter analysis for multi-gigabit interfaces. He received his Ph.D. in Electrical Engineering from Stanford University, M.S. in Electrical and Computer Engineering from Oregon State University, and B.S. in Electronic Engineering from Tsinghua University in 2006, 2001, and 1999, respectively. His professional interests include design, modeling, and simulation for mixed-signal integrated circuits, substrate noise coupling, power and signal integrity, and high-speed interconnects.
Yi Lu is a senior systems engineer at Rambus Inc. He received the B.S. degree in electrical engineer and computer science from U.C. Berkeley in 2002 with honors. In 2004, he received the M.S. degree in electrical engineering from UCLA, where he designed and fabricated a 3D MEMS microdisk optical switch. Since joining Rambus in 2006, he has been a systems engineer designing various memory interfaces including XDR1/2 and DDR2/3.
Introduction
The memory bandwidth requirement of multimedia consumer electronic products like HDTV systems is constantly increasing, driven by the adoption of advanced features like frame rate up-scaling and 3D projection. At the same time, consumer electronic products remain very cost sensitive, targeting low-cost package and system environment to reduce the overall bill of materials. This creates the need for high-speed memory interfaces implemented in low-cost system environments. In order to address this need we have designed a 1600 Mbps DDR3 memory interface PHY in a wirebond package targeting a low-cost system environment with a 4-layer PCB stack-up typical for cost-optimized consumer electronic products.
Designing a DDR3 memory interface for such a high data rate is not trivial. The memory device itself requires more than 40% of the bit time for internal timing, leaving little more than half of the bit time for all channel and PHY timing errors. Meeting these requirements in a wirebond package, using a 4-layer PCB stackup, is a serious challenge. Bond wire coupling in the package and coupling in the PCB routing, which only allows a microstrip routing in a 4-layer stackup, lead to increased crosstalk in the interface system. Additionally, the bond wire inductance leads to higher supply noise, causing power supply induced jitter (PSIJ) as well as simultaneous switching output (SSO) noise in the interface system. The interface design therefore requires a careful optimization of signal and power integrity in the entire system, from the controller PHY to the DRAM component pin.
In this paper we will present the signal and power integrity analysis used to optimize the interface design and assuring reliable operation at the target data rate in a low-cost system environment. First we will present the analysis of power supply induced jitter. For this, we analyzed the supply noise spectrum generated in the system and the sensitivity of the system to this noise. With this analysis we were able to predict and optimize the jitter in the PHY, making sure the PHY will meet the tight jitter requirements of the DRAM device.
Next we analyze the channel margin loss due to ISI, crosstalk, and SSO. Special emphasize is given to crosstalk and SSO noise, since these are the major contribution to margin loss in the channel timing. A careful optimization of PHY floor plan, package design, and PCB routing was implemented to minimize the margin loss due to crosstalk and SSO.
Finally, the system timing was verified for the full range of process variations of the controller PHY and channel parameter variations for low-cost system environments typical for cost-sensitive consumer electronics products. This analysis provides the confidence that the final system will meet the target performance with high yield under High-Volume Manufacturing conditions.
The DDR3 PHY was implemented on a test chip and achieves reliable memory operation for a data rate of 1866 Mbps using DDR3 memories of a 1600 Mbps speed grade.
I.System Environment and SI/PI Challenges
The design target of the DDR3 PHY described in this paper are high-performance consumer electronic systems with a bandwidth requirement of up to 6.4GB/s in a low-cost system environment. This bandwidth is achieved using a x32 PHY running at a data rate of 1600Mbps.
In order to support a low system cost implementation, the PHY was designed in a 4-layer wirebond package. Such a package is significantly less expensive than flip-chip packages, however it poses challenges for signal and power integrity especially at higher data rates. Additionally, the PHY is designed for a PCB with only 4 layers, further reducing the final system cost. Finally, silicon area, pad count, and decoupling requirements are carefully optimized to minimize total system cost for the memory subsystem.
The goal for this design effort was to achieve a PHY implementation that will reliable achieve the targeted data rate under high volume manufacturing (HVM) conditions using any DDR3 DRAM meeting the JEDEC spec at the targeted data rate. In order to meet this goal it was not enough to design and analyze the PHY alone. Instead, the PHY had to be analyzed in the targeted system environment, optimizing system and PHY implementation concurrently. Closing the voltage and timing budget on the system level resulted in PHY design requirements necessary to achieve the targeted interface system performance in the final implementation using a low-cost system environment.
Creating a cost-efficient high-speed memory interface requires careful analysis of power and system integrity [1]. The bond wires in a wirebond package contribute significantly to the inductance of the power distribution network (PDN) of the interface. Inductance in the supply path causes supply noise when the current dissipation of the PHY is changing. This supply noise causes voltage distortions and timing variations, generating timing jitter on interface signals as well as internal PHY signals. The contribution of bond wires to the supply inductance can be reduced by adding additional supply pads to the design, but this would increase the PHY width and ultimately increase the PHY cost and is therefore not advisable. Instead, the number and placement of supply bond wires has to be carefully optimized to achieve the necessary supply noise targets in the design.
Bond wires also lead to crosstalk between different signal lines. This is a severe signal integrity challenge especially at higher data rate as targeted for this design. Routing the signaling channel on a 4-layer PCB only allows for microstrips instead of striplines, which adds further crosstalk to the signaling channel. As a result, crosstalk is a major signal integrity challenge for the implementation of a high-speed DDR3 interface in this low-cost system environment, and the PHY design has to meet tight timing and voltage requirements to allow for the distortions added in the package and the PCB routing channel.
II.Power Integrity Analysis
II.1.Power Integrity Challenges
Power Integrity is an important design consideration for high-speed interfaces. Supply noise in the PHY causes waveform distortions and delay variations, resulting in jitter, on interface signals and internal signals inside the PHY. Designing a high-speed interface system in a low-cost 4-layer wirebond package is particular challenging, since the supply inductance of such packages is comparably high and the bond wires allow rail-to-rail coupling between noisy digital supplies and very noise sensitive analog supplies. In order to achieve a high data rate it is therefore necessary to carefully analyze supply noise and its impact on the PHY circuits and interface characteristics.
In general, there are two Power Integrity challenges in the design of high-speed interface systems that are best analyzed separately.
The first power integrity challenge in high-speed interfaces is the distortion of signal quality and timing of the interface signals during Simultaneous Switching Outputs (SSO) events. SSO noise is a common problem in interface systems using single-ended signaling like DDR3 and it is discussed in detail in previous works [5]. Since the impact of SSO is strongly influenced by the interaction of the interface PHY with the external channel implementation in package and PCB, we will discuss SSO impact as part of the channel analysis. It is analyzed using a signal and power integrity co-simulation model described in a later chapter.
The second challenge is the supply noise inside the PHY cause by the circuit activity of the PHY itself. This activity generates noise on all supply rails inside the PHY, including sensitive analog supplies, due to self-induced current changes or noise coupling from other system elements. This supply noise affects the performance of circuits inside the PHY, and in particular, it creates jitter in the timing circuits controlling the internal and channel timing of the interface system. The impact of power supply induced jitter (PSIJ) on the system margin of the interface has to be carefully analyzed and optimized to ensure reliable operation at the target data rate.
In a DDR3 interfaces the timing on the DQ data bus is most critical, since these signals are transmitted at the full (double) data rate. The critical timing parameters on this bus are defined relative to data strobe signals, DQS. As a result, jitter that is shared between the DQ data signals and the DQS strobe signal is not affecting the system timing margin. This is particularly helpful during WRITE access, when both the DQ and DQS signals are generated in the PHY. Only PSIJ components due to DQ and DQS mismatches have to be taken into consideration for this operation. This mismatch can be minimized with a careful design of the timing paths inside the PHY.
The clock signal, CK, generated by the PHY acts as a timing reference source for the internal DRAM timing and has to meet various jitter requirements defined in the DRAM specification. It also acts as timing reference for the control and address signals on the CA bus, but timing requirements on this bus are less critical since the CA bus only operates at half the data rate of the DQ bus. Meeting the jitter requirements of the DRAM specification, however, is not necessarily sufficient to operate the DDR3 interface at high
data rates. Jitter on the CK signal increases the output hold time parameter tQH of the DRAM device, reducing system margin during READ operations. It is therefore advisable to keep jitter on the CK signal very low, if possible even lower than required by the DRAM specification, to gain system margin during READ access. In the following chapter we will present a detailed PSIJ analysis for the CK signal path inside the PHY. II.2.Power Supply Model and Simulation Results
The prediction of power supply noise plays a vitally important role in defining the voltage and timing budget for this low-cost wirebond DDR3 PHY design targeting at 1600Mbps up to 1866Mbps. Besides the common concern on the dynamic range of the supply noise, it is also crucial to understand the supply noise impact on the system timing jitter, or, power supply noise induced jitter (PSIJ). Previously, a systematic approach for predicting PSIJ by combining the supply noise spectrum and the clocking circuit jitter sensitivity has been developed [2]. The methodology flow is shown in Figure 1. In order to estimate the supply noise impact on jitter, this method seeks to obtain the jitter spectrum, J(f), which in turn can be obtained by multiplying the supply noise spectrum, V(f), and jitter sensitivity profile, S(f), all in frequency domain. The jitter sensitivity profile is solely determined by the circuit realization and independent of the circuit activity. On the other side, the supply noise spectrum is determined by both the power delivery network and the current profile, a variable depending on different circuit activity and data pattern. The following sections will first describe the supply noise analysis to obtain V(f) and then discuss the jitter sensitivity results of S(f) so that the final prediction of PSIJ in the DDR3 system can be evaluated. Four supplies are used in the implemented DDR3 test system, including VDDP, VDDA, VDDIO, and VDDR. The PLL is supplied by the dedicated VDDP supply. The clock distribution circuits operate on VDDA. The I/O circuits use VDDIO. The rest of the circuits, mainly the digital logic circuits for the data path, operate on VDDR. Since the entire clocking circuits are on VDDP, VDDA, and VDDR, it is expected that the main jitter contribution comes from the noise on these three supplies. The following discussions will focus on these three supplies, which are highly jitter sensitive.
Figure 1. Methodology for predicting supply noise impact on jitter (PSIJ) [2].
V
Off-Chip PDN On-Chip PDN Current Profile
Figure 2. Power supply model for pre-layout supply noise simulation.
Figure 2 shows the power supply model topology used for the supply noise analysis. As shown in the figure, three components are required including off-chip PDN, on-chip PDN, and supply current profile. The off-chip PDN is modeled by passive RLC components resulting from voltage regulator, PCB, and package parasitics as well as low and medium frequency decoupling capacitors. The on-chip PDN represents the physical power grids from die pads to rest of the chip, typically includes RC parasitics and very importantly, on-chip decaps. The third component is the current profile, which is extracted from the circuit simulation and applied as the stimulus to the PDN. In order to evaluate both the worst-case switching noise and the steady state supply noise, it is desired to have the current profile extracted under the DDR3 PHY operating condition for bus turn-around. Figure 3 shows the data waveform under a WRITE-NOP-READ bus turn-around condition as well as the corresponding current profiles for VDDR, VDDA, and VDDP supplies. As can be seen from the figure, the VDDA and VDDP current profiles are independent of the operation modes while average VDDR current shifts significantly between the active WRITE/READ mode and the NOP mode.
WRITE
READ NOP avg=21mA
peak=32mA avg=163mA
peak=638mA avg=102mA
peak=599mA avg=165mA peak=655mA
avg=102mA peak=596mA
avg=21mA peak=32mA
avg=21mA peak=32mA avg=115mA peak=622mA avg=102mA peak=597mA 80 back-to-back PRBS, BL=4
~300ns 80 back-to-back PRBS, BL=4~300ns
Figure 3: Supply current profiles for bus turn-around, representing 300ns of continuous WRITE and 300ns
of continuous READ with 150ns NOP in between.
vddr 10.2 mV pp 10.4 mV pp 18.8 mV pp ~20mV DC shift 4.4 mV pp 18.7 mV pp
4.2 mV pp
Due to Standby/Active
Power Mode Transition
vdda
vddp
WRITE
READ NOP
Figure 4: Overview of VDDR, VDDA, and VDDP supply noise for the DDR test system.
The power supply noise analysis is performed by applying the above current profiles to the power supply model shown in Figure 2. The overview of the supply noise simulation results are summarized in Figure 4. As the dedicated supply to PLL alone, the VDDP noise , independent of the activity mode, is around 5mVpp and. Comparing to the VDDP noise, the VDDA noise is significantly higher at around 19mVpp due to the strong switching activity generated by the clock buffers in the clock distribution circuits. The VDDA noise is also independent of activity mode and it remains stable as long as the clock distribution stays on. The VDDR noise exhibits strong dependence on mode of operation. The VDDR supply experiences significant DC IR shift between the active WRITE/READ mode and the non-active NOP mode. What matter the most are the switching noise during the transitions between the active and non-active operation modes and the steady state noise during the normal active modes for continuous WRITE or READ operation. The former usually leads to the worst-case supply voltage collapse and the latter determines how much net jitter impact it has on the timing budget of the system. As shown by the figure, the bus turn-around switching noise is as high as 25mVpp and the steady state noise is around 10mVpp. As will be discussed shortly, VDDP has the highest jitter sensitivity followed by VDDA and VDDR while its supply noise is relatively small. The net jitter contributions from the supply noise on each of these domains are discussed in the following sections.
Figure 5-7 shows the details of the simulated supply noise in time-domain and frequency-domain under WRITE and READ conditions. The VDDR simulation results are shown in Figure 5, where the time-domain results indicate that the peak-to-peak noise is around 10mV. The noise spectrum results show that the major component is at the 1066MHz data rate, with sub-harmonic at 533MHz, and its higher-order harmonics. The obtained noise spectrum will be used to compute the PSIJ impact. Similarly, the VDDA simulation results in Figure 6 show that the swing is around 19mV with major frequency components are at 533MHz and 1066MHz. The VDDP noise simulation results are shown in Figure 7. The peak-to-peak noise is around 5mV and the frequency components are the PLL reference clock, its output clock and their higher-order harmonics.
10.2 mVpp 8.2 mVpp
10.4 mVpp
(a) (b)
Data rate @1066MHz TX/RX CLK
@533MHz
LF/MF noise Data rate @1066MHz
TX/RX CLK
@533MHz LF/MF noise
(c) (d) Figure 5: Simulation results of VDDR supply noise. (a)Supply noise during WRITE, (b)Supply noise during READ, (c)Spectrum of supply noise during WRITE, and (d)Spectrum of supply noise during READ. 18.8 mVpp 18.7 mVpp
(a) (b) TX/RX CLK
@533MHz LF/MF noise Data rate
@1066MHz HF Data rate @1066MHz
TX/RX CLK @533MHz LF/MF noise
HF
(c) (d)
Figure 6. Simulation results of VDDA supply noise. (a)Supply noise during WRITE, (b)Supply noise during READ, (c)Spectrum of supply noise during WRITE, and (d)Spectrum of supply noise during
READ.
4.4 mVpp 4.2 mVpp
(a) (b) half CK freq
@266MHz
LF/MF noise VCO freq harmonics
REFCLK @133MHz
CK
@533MHz
half CK freq
@266MHz
LF/MF noise
VCO freq
harmonics
REFCLK
@133MHz
CK
@533MHz (c) (d)
Figure 7. Simulation results of VDDP supply noise. (a)Supply noise during WRITE, (b)Supply noise during READ, (c)Spectrum of supply noise during WRITE, and (d)Spectrum of supply noise during
READ.
II.3.Jitter Sensitivity and Jitter Spectrum
PSIJ sensitivity is defined in frequency domain as the system jitter response to sinusoidal supply noise. Its magnitude profile represents how much jitter is induced by the supply noise with one unit of swing. Its phase profile represents how much phase difference between the supply noise and its induced jitter sequence in the steady state. The PSIJ sensitivity is solely determined by the circuit implementation and is independent of different circuit activity. Therefore, it is a system transfer function for characterizing the jitter impact induced by the supply noise. It serves as a key linking parameter between the supply noise as the stimulus and the jitter impact as the output response. The PSIJ sensitivity extraction methodology has been previously reported in [2]. It is applied here to extract the CK PSIJ sensitivity profiles for the DDR3 test system. The PSIJ sensitivity results for VDDR, VDDA, and VDDP are shown in Figure 8(a)-(c), respectively. As seen in the figure, the PSIJ sensitivity of VDDR and VDDA are relatively lower than that of VDDP. This is expected since the most sensitive block in the entire clocking path is the PLL circuit, which is solely supplied by VDDP. The VDDP sensitivity, as shown in Figure 8(c), exhibits a band-pass behavior with its peak of about 1ps/mV at around 10MHz, which roughly corresponds to the PLL loop bandwidth. The VDDA sensitivity, as shown in Figure 8(b), exhibits a low-pass behavior. This is also expected because VDDA supplies the entire clock distribution circuitry, where the major jitter sensitivity characteristic is due to the clock buffer delay change caused by the supply voltage variation, up to the circuit bandwidth.
(a) (b) (c)
Figure 8: Simulated DDR3 PSIJ sensitivity profiles for (a)VDDR, (b)VDDA, and (c)VDDP The final PSIJ is derived by combing the PSIJ sensitivity, S(f), and the supply noise spectrum, V(f). Each of these two required components has been addressed as above. One can compute the jitter spectrum J(f) as follows:
S
f
J(Eq. 1)
(f
f
V
)
)
(
(
)
The above jitter spectrum is a comprehensive characterization on the supply noise impact on jitter. It reveals magnitude and location of all the jitter components and relates their sources to the supply noise frequency components. It quantifies what frequency components of the supply noise make the most significant contribution to the final jitter impact. Moreover, the jitter spectrum serves as the basis to derive many important aspects of the jitter. For example, the time-domain jitter sequence is computed as follows:
S
V
f
ifft
f
t j(Eq. 2)
ifft
J
)]
)
)(f
)]
(
(
[
(
[
By applying the above procedure, the jitter induced by the supply noise is derived to estimate the PSIJ contribution to the total jitter in the test DDR3 system. The results are summarized in Figures 9-11. Figure 9 shows the VDDR PSIJ prediction results for continuous WRITE and READ modes. Figure 9(a) is the simulated jitter spectrum due to the VDDR noise during WRITE, showing that the major jitter components are at the CK frequency and the data rate. The corresponding time-domain jitter sequence is computed by using Eq.2 and is shown in Figure 9(c). From the figure, the peak-to-peak jitter is found to be around 3.3ps. Figure 9(e) further shows the histogram of the jitter sequence so that the PSIJ statistical property can be revealed, e.g., distribution form, peak-to-peak value, and deviation, etc. Similarly, the VDDR PSIJ results under READ condition in terms of jitter frequency-domain spectrum, time-domain sequence, and statistical histogram are shown in Figure 9(b)(d)(f). The peak-to-peak jitter for READ is found to be around 2.9ps, which is slightly less than that in WRITE. Figure 10(a)-(f) show the VDDA PSIJ results. Although it is expected that the results are independent on WRITE or READ, the results under these two conditions are shown in the figure as a sanity check. As seen from the figure, the major jitter components are at the CK frequency at 533MHz and its 2nd harmonic at 1066MHz. The peak-to-peak jitter is found to be around 2.4ps for WRITE and 2.2ps for READ. Figure 11(a)-(f) show the VDDP PSIJ results. Although the VDDP has the highest jitter sensitivity, the noise in its supply domain is not as big as those in VDDR or VDDA. As a result, the peak-to-peak jitter due to VDDP
noise is found to be about 1.8ps for WRITE and 2.0ps for READ. The major jitter contribution comes from the PLL reference clock at 133MHz as well as its 2nd and 3rd harmonics.
(a) (b)
(c) (d)
(e) (f)
Figure 9: Simulated vddr PSIJ results for continuous WRITE and READ. (a) Spectrum of jitter induced by VDDR noise during WRITE, (b)Spectrum of jitter induced by vddr noise during READ, (c)VDDR PSIJ jitter sequence during WRITE, (d)VDDR PSIJ sequence during READ, (e) VDDR PSIJ histogram during
WRITE, and (f)VDDR PSIJ histogram during READ.
(a) (b)
(c) (d)
(e) (f)
Figure 10: Simulated vdda PSIJ results for continuous WRITE and READ. (a) Spectrum of jitter induced by VDDA noise during WRITE, (b)Spectrum of jitter induced by VDDA noise during READ, (c)VDDA PSIJ jitter sequence during WRITE, (d)VDDA PSIJ sequence during READ, (e) VDDA PSIJ histogram during WRITE, and (f)VDDA PSIJ histogram during READ.
(a) (b)
(c) (d)
(e) (f)
Figure 11: Simulated vddp PSIJ results for continuous WRITE and READ. (a) Spectrum of jitter induced by VDDA noise during WRITE, (b)Spectrum of jitter induced by VDDA noise during READ, (c)VDDA PSIJ jitter sequence during WRITE, (d)VDDA PSIJ sequence during READ, (e) VDDA PSIJ histogram during WRITE, and (f)VDDA PSIJ histogram during READ.
Although the above PSIJ results represent the steady state activity mode for continuous WRITE or READ, it is also important to estimate the worst-case pathological jitter impact. Since neither VDDA nor VDDP noise should be dependent on the activity mode, the major variable in noise source is the VDDR noise. However, the basis to construct such cases is not the supply noise spectrum itself. Instead, the determining factor is the peak jitter sensitivity frequency location. As suggested by the VDDR PSIJ sensitivity shown in Figure 8(a), the peaking occurs at 5~10MHz with about 0.5ps/mV. Therefore, the worst-case VDDR PSIJ should occur when the VDDR supply noise has major components at 5~10MHz. Such case can be emulated by stitching the active mode current profile with the non-active mode current profile with a repetition rate of 5MHz. Figure 12 shows the PSIJ results under such conditions. Figure 12(a) and (b) show the VDDR supply noise waveforms for pathological WRITE-NOP and READ-NOP cases. The DC shift is about 20mV between the active and non-active mode and the peak-to-peak noise is about 25mV. The corresponding PSIJ jitter spectrum are plotted in Figure 12(c) and (d), showing jitter components as high as 10ps in magnitude at 5MHz. The resulting jitter sequences are plotted in Figure 12(e) and (f), where the significant 5MHz jitter component as well as its 10MHz harmonics can be clearly seen. Recall that the peak-to-peak supply noise for active mode is about 19mV during normal continuous WRITE or READ and the resulting PSIJ is about 3.3ps. In the pathological case, the peak-to-peak supply noise is about 25mV, which is 1.3x larger than that in the normal active mode. But the resulting jitter is about 34ps, which is 10x higher than that in the normal active mode. The constructed pathological case is thus useful to estimate the worst-case or upper bound of the PSIJ impact in the system.
~20mV DC shift WR WR WR WR WR NOP NOP NOP NOP 200ns NOP 100ns 100ns NOP 100ns 200ns
RE RE RE RE RE
NOP
NOP NOP NOP
100ns
Figure 12: Worst-case vddr PSIJ estimation. (a)Worst-case of WRITE-NOP with 5MHz repetition rate, (b)READ-NOP with 5MHz repetition rate, (c)VDDR PSIJ spectrum for worst case WRITE-NOP,
(d)VDDR PSIJ spectrum for worst case READ-NOP, (e) VDDR PSIJ sequence under worst-case WRITE-
NOP, and (f)VDDR PSIJ sequence under worst-case READ-NOP.
With the above PSIJ results, it is now possible to understand the relative significance of jitter impact due to various supply noise sources as well as the net PSIJ contribution to the overall timing jitter. Table 1 summarizes the PSIJ impact in the DDR3 test system, including the simulated results for DDR3 at 1066Mbps as well as the extrapolated results
for DDR3 at 1600Mbps and 1866Mbps. For 1066Mbps operation, the net PSIJ impact to the overall timing jitter is about 0.81% and 0.73% of UI for normal continuous WRITE and READ modes, respectively. In each case, the VDDR noise has the biggest jitter impact, followed by VDDA and VDDP. Under the pathological cases, the VDDA and VDDP jitter impact remain the same but the VDDR jitter impact significantly increases. As can be seen in Table 1, the VDDR PSIJ impact increases from less than 0.35% of UI to as high as 3.5% of UI, a 10x increase over the normal active mode. By extrapolation, under the normal active mode the total PSIJ impact is predicted to account for 1.2% of an UI for 1600Mbps and 1.4% of an UI for 1866Mbps. Under the pathological cases, the total PSIJ impact is predicted to account for 6.1% of an UI for 1600Mbps and 7.1% of an UI for 1866Mbps. The results simulated or extrapolated here will be used for the overall timing budget analysis for the DDR3 test system, to be discussed in following sections. III.Channel Analysis and Signal Integrity
The target of our design project was to generate a PHY that will reliably achieve the target data rate of 1600Mbps in a customer system. In order to achieve this target we have to analyze the performance of the PHY in the target system environment.
It is common practice in the design of high-speed interfaces to define a voltage and timing budget (VT budget) that accounts for all timing and voltage uncertainties introduced by the various interface components in the system. The VT budget of the system is balanced at a given data rate if the sum of all timing errors is smaller than the bit time at the target data rate and the sum of all voltage errors is smaller than the initial voltage swing of the signaling system. Based on a balanced system VT budget, specifications can be derived for the different components of the interface system, assigning budgets of maximum voltage and timing error to each of the components.
In a DDR3 interface system, the DRAM specification defines the voltage and timing uncertainty of the memory device at the target data rate. Additional voltage and timing errors are introduced by the passive channel between the controller and DRAM devices and by the controller PHY itself. The channel analysis of the target system allows us to quantify the voltage and timing error introduced by the channel and to define design specifications the controller PHY has to meet in order to close the system VT budget.
Channel timing and voltage errors can be caused by many effects. We will break down our analysis into four separate analysis steps, each of them targeting a different source of channel errors that can be addressed and optimized separately. The first analysis investigates inter symbol interference (ISI) effects on a single data lane under nominal conditions. The second analysis targets crosstalk (Xtalk) between different data lanes. The third analysis investigates the impact of supply noise due to simultaneous switching outputs (SSO). Finally, the fourth analysis investigates the impact of parameter variations typical in high-volume manufacturing processes on the system margin.
Each of these analysis steps uses the same channel model, which represents a reference implementation of a customer system using the developed PHY. We will focus on the analysis of the DQ channel, since this channel is operating at the highest data rate and has the most challenging VT budget to meet. A similar analysis was done for the RQ channel, but will not be presented in this paper.
III.1.Channel Model Overview
Figure 13: Channel schematic of DDR3 SI/PI co-simulation analysis The DDR3 interface was designed in a wirebond package and a 4-layer PCB system for a data rate of 1600Mpbs. Signal and PDN models are shown in Figure 13 which includes driver, package, PCB, PDN models for both controller and DDR3 device. A detailed SI/PI co-simulation methodology was discussed in [4, 5]. First, transistor level driver models were used in the simulation for 5 DQ pins and strobe signals. The remaining signal drivers were modeled using current-controlled current sources, which limit the simulation complexity of the channel model but still maintain correct current waveforms on signal traces and the supply system.
For wirebond package, both signal and power traces were modeled using a 3D EM solver tools to accurately model the coupling between signal and power rails. In order to reduce simulation complexity, the model was simplified using matrix reduction [6], combining the multiple supply traces for each supply rail. W-element model are commonly used for signal traces of the package substrate and PCB. 7 DQ lines, including 5 signal lines and 2 strobes, were modeled for the Xtalk and SSO analysis. Finally, lumped via and BGA balls models were used to stitch the channel together.
III.2.Channel ISI Results
In the targeted application, the DQ channel routes a point-to-point from the controller to a single DRAM device. Figure 14(a) and 14(b) show the passive channel AC response, and the single bit response.
Since the channel is well terminated and the connection is point-to-point, channel distortion effects are small in the frequency range of interest. For 1600Mbps data rate, the attenuation S21 is -1.2dB, almost unaffected by the Ci loading of the channel, and reflection S11 is around -10dB. For frequencies beyond 1.4GHz Ci loading starts to limit
the channel performance. The single-bit response shows little ISI at the target data rate and only mild reflection.
Figure 14(a): Channel transfer functions Figure 14(b): Channel signal bit response
III.3. Crosstalk Analysis and Routing Optimization
Crosstalk in the wirebond package and the PCB is a major margin loss for high performance and low-cost DDR3 system. In order to find out the main crosstalk contributors, we isolated the impact of each component for the write access case. Fig 15 shows the Xtalk breakdown for the whole passive channel. In this simulation the DQ victim line, located at the center of the five lines, is kept quiet while a single bit pattern is transmitted on the four aggressor lines surrounding the victim. The noise is observed at the DRAM pad of the victim line. Fig 15 shows the crosstalk simulation results for the package and several PCB routing options.
Special care was taken during the design of the wirebond package to minimize the crosstalk contribution of the bond wires, as described in [8]. The remaining crosstalk in the package (+/- 6% of Vnom) was considered unavoidable given the technology constraints of the package design and the pad limitation of the PHY. The goal was to limit the contribution of additional crosstalk in the PCB routing of the channel.
The signal routing on the 4-layer PCB was done using microstrip lines. All the trace routing examples are shown in Fig 16(a). Starting from an earlier routing strategy (Figure 16(b)) the impact of trace spacing on crosstalk of the channel was analyzed. Figure 15 shows the crosstalk impact for different routing implementations. We can see that both 2W and 3W spacing result in significantly higher crosstalk than that of the package alone. For 100mm microstrip line length, crosstalk are +/-13% and +/-10% for 2W and 3W spacing, respectively. It would have been difficult to close the system VT budget at the target data rate under these conditions. Therefore, we changed the routing strategy for the PHY, shortening the DQ bus and at the same time providing more space between DQ traces to add ground guards (Figure 16(c)). This reduced the crosstalk impact on the victim to +/-8%, only marginally higher than the package crosstalk alone.
The new routing strategy required a change in the floor plan and pad-out of the PHY, giving an example of the feedback between channel analysis and silicon design in order
to optimize the system performance of the final PHY.
Figure 15: Channel xtalk contribution breakdown
(a) (b) (c)
Figure 16: PCB trace routing optimization . (a)Trace spacing study, (b)Initial routing topology , (c)Final
routing topology
III.4.SSO Analysis
The channel model introduced earlier is an accurate model of the power supply network for the silicon, the package, and the PCB. This supply model covers the VDDR and VDDQ supplies used for the output driver and pre-driver circuits of the PHY. Correspondingly, the transistor-level driver models used in the SI/PI co-simulation contain the pre-driver and main driver circuits, generating accurate current profiles on these rails during SSO analysis. The analysis is extended to VDDR to cover the impact of VDDR noise on the pre-driver and the resulting jitter during SSO. This SSO contribution
can be significant at higher data rates [4].
Since supply noise during SSO is strongly dependent on the data pattern transmitted by the output drivers, the impact of different pattern on the system margin was tested to identify the worst-case pattern. The tested patterns were PRBS, pattern targeting the package-chip resonance on VDDR-VSS and VDDQ-VSS, and pattern targeting the highest impedance between DQ signals and VDDQ/VSS supply traces, which is the return path loop for push-pull drivers used in DDR3. Figure 17 shows the eye opening for the different pattern. It shows that the smallest eye opening was achieved using PRBS pattern. This pattern was therefore used for further SSO margin loss analysis.
Figure 17: SSO Margin Loss for Different Data Pattern
III.5.High volume manufacturing sensitivity analysis To ensure high performance under high volume manufacturing variations, statistical and sensitivity analysis has been widely used. Taguchi method has been introduced and discussed before [7]. Table 2 lists all the parameter manufacturing variations which dominate the channel performance. Other channel parameters have small impact on VT budget and are not listed in this paper.
Tx driver impedance ()
On-die-termination ()
CTR pkg trace impedance ()
PCB trace impedance ()
Table 2: Channel parameter manufacturing tolerance
Figure 18 shows the impact of each parameter on the system margin during ISI analysis, as these parameters are varied. It shows that Ci, PCB trace impedance, and driver impedance have the largest impact on system margin.
电源完整性设计 作者:于博士 一、为什么要重视电源噪声 芯片内部有成千上万个晶体管，这些晶体管组成内部的门电路、组合逻辑、寄存器、计数器、延迟线、状态机、以及其他逻辑功能。随着芯片的集成度越来越高，内部晶体管数量越来越大。芯片的外部引脚数量有限，为每一个晶体管提供单独的供电引脚是不现实的。芯片的外部电源引脚提供给内部晶体管一个公共的供电节点，因此内部晶体管状态的转换必然引起电源噪声在芯片内部的传递。 对内部各个晶体管的操作通常由内核时钟或片内外设时钟同步，但是由于内部延时的差别，各个晶体管的状态转换不可能是严格同步的，当某些晶体管已经完成了状态转换，另一些晶体管可能仍处于转换过程中。芯片内部处于高电平的门电路会把电源噪声传递到其他门电路的输入部分。如果接受电源噪声的门电路此时处于电平转换的不定态区域，那么电源噪声可能会被放大，并在门电路的输出端产生矩形脉冲干扰，进而引起电路的逻辑错误。芯片外部电源引脚处的噪声通过内部门电路的传播，还可能会触发内部寄存器产生状态转换。 除了对芯片本身工作状态产生影响外，电源噪声还会对其他部分产生影响。比如电源噪声会影响晶振、PLL、DLL的抖动特性，AD转换电路的转换精度等。解释这些问题需要非常长的篇幅，本文不做进一步介绍，我会在后续文章中详细讲解。 由于最终产品工作温度的变化以及生产过程中产生的不一致性，如果是由于电源系统产生的问题，电路将非常难调试，因此最好在电路设计之初就遵循某种成熟的设计规则，使电源系统更加稳健。 二、电源系统噪声余量分析 绝大多数芯片都会给出一个正常工作的电压范围，这个值通常是±5%。例如：对于3.3V 电压，为满足芯片正常工作，供电电压在3.13V到3.47V之间，或3.3V±165mV。对于1.2V 电压，为满足芯片正常工作，供电电压在1.14V到1.26V之间，或1.2V±60mV。这些限制可以在芯片datasheet中的recommended operating conditions部分查到。这些限制要考虑两个部分，第一是稳压芯片的直流输出误差，第二是电源噪声的峰值幅度。老式的稳压芯片
于博士信号完整性研究网 https://www.doczj.com/doc/3d945998.html, 电源完整性设计详解 作者：于争 博士 2009年4月10日
目 录 1 为什么要重视电源噪声问题？....................................................................- 1 - 2 电源系统噪声余量分析................................................................................- 1 - 3 电源噪声是如何产生的？............................................................................- 2 - 4 电容退耦的两种解释....................................................................................- 3 - 4.1 从储能的角度来说明电容退耦原理。..............................................- 3 - 4.2 从阻抗的角度来理解退耦原理。......................................................- 4 - 5 实际电容的特性............................................................................................- 5 - 6 电容的安装谐振频率....................................................................................- 8 - 7 局部去耦设计方法......................................................................................- 10 - 8 电源系统的角度进行去耦设计..................................................................- 12 - 8.1 著名的Target Impedance（目标阻抗）..........................................- 12 - 8.2 需要多大的电容量............................................................................- 13 - 8.3 相同容值电容的并联........................................................................- 15 - 8.4 不同容值电容的并联与反谐振（Anti-Resonance）......................- 16 - 8.5 ESR对反谐振（Anti-Resonance）的影响......................................- 17 - 8.6 怎样合理选择电容组合....................................................................- 18 - 8.7 电容的去耦半径................................................................................- 20 - 8.8 电容的安装方法................................................................................- 21 - 9 结束语..........................................................................................................- 24 -
现在的高速电路设计已经达到GHz的水平，高速PCB设计要求从三维设计理论出发对过孔、封装和布线进行综合设计来解决信号完整性问题。高速PCB设计要求中国工程师必须具备电磁场的理论基础，必须懂得利用麦克斯韦尔方程来分析PCB设计过程中遇到的电磁场问题。目前，Ansoft公司的仿真工具能够从三维场求解的角度出发，对PCB设计的信号完整性问题进行动态仿真。 (一)Ansoft公司的仿真工具 现在的高速电路设计已经达到GHz的水平，高速PCB设计要求从三维设计理论出发对过孔、封装和布线进行综合设计来解决信号完整性问题。高速PCB设计要求中国工程师必须具备电磁场的理论基础，必须懂得利用麦克斯韦尔方程来分析PCB设计过程中遇到的电磁场问题。目前，Ansoft公司的仿真工具能够从三维场求解的角度出发，对PCB设计的信号完整性问题进行动态仿真。 Ansoft的信号完整性工具采用一个仿真可解决全部设计问题： SIwave是一种创新的工具，它尤其适于解决现在高速PCB和复杂IC封装中普遍存在的电源输送和信号完整性问题。 该工具采用基于混合、全波及有限元技术的新颖方法，它允许工程师们特性化同步开关噪声、电源散射和地散射、谐振、反射以及引线条和电源/地平面之间的耦合。该工具采用一个仿真方案解决整个设计问题，缩短了设计时间。 它可分析复杂的线路设计，该设计由多重、任意形状的电源和接地层，以及任何数量的过孔和信号引线条构成。仿真结果采用先进的3D图形方式显示，它还可产生等效电路模型，使商业用户能够长期采用全波技术，而不必一定使用专有仿真器。 (二)SPECCTRAQuest Cadence的工具采用Sun的电源层分析模块： Cadence Design Systems的SpecctraQuest PCB信号完整性套件中的电源完整性模块据称能让工程师在高速PCB设计中更好地控制电源层分析和共模EMI。 该产品是由一份与Sun Microsystems公司签署的开发协议而来的，Sun最初研制该项技术是为了解决母板上的电源问题。 有了这种新模块，用户就可根据系统要求来算出电源层的目标阻抗；然后基于板上的器件考虑去耦合要求，Shah表示，向导程序能帮助用户确定其设计所要求的去耦合电容的数目和类型；选择一组去耦合电容并放置在板上之后，用户就可运行一个仿真程序，通过分析结果来发现问题所在。 SPECCTRAQuest是CADENCE公司提供的高速系统板级设计工具，通过它可以控制与PCB layout相应的限制条件。在SPECCTRAQuest菜单下集成了一下工具： （1）SigXplorer可以进行走线拓扑结构的编辑。可在工具中定义和控制延时、特性阻抗、驱动和负载的类型和数量、拓扑结构以及终端负载的类型等等。可在PCB详细设计前使用此工具，对互连线的不同情况进行仿真，把仿真结果存为拓扑结构模板，在后期详细设计中应用这些模板进行设计。 （2）DF/Signoise工具是信号仿真分析工具，可提供复杂的信号延时和信号畸变分析、IBIS 模型库的设置开发功能。SigNoise是SPECCTRAQUEST SI Expert和SQ Signal Explorer Expert进行分析仿真的仿真引擎，利用SigNoise可以进行反射、串扰、SSN、EMI、源同步及系统级的仿真。 （3）DF/EMC工具——EMC分析控制工具。 （4）DF/Thermax——热分析控制工具。 SPECCTRAQuest中的理想高速PCB设计流程： 由上所示，通过模型的验证、预布局布线的space分析、通过floorplan制定拓朴规则、由规
信号完整性需要重视的几大关键问题 信号完整性是许多设计人员在高速数字电路设计中涉及的主要主题之一。信号完整性涉及数字信号波形的质量下降和时序误差，因为信号从发射器传输到接收器会通过封装结构、PCB走线、通孔、柔性电缆和连接器等互连路径。 当今的高速总线设计如LpDDR4x、USB 3.2 Gen1 / 2(5Gbps / 10Gbps)、USB3.2x2(2x10Gbps)、PCIe和即将到来的USB4.0(2x20Gbps)在高频数据从发送器流向接收器时会发生信号衰减。本文将概述高速数据速率系统的信号完整性基础知识和集肤效应、阻抗匹配、特性阻抗、反射等关键问题。 随着硅节点采用10nm、7nm甚至5nm工艺，这可以在给定的芯片尺寸下实现高集成度并增加功能。在移动应用中，趋势是更高的频率和更高的数据速率，并降低工作核心电压如0.9v、0.8V、0.56V甚至更低以优化功耗。 在较低的工作电压下以较高的频率工作会使阈值电平或给定位数据的数据有效窗口变小，从而影响走线和电源层分配功率以及“眼图”的闭合度。 由较高频率和较低工作电压引起的闭眼，增加了数据传输误差的机会，因而增加了误码率，这就需要重新传输数据流。重传会导致处理器在较长时间处于有源模式以重传数据流，这会导致移动应用更高的功耗并减少使用日(DOU)。
图1. 频率和较低电压对眼图张开的影响 在给定的高频设计中增加其它设计挑战如信号衰减、反射、阻抗匹配、抖动等时，很明显，信号损耗使接收器难以正确译出信息，从而增加了误差的机会。 数据流中的时钟采样 在接收器处，数据是在参考时钟的边缘处采样的。眼图张开越大，就越容易将采样CLK设置在给定位的中间以采样数据。任何幅值衰减、反射或任何抖动，都将使眼图更闭合并使数据有效窗口和有效位时间变得更窄，从而导致接收端出现误差。 图2. CLK采样 现在，让我们检查何时需要将通道或互连视为传输线，并查看在智能手机或平板电脑等系统中传输损耗的一些主要原因。
电源完整性理论基础 ------- 阿鸣随着PCB设计复杂度的逐步提高，对于信号完整性的分析除了反射，串扰以及EMI之外，稳定可靠的电源供应也成为设计者们重点研究的方向之一。尤其当开关器件数目不断增加，核心电压不断减小的时候，电源的波动往往会给系统带来致命的影响，于是人们提出了新的名词：电源完整性，简称PI(power integrity)。其实，PI和SI是紧密联系在一起的，只是以往的EDA仿真工具在进行信号完整性分析时，一般都是简单地假设电源绝对处于稳定状态，但随着系统设计对仿真精度的要求不断提高，这种假设显然是越来越不能被接受的，于是PI的研究分析也应运而生。从广义上说，PI是属于SI研究范畴之内的，而新一代的信号完整性仿真必须建立在可靠的电源完整性基础之上。虽然电源完整性主要是讨论电源供给的稳定性问题，但由于地在实际系统中总是和电源密不可分，通常把如何减少地平面的噪声也作为电源完整性中的一部分进行讨论。 一． 电源噪声的起因及危害 造成电源不稳定的根源主要在于两个方面：一是器件高速开关状态下，瞬态的交变电流过大；二是电流回路上存在的电感。从表现形式上来看又可以分为三类：同步开关噪声（SSN），有时被称为Δi噪声，地弹（Ground bounce）现象也可归于此类（图1-a）；非理想电源阻抗影响（图1-b）；谐振及边缘效应（图1-c）。
对于一个理想的电源来说，其阻抗为零，在平面任何一点的电位都是保持恒定的（等于系统供给电压），然而实际的情况并不如此，而是存在很大的噪声干扰，甚至有可能影响系统的正常工作，见图2： 开关噪声给信号传输带来的影响更为显著，由于地引线和平面存在寄生电感，在开关电流的作用下，会造成一定的电压波动，也就是说器件的参考地已经不再保持零电平，这样，在驱动端（见图3-a），本来要发送的低电平会出现相应的噪声波形，相位和地面噪声相同，而对于开关信号波形来说，会因为地噪声的影响导致信号的下降沿变缓；在接收端（见图3-b），信号的波形同样会受到地噪声的干扰，不过这时的干扰波形和地噪声相位相反；另外，在一些存储性器件里，还有可能因为本身电源和地噪声的影响造成数据意外翻转（图3-c）。 从前面的图3-c我们可以看到，电源平面其实可以看成是由很多电感和电容构成的网络，也可以看成是一个共振腔，在一定频率下，这些电容和电感会发生谐振现象，从而影响电源层的阻抗。比如一个8英寸×9英寸的PCB空板，板材是普通的FR4，电源和地之间的间距为4.5Mils，随着频率的增加，电源阻抗是不断变化的，尤其是在并联谐振效应显著的时候，电源阻抗也随之明显增加（见图4）。
期待解决的问题： 1.为何AC耦合电容放在TX端； 2.为何有的电源或地平面要挖掉一块； 3.搞清楚反射； 4.搞清楚串扰； 5.搞清楚地弹； 6.搞清楚眼图； 7.搞清楚开关噪声； 8.各种地过孔的作用； 9.写一份学习总结。 自己总结： 从微观的角度讲，信号完整性研究的是电子在电场和磁场的作用下是如何运动的，以及这种运动会造成哪些电气特性产生什么变化。 从宏观的角度讲，信号完整性研究的是如何保证信号从源端传送到终端的过程中，失真的程度在要求的范围内。
第1章 四类基本信号完整性问题： 1、单一网络的信号质量：在信号路径和返回路径上由阻抗突变而引起的反射和失真。 2、两个或多个网络间的串扰：理想回路和非理想回路耦合的互电容和互电感。 3、电源分配系统中的轨道塌陷：电源和地网络中的阻抗压降。 4、来自元件或系统的电磁干扰。 阻抗： 1、任何阻抗突变，都会引起电压信号的反射和失真。 2、信号的串扰，是由相邻线条及其返回路径之间的电场和磁场的耦合引起的，信号线间的 互耦合电容和互耦合电感的阻抗决定了耦合电流的值。 3、电源供电轨道的塌陷，与电源分布系统（PDS）的阻抗有关。 4、最大的EMI根源是流经外部电缆的共模电流，此电流由地平面上的电压引起。在电缆周 围使用铁氧体扼流圈，增加共模电流所受到的阻抗，从而减小共模电流。
第2章时域与频域 频谱：在频域中，对波形的描述变为不同正弦波频率值的集合。每个频率值都有相关的幅度和相位。把所有这些频率值及其幅度值的集合称为波形的频谱。（在频域中，描述波形的方法） 频域中的频谱表示的是时域波形包含的所有正弦波频率的幅度。 计算时域波形频谱的唯一方法是傅立叶变换。 即使每个波形的时钟频率相同，然而他们的上升时间可能不同，因此带宽也不同。 每个严肃认真的工程师都应该至少用手工计算一次傅立叶积分来观察它的细节。 带宽：表示频谱中有效的最高正弦波频率分量。 把频谱中更高频率的分量都去掉，也能充分近似时域波形的特征。 信号的带宽就是幅度比理想方波幅度小3dB（50%）的那个最高频率。 上升时间与时钟周期什么关系？ 原则上讲，两者之间的唯一约束是：上升时间一定小于周期的50%。
电源完整性设计电容的安装方法 电容的安装方法 电容的摆放 对于电容的安装，首先要提到的就是安装距离。容值最小的电容，有最高的谐振频率，去耦半径最小，因此放在最靠近芯片的位置。容值稍大些的可以距离稍远，最外层放置容值最大的。但是，所有对该芯片去耦的电容都尽量靠近芯片。下面的图14就是一个摆放位置的例子。本例中的电容等级大致遵循10倍等级关系。 图14 电容摆放位置示例 还有一点要注意，在放置时，最好均匀分布在芯片的四周，对每一个容值等级都要这样。通常芯片在设计的时候就考虑到了电源和地引脚的排列位置，一般都是均匀分布在芯片的四个边上的。因此，电压扰动在芯片的四周都存在，去耦也必须对整个芯片所在区域均匀去耦。如果把上图中的680pF电容都放在芯片的上部，由于存在去耦半径问题，那么就不能对芯片下部的电压扰动很好的去耦。 电容的安装 在安装电容时，要从焊盘拉出一小段引出线，然后通过过孔和电源平面连接，接地端也
是同样。这样流经电容的电流回路为：电源平面->过孔->引出线->焊盘->电容->焊盘->引出线->过孔->地平面，图15直观的显示了电流的回流路径。 图15 流经电容的电流回路 放置过孔的基本原则就是让这一环路面积最小，进而使总的寄生电感最小。图16显示了几种过孔放置方法。 图16 高频电容过孔放置方法 第一种方法从焊盘引出很长的引出线然后连接过孔，这会引入很大的寄生电感，一定要避免这样做，这时最糟糕的安装方式。 第二种方法在焊盘的两个端点紧邻焊盘打孔，比第一种方法路面积小得多，寄生电感也较小，可以接受。 第三种在焊盘侧面打孔，进一步减小了回路面积，寄生电感比第二种更小，是比较好的
高速电路中的信号完整性问题 许致火 （07级信号与信息处理 学号 307081002025) 1 信号完整性问题的提出 一般来讲，传统的低频电路设计对于电子工程师并不是多么复杂的工作。因为在低于30MHz的系统中并不要考虑传输线效应等问题，信号特性保持完好使得系统照常能正常工作。但是随着人们对高速实时信号处理的要求，高频信号对系统的设计带来很大的挑战。电子工程师不仅要考虑数字性能还得分析高速电路中各种效应对信号原来 面目影响的问题。 输入输出的信号受到传输线效应严重的影响是我们严峻的挑战 之一。在低频电路中频率响应对信号影响很小，除非是传输的媒介的长度非常长。然而伴随着频率的增加，高频效应就显而易见了。对于一根很短的导线也会受到诸如振玲、串扰、信号反射以及地弹的影响，这些问题严重地损害了信号的质量，也就是导致了信号完整性性能下降。 2 引起信号完整性的原因 2.1 传输线效应 众所周知，传输线是用于连接发送端与接收段的连接媒介。传统的比如电信的有线线缆能在相当长的距离范围内有效地传输信号。但是高速的数字传输系统中，即使对于PCB电路板上的走线也受到传输线效应的影响。如图1所示，对于不同高频频率的PCB板上的电压分布是不同的。 图 1 PCB在不同频率上的电压波动
因为低频电路可以看成是一个没有特性阻抗、电容与电感寄生效应的理想电路。高速电路中高低电平的快速切换使得电路上的走线要看成是阻抗、电容与电感的组合电路。其等效电路模型如图2所示。导线的阻抗是非常重要的概念，一旦传输路径上阻抗不匹配就会导致信号的质量下降。 图 2 传输线等效电路模型 由图2的模型可得电报方程： 2.2 阻抗不匹配情况 信号源输出阻抗（Zs）、传输线上的阻抗（Zo）以及负载的阻抗（ZL）不相等时，我们称该电流阻抗不匹配。也这是说信号源的能量没有被负载全部吸收，还有一部分能量被反射回信号源方向了。反射后又被信号源那端反射给负载，除了吸收一部分外，剩下的又被反射回去。这个过程一直持续，直到能量全部被负载吸收。这样就会出现过冲与下冲(Overshoot/Undershoot)、振铃(ring)、阶梯波形(Stair-step Waveform)现象，这些现象的产生导致信号出现错误。 当传输媒介的特性阻抗与负载终端匹配时，阻抗就匹配了。对于PCB板来说，我们可以选取合适的负载终端策略及谨慎地选择传输介
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什么是信号完整性? 如果你发现，以前低速时代积累的设计经验现在似乎都不灵了，同样的设计，以前没问题，可是现在却无法工作，那么恭喜你，你碰到了硬件设计中最核心的问题：信号完整性。早一天遇到，对你来说是好事。 在过去的低速时代，电平跳变时信号上升时间较长，通常几个ns。器件间的互连线不至于影响电路的功能，没必要关心信号完整性问题。但在今天的高速时代，随着IC输出开关速度的提高，很多都在皮秒级，不管信号周期如何，几乎所有设计都遇到了信号完整性问题。另外，对低功耗追求使得内核电压越来越低，1.2v内核电压已经很常见了。因此系统能容忍的噪声余量越来越小，这也使得信号完整性问题更加突出。 广义上讲，信号完整性是指在电路设计中互连线引起的所有问题，它主要研究互连线的电气特性参数与数字信号的电压电流波形相互作用后，如何影响到产品性能的问题。主要表现在对时序的影响、信号振铃、信号反射、近端串扰、远端串扰、开关噪声、非单调性、地弹、电源反弹、衰减、容性负载、电磁辐射、电磁干扰等。 信号完整性问题的根源在于信号上升时间的减小。即使布线拓扑结构没有变化，如果采用了信号上升时间很小的IC芯片，现有设计也将处于临界状态或者停止工作。 下面谈谈几种常见的信号完整性问题。 反射： 图1显示了信号反射引起的波形畸变。看起来就像振铃，拿出你制作的电路板，测一测各种信号，比如时钟输出或是高速数据线输出，看看是不是存在这种波形。如果有，那么你该对信号完整性问题有个感性的认识了，对，这就是一种信号完整性问题。 很多硬件工程师都会在时钟输出信号上串接一个小电阻，至于为什么，他们中很多人都说不清楚，他们会说，很多成熟设计上都有，照着做的。或许你知道，可是确实很多人说不清这个小小电阻的作用，包括很多有了三四年经验的硬件工程师，很惊讶么?可这确实是事实，我碰到过很多。其实这个小电阻的作用就是为了解决信号反射问题。而且随着电阻的加大，振铃会消失，但你会发现信号上升沿不再那么陡峭了。这个解决方法叫阻抗匹配，奥，对了，一定要注意阻抗匹配，阻抗在信号完整性问题中占据着极其重要的
如何实现电源PCB板完整性的设计 在电路设计中，一般我们很关心信号的质量问题，但有时我们往往局限在信号线上进行研究，而把电源和地当成理想的情况来处理，虽然这样做能使问题简化，但在高速设计中，这种简化已经是行不通的了。尽管电路设计比较直接的结果是从信号完整性上表现出来的，但我们绝不能因此忽略了电源完整性设计。因为电源完整性直接影响最终PCB板的信号完整性。电源完整性和信号完整性二者是密切关联的，而且很多情况下，影响信号畸变的主要原因是电源系统。例如，地反弹噪声太大、去耦电容的设计不合适、回路影响很严重、多电源/地平面的分割不好、地层设计不合理、电流不均匀等等。 （1）电源分配系统 电源完整性设计是一件十分复杂的事情，但是如何近年控制电源系统（电源和地平面）之间阻抗是设计的关键。理论上讲，电源系统间的阻抗越低越好，阻抗越低，噪声幅度越小，电压损耗越小。实际设计中我们可以通过规定最大的电压和电源变化范围来确定我们希望达到的目标阻抗，然后，通过调整电路中的相关因素使电源系统各部分的阻抗（与频率有关）目标阻抗去逼近。 （2）地反弹 当高速器件的边缘速率低于0.5ns时，来自大容量数据总线的数据交换速率特别快，当它在电源层中产生足以影响信号的强波纹时，就会产生电源不稳定问题。当通过地回路的电流变化时，由于回路电感会产生一个电压，当上升沿缩短时，电流变化率增大，地反弹电压增加。此时，地平面（地线）已经不是理想的零电平，而电源也不是理想的直流电位。当同时开关的门电路增加时，地反弹变得更加严重。对于128位的总线，可能有50_100个I/O线在相同的时钟沿切换。这时，反馈到同时切换的I/O驱动器的电源和地回路的电感必须尽可能的低，否则，连到相同的地上的静止将出现一个电压毛刷。地反弹随处可见，如芯片、封装、连接器或电路板上都有可能会出现地反弹，从而导致电源完整性问题。 从技术的发展角度来看，器件的上升沿将只会减少，总线的宽度将只会增加。保持地反弹在可接受的唯一方法是减少电源和地分布电感。对于，芯片，意味着，移到一个阵列晶片，
基于Cadence Allegro SI 16.3的信号完整性仿真 信号完整性是指信号在信号线上的质量。信号具有良好的信号完整性是指当在需要的时候，具有所必需达到的电压电平数值。差的信号完整性不是由某一因素导致的，而是由板级设计中多种因素共同引起的。特别是在高速电路中，所使用的芯片的切换速度过快、端接元件布设不合理、电路的互联不合理等都会引起信号的完整性问题。具体主要包括串扰、反射、过冲与下冲、振荡、信号延迟等。 信号完整性问题由多种因素引起，归结起来有反射、串扰、过冲和下冲、振铃、信号延迟等，其中反射和串扰是引发信号完整性问题的两大主要因素。 反射和我们所熟悉的光经过不连续的介质时都会有部分能量反射回来一样，就是信号在传输线上的回波现象。此时信号功率没有全部传输到负载处，有一部分被反射回来了。在高速的PCB中导线必须等效为传输线，按照传输线理论，如果源端与负载端具有相同的阻抗，反射就不会发生了。如果二者阻抗不匹配就会引起反射，负载会将一部分电压反射回源端。根据负载阻抗和源阻抗的关系大小不同，反射电压可能为正，也可能为负。如果反射信号很强，叠加在原信号上，很可能改变逻辑状态，导致接收数据错误。如果在时钟信号上可能引起时钟沿不单调，进而引起误触发。一般布线的几何形状、不正确的线端接、经过连接器的传输及电源平面的不连续等因素均会导致此类反射。另外常有一个输出多个接收，这时不同的布线策略产生的反射对每个接收端的影响也不相同，所以布线策略也是影响反射的一个不可忽视的因素。 串扰是相邻两条信号线之间的不必要的耦合，信号线之间的互感和互容引起线上的噪声。因此也就把它分为感性串扰和容性串扰，分别引发耦合电流和耦合电压。当信号的边沿速率低于1ns时，串扰问题就应该考虑了。如果信号线上有交变的信号电流通过时，会产生交变的磁场，处于磁场中的相邻的信号线会感应出信号电压。一般PCB板层的参数、信号线间距、驱动端和接收端的电气特性及信号线的端接方式对串扰都有一定的影响。在Cadence 的信号仿真工具中可以同时对6条耦合信号线进行串扰后仿真，可以设置的扫描参数有：PCB 的介电常数，介质的厚度，沉铜厚度，信号线长度和宽度，信号线的间距．仿真时还必须指定一个受侵害的信号线，也就是考察另外的信号线对本条线路的干扰情况，激励设置为常高或是常低，这样就可以测到其他信号线对本条信号线的感应电压的总和，从而可以得到满足要求的最小间距和最大并行长度。 过冲是由于电路切换速度过快以及上面提到的反射所引起的信号跳变，也就是信号第一个峰值超过了峰值或谷值的设定电压。下冲是指下一个谷值或峰值。过分的过冲能够引起保护二极管工作，导致过早地失效，严重的还会损坏器件。过分的下冲能够引起假的时钟或数据错误。它们可以通过增加适当端接予以减少或消除。 在Cadence的信号仿真软件中，将以上的信号完整性问题都放在反射参数中去度量。在接收和驱动器件的IBIS模型库中，我们只需要设置不同的传输线阻抗参数、电阻值、信号传输速率以及选择微带线还是带状线，就可以通过仿真工具直接计算出信号的波形以及相应的数据，这样就可以找出匹配的传输线阻抗值、电阻值、信号传输速率，在对应的PCB软件Allegro中，就可以根据相对应的传输线阻抗值和信号传输速率得到各层中相对应信号线的宽度(需提前设好叠层的顺序和各参数)。选择电阻匹配的方式也有多种，包括源端端接和并行端接等，根据不同的电路选择不同的方式。在布线策略上也可以选择不同的方式：菊花型、星型、自定义型，每种方式都有其优缺点，可以根据不同的电路仿真结果来确定具体的选择方式。
二信号的完整性问题及解决办法 两个方面（时序和电平） 信号完整性(Signal Integrity)是指信号未受到损伤的一种状态，它表示信号质量和信号传输后仍保持正确的功能特性。良好的信号完整性是指在需要时信号仍能以正确的时序和电压电平值作出响应。随着高速器件的使用和高速数字系统设计越来越多，系统数据速率、时钟速率和电路密集度都在不断增加。在这种设计中，系统快斜率瞬变和工作频率很高，电缆、互连、印制板(PCB)和硅片将表现出与低速设计截然不同的行为，即出现信号完整性问题。 信号完整性问题能导致或者直接带来信号失真，定时错误，不正确数据、地址和控制线以及系统误工作甚至系统崩溃，解决不好会严重影响产品性能并带来不可估量的损失，已成为高速产品设计中非常值得注意的问题。 信号完整性问题的真正起因是不断缩减的信号上升与下降时间。一般来说，当信号跳变比较慢即信号的上升和下降时间比较长时，PCB中的布线可以建模成具有一定数量延时的理想导线而确保有相当高的精度。此时，对于功能分析来说，所有连线延时都可以集总在驱动器的输出端，于是，通过不同连线连接到该驱动器输出端的所有接收器的输入端在同一时刻观察都可得到相同波形。然而，随着信号变化的加快，信号上升时间和下降时间缩短，电路板上的每一个布线段由理想的导线转变为复杂的传输线。此时信号连线的延时不能再以集总参数模型的方式建模在驱动器的输出端，同一个驱动器信号驱动一个复杂的PCB连线时，电学上连接在一起的每一个接收器上接收到的信号就不再相同。从实践经验中得知，一旦传输线的长度大于驱动器上升时间或者下降时间对应的有效长度的1/6，传输线效应就会出来，即出现信号完整性问题，包括反射、上冲和下冲、振荡和环绕振荡、地电平面反弹和回流噪声、串扰和延迟等。表1列出了高速电路设计中常见的信号完整性问题，以及可能引起该信号完整性的原因，并给出了相应的解决方法。目前，解决信号完整性问题的方法主要有电路设计、合理布局和建模仿真。电路设计中，通常采用以下方法来解决信号完整性问题：·控制同步切换输出数量，控制各单元的最大边沿速率(dI/dt和dV/dt)，从而得到最低且可接受的边沿速率；·为高输出功能块(如时钟驱动器)选择差分信号；·在传输线上端接无源元件(如电阻、电容等)，以实现传输线与负载间的阻抗匹配。端接策略的选择应该是对增加元件数目、开关速度和功耗的折中，且端接串联电阻R或RC电路应尽量靠近激励端或接收端。布线非常重要，设计者应该在不违背一般原则的前提下，利用现有的设计经验，综合多种可能的方案，优化布线，消除各种潜在的问题。一方面要充分利用现有的、已经过验证的布线经验，将它们应用于布线工作中；另一方面要积极利用一些信号完整性方面的仿真工具，约束、指导布线。合理进行电路建模仿真是最常见的信号完整性解决方法。在高速电路设计中，仿真分析越来越显示出优越性。它给设计者以准确、直观的设计结果，便于及早发现问题，及时修改，从而缩短设计时间，降低设计成本。在进行电路建模仿真过程中，设计者应对
什么是高速数字信号？ 高速数字信号由信号的边沿速度决定，一般认为上升时间小于4倍信号传输延迟时可视为高速信号，而高频信号是针对信号频率而言的。高速电路涉及信号分析、传输线、模拟电路的知识。错误的概念是：8KHz帧信号为低速信号。多高的频率才算高速信号？ 当信号的上升/下降沿时间< 3~6倍信号传输时间时,即认为是高速信号. 对于数字电路，关键是看信号的边沿陡峭程度，即信号的上升、下降时间,信号从10%上升到90%的时间小 于6倍导线延时,就是高速信号! 即使8KHz的方波信号,只要边沿足够陡峭,一样是高速信号,在布线时需要使用传输线理论。 信号完整性研究：什么是信号完整性? 时间:2009-03-11 20:18来源:sig007 作者:于博士点击:1813次 信号完整性主要是指信号在信号线上传输的质量，当电路中信号能以要求的时序、持续时间和电压幅度到达接收芯片管脚时，该电路就有很好的信号完整性。当信号不能正常响应或者信号质量不能使系统长期稳定工作时，就出现了信号完整性问题，信号完整性主要表现在延迟、反射、串扰、时序、振荡等几个方面。一般认为，当系统工作在50MHz时，就会产生信号完整性问题，而随着系统和器件频率的不断攀升，信号完整性的问题也就愈发突出。元器件和PCB板的参数、元器件在PCB板上的布局、高速信号的布线等 这些问题都会引起信号完整性问题，导致系统工作不稳定，甚至完全不能正常工作。 1、什么是信号完整性（Singnal Integrity）？ 信号完整性（Singnal Integrity）是指一个信号在电路中产生正确的相应的能力。信号具有良好的信号完整性（Singnal Integrity）是指当在需要的时候，具有所必须达到的电压电平数值。主要的信号完整性问题包括反射、振荡、地弹、串扰等。常见信号完整性问题及解决方法： 问题可能原因解决方法其他解决方法 过大的上冲终端阻抗不匹配终端端接使用上升时间缓慢的驱动源 直流电压电平不好线上负载过大以交流负载替换直流负载在接收端端接，重新布线或检查地平面
信号完整性之初识信号反射 版本号更改描述更改人日期 1.0 第一次撰稿 eco 2013-10-19 E-mial：zhongweidianzikeji@https://www.doczj.com/doc/3d945998.html, QQ：2970904654 反射产生的原因 在《和信号完整性有关的几个概念》中我们已经简单的介绍了“反射”这厮。在下认为 “信号反射”在电路中是不可避免的，不论是高速电路还是低速电路。而我们只能用一些办 法去优化电路，去优化PCB的布局布线，从而降低反射的大小或者在信号反射时避免对电 路的操作。 为什么信号反射无法完全消除，在高速和低速电路中都会存在，在下鄙见如下： V = 3x10^8 / sqrξ 式1 其中：V是带状线中信号传播的速度（m/s），3x10^8是光速(m/s)，ξ是介电常数。 由式1可知，信号的传播速度只与物质的介电常数有关，在基材相同的情况下，不论在 高速电路中还是在低速电路中信号都会以相同的速度传播。在基材为FR4的电路板中，介 电常数ξ一般为4左右，由式1我们可以计算出信号的传播速度V = 3x10^8 / sqr(4) = 1.5x10^8 m/s,转换单位后约为6in/ns，这就是为什么很多资料上喊信号在FR4材料中的传 播速度为6in/ns（注：1mil = 0.0254mm； 1inch = 25.4mm。对于这个单位转化，感兴趣 的人一定要自己计算计算，享受过程可以让你更快乐更智慧哦）。1.5x10^8 m/s（6in/ns） 速度极快了吧，设想山间小溪，小溪中的水流以1.5x10^8 m/s流动，流动中突遇一石头便 会荡起无数涟漪，迸射无数水花。溪中这块石头意味着阻抗失配。综上所述，我们姑且把这 水流现象近似看作电路中的信号反射。 为了给大家一个直观的感受，在下从网上找了两张图片，见图1、图2。很多时候有些 东西是说不清道不明的，关键看大家如何去想，如何去悟。我建议大家应该看着这个水流冥 想一下。 图1 这就是电流
DesignCon 2011 Signal and Power Integrity for a 1600 Mbps DDR3 PHY in Wirebond Package June Feng, Rambus Inc. [Email: jfeng@https://www.doczj.com/doc/3d945998.html,] Ralf Schmitt, Rambus Inc. Hai Lan, Rambus Inc. Yi Lu, Rambus Inc.
Abstract A DDR3 interface for a data rate of 1600MHz using a wirebond package and a low-cost system environment typical for consumer electronics products was implemented. In this environment crosstalk and supply noise are serious challenges and have to be carefully optimized to meet the data rate target. We are presenting the signal and power integrity analysis used to optimize the interface design and guarantee reliable system operation at the performance target under high-volume manufacturing conditions. The resulting DDR3 PHY was implemented in a test chip and achieves reliable memory operations at 1600MHz and beyond. Authors Biography June Feng received her MS from University of California at Davis, and BS from Beijing University in China. From 1998 to 2000, she was with Amkor Technology, Chandler, AZ. She was responsible for BGA package substrate modeling and design and PCB characterization. In 2000, she joined Rambus Inc and is currently a senior member of technical staff. She is in charge of performing detailed analysis, modeling, design and characterization in a variety of areas including high-speed, low cost PCB layout and device packaging. Her interests include high-speed interconnects modeling, channel VT budget simulation, power delivery network modeling and high-frequency measurements. Ralf Schmitt received his Ph.D. in Electrical Engineering from the Technical University of Berlin, Germany. Since 2002, he is with Rambus Inc, Los Altos, California, where he is a Senior Manager leading the SI/PI group, responsible for designing, modeling, and implementing Rambus multi-gigahertz signaling technologies. His professional interests include signal integrity, power integrity, clock distribution, and high-speed signaling technologies. Hai Lan is a Senior Member of Technical Staff at Rambus Inc., where he has been working on on-chip power integrity and jitter analysis for multi-gigabit interfaces. He received his Ph.D. in Electrical Engineering from Stanford University, M.S. in Electrical and Computer Engineering from Oregon State University, and B.S. in Electronic Engineering from Tsinghua University in 2006, 2001, and 1999, respectively. His professional interests include design, modeling, and simulation for mixed-signal integrated circuits, substrate noise coupling, power and signal integrity, and high-speed interconnects. Yi Lu is a senior systems engineer at Rambus Inc. He received the B.S. degree in electrical engineer and computer science from U.C. Berkeley in 2002 with honors. In 2004, he received the M.S. degree in electrical engineering from UCLA, where he designed and fabricated a 3D MEMS microdisk optical switch. Since joining Rambus in 2006, he has been a systems engineer designing various memory interfaces including XDR1/2 and DDR2/3.