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High-speed low-kickback-noise accurate comparators based on preamplifier-latch topology

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High-Speed Low-Kickback-Noise Accurate Comparators Based on Preamplifier-Latch Topology

Obalit Shino*, Ali Baradaran Rezaeii and Tohid Moradi Department of Microelectronics Engineering, Urmia Graduate Institute *m.o.shino@urumi.ac.ir

Abstract— Implementation of many high-speed systems, such as ADCs, is dependent on high performance comparators. In this paper two structures are presented for high-speed, low-noise and accurate applications. Both of the circuits are based on a positive feedback structure of two back-to-back inverters. First circuit is an improved rail-to-rail folded cascode amplifier in which an active bias circuit is utilized for rearranging the structure appropriate to the running comparison phase. Next circuit is a new comparator which is distinguished by its novel data reception style. In this circuit, PMOS transistors of the latch structure are constructed in separate n-wells, known as hot n-well. Inputs are applied to the bulks of the mentioned PMOS transistors via two differential pairs; hence due to isolation of regenerative outputs from bulks, a sensible attenuation in kickback noise value is observed. Despite the noted advantage, employing hot n-wells enlarges the active area of comparator. Another drawback of the proposed comparator is the necessity of utilizing extra capacitors in its structure. Although the capacitors are negligibly small, their construction should be without any tolerance, otherwise, any mismatch in their structure will enhance the total offset of the circuit. An advantage that can be noted for both presented circuits is the possibility of merging the evaluation phase with reset and latch sequences which leads to an intense increase in comparison speed. The comparators have been simulated using CSMC 0.35μm CMOS process model considering process variations, VDD noise of 100mVp-p, alterations in temperature and applying the inputs for testing the comparators in worst case. Simulation results confirm recognition of a differential input with 2mV pick-to-pick amplitude at as high a clock frequency as 800MHz with power consumption about 2.6mW for first circuit and a 1mV differential input with update rate of 1GHz and power consumption about 1.6mW for the low-noise structure of the second comparator. Layout results of the circuits apprize a 55μm × 13μm and a 24μm × 15μm active area for improved folded cascode comparator and the proposed novel structure respectively.

Keywords- High Speed Comparator; Kickback Noise; High Speed ADC; High Resolution Comparator.

I. INTRODUCTION CMOS high-speed analog-to-digital converters (ADCs) are one of the best suited blocks for vast use in the growing field of digital signal processing. Many challenges in the overall design process of these ADCs had to be solved to achieve high performance systems with desirable characteristics. A high-

speed, high-resolution and low-power comparator can be assumed as the bottleneck of the high performance ADC structures, therewith a low power consumption is expected, to keep the overall power consumption of the system in a reasonable level. Voltage comparators are circuits which compare the input voltage with a particular reference value and output a "high" or "low" signal based on the comparison. Unlike the input voltage of a comparator that changes continuously, the output value changes in steps at the input clock edges. Despite the great variety, according to their main architecture, comparators can be categorized in two groups, single-stage and multi-stage structures [2]. The multi-stage comparators are usually based on an input block acting as a pre-amplifier, one or more intermediate stages for increasing the overall gain and attenuation of the kickback effect on analog input signals, [5], and finally an output latch which guaranties the complete separation of the differential output voltages. Multiplicity of internal stages in structure of the comparators increases the total delay time and hence prolongs the comparison cycle which means a great restriction for speed enhancement. Moreover, additional stages result in larger die size and extra power consumption which are wholly in conflict with integration traits. It might seem that the single stage comparators, [1][2][3][4], are more proportional with integration features, but executing the consecutive sequences of comparison process (reset, evaluation and latch), using a single block, obligates the rearrangement of block structure, using some additional controlling signals [1][2]. Variety of timing signals might increase the digital coupled noise in analog section, also generation of these controlling signals requires some extra hardware which again increases the die size and power consumption of the system. CMOS process variation is the main origin of the offset voltage introduced to the latched comparators, which extremely restricts their comparison accuracy. Coupling a pre-amplifier stage before the output latch attenuates the input-referred offset voltage of comparator, thus an accurate preamplifier-latch topology is engendered, [6][7][8], making it possible to utilize the comparator for high-resolution purposes.

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New Logic Family Achieves Highest Speeds at Lower Voltagesby Stephen Nolan and Ji Park, Texas InstrumentsWorkstations, servers, and other high-performance systems are reaching new heights in innovation daily. As these productsimprove, bus- and memory-interface devices must keep paceand must advance to greater speeds as well. Moreover, thesesystems require that this increased speed be coupled with lower power consumption. This imperative usually means a lowervoltage node. Also to function as viable solutions, these logicdevices must reach these faster and faster speeds withoutsacrificing signal integrity.Texas Instruments’ new logic family, the AVC (AdvancedVery-low-voltage CMOS) family, delivers both high speed and low power without reducing signal quality. AVC logic follows on the heels of TI’s ALVC (Advanced Low Voltage CMOS) logic, which helped engineers make the transition from 5-V to 3.3-Vdesigns beginning in 1994. Many designs are now migratingfrom 3.3-V to 2.5-V, creating new design challenges.Complicating this transition is the industry’s appetite for higher system speeds, which has driven bus speeds above the125-MHz mark (Figure 1). The AVC logic family is the firstlogic family in the industry with propagation delays of less than two nanoseconds (2 ns).High-speed logic usually generates significant undershoot andovershoot noise from the very fast signal transitions. Seriesdamping resistors are sometimes used to reduce electrical noise; but resistors, whether they are internal or external to the logic,also slow the speed of the signals through the circuitry. TheAVC family does not require series damping resistors to reduce electrical noise (Figure 2).TI has developed a unique innovation called Dynamic OutputControl (DOC™) (patent pending), which gives AVC logic "the best of both worlds." Specifically, AVC logic achieves very high signaling speeds because the circuitry behaves as though therewere no resistors in the output when a signal transition is taking place. Then, as the signal transition nears completion, circuitry is automatically activated that behaves as though there were series damping resistors on the output. This capability dramaticallyminimizes the signal undershoot or overshoot and effectivelymuffles electrical noise.In addition to high-speed and low electrical noise, AVCconsumes little power and is easy to design into a mixed-voltage system. Although AVC is very low power with its optimization for 2.5-V systems, it remains compatible with 3.3-V or even1.8-V components as well. In fact, AVC is operational from1.65 V to 3.6 V. Moreover, AVC logic can save battery lifesince it has a feature that supports partial power off--thusallowing the power to be turned off to portions of a systemwhen those sections are not in use.The AVC family is over-voltage tolerant at both the inputs and the outputs--a feature which helps the engineer who is facedwith a mixed voltage mode design. For example, if a design calls for interfacing a 2.5-V memory controller with 3.3-V memories, all the designer needs to do is place an AVC transceiver inbetween the memory controller and the memories. The AVCdevice, powered at 2.5 V, will provide reliable bi-directionaldata communication between the devices at these two voltagenodes. The data from the 3.3-V memories are accepted at theinputs of the AVC transceiver without any problems, since the transceiver’s inputs are over-voltage tolerant. Also, an AVCdriver or register device, powered at 1.8 V, can be used toprovide uni-directional data communication from devices at the 3.3-V or the 2.5-V nodes to devices at 1.8 V.Dynamic Output Control (DOC)The way the AVC family’s DOC circuitry handles high-speedsignals is similar to the way a race car driver negotiates an oval track. On the straight-aways, the driver can accelerate tomaximum speed. But, as he approaches a curve in the track, the driver must slow down or risk losing control of the car. In much the same way, DOC circuitry (Figure 3) allows the signaling to accelerate to its maximum speed during the transition from a low to a high state (or from a high to a low). Then, in much the same way that a race car driver eases off the accelerator as henegotiates a curve, the DOC circuitry reduces the power of the electrical signal when the transition nears completion. Thisreduction minimizes overshoot and undershoot noise that would otherwise be generated by a high-speed signal transition.Specifically, DOC lowers the output impedance of the circuitry at the beginning of a signal transition to drive the load at highspeeds. Then, as the end of transition is near, DOCautomatically raises the impedance to roll-off the signal and toreduce noise.(figure 4)The DOC effectively consists oftwo parallel drivers and animpedance control circuit (ZCC)that monitors the output signal.When the impedance controlcircuit senses that more current isneeded, the outputs of both theparallel drivers are enabled,thereby reducing the outputimpedance. As the signal passes through the threshold during a transition, the impedance control circuit disables the output ofone of the drivers, thereby increasing the output impedance.Obviously, the driver that is disabled does not contribute anyadditional drive current or loading to the output.Bus Hold™(figure 5)The bus hold feature was alsoincluded in the AVC family of logicdevices. Bus hold helps solve theproblem of floating inputs andeliminates the need for pull-up orpull-down resistors. With thetotem-pole structure that characterizesthe inputs of CMOS devices, theinput must be held as close to VCC orGND rails as possible. Precautions should be taken to preventthe input voltage from floating near the threshold voltagebecause this eventuality would bias both input transistors on and would create undesirably high ICC currents at the VCC pin of the device. One possible method would be to use pull-up orpull-down resistors, but these are costly and take up additionalcircuit-board area. An alternative solution is to use devices in the AVC family that utilize the optional bus-hold circuit at the inputs. AVC devices with bus-hold circuitry are designated AVCH.The bus-hold circuit consists of two series inverters with theoutput fed back to the input through a resistor. This arrangement provides a weak positive feedback by sinking or sourcingcurrent to the input node. The bus-hold circuit consists of twoseries inverters with the output fed back to the input through aresistor. This arrangement provides a weak positive feedbackby sinking or sourcing current to the input node. The bus-holdcell holds the input at its last known valid logic state until thisstate is forcibly changed by a driving circuit.A Full Family of LogicA comprehensive selection of AVC devices is planned forintroduction over the next two years. The AVC productportfolio will be comprised of gate, octal, Widebus™, andWidebus+™ logic devices. A complete selection of differentdevice types such as bus drivers and transceivers, buffers,flip-flops, latches, and address drivers will eventually find their way into the AVC family. Samples of the first four members of the AVC logic family should be available from TexasInstruments and its authorized distributors in the fourth quarter of 1998. Part numbers and anticipated resale pricing in quantitiesof 1000 are as follows: AVC16244 16-bit buffer $2.92,AVC16245 16-bit transceiver $2.92, AVC16373 16-bitD-type transparent latch $2.92, and AVC16374 16-bit D-typeflip-flop $2.92. Military versions of selected AVC functions are also planned.Top of PageAbout the AuthorsStephen Nolan is the senior applications engineer for TexasInstruments' CBT and CBTLV bus switches and the AVC(Advanced Very-low-voltage CMOS) logic family. Nolan hadpreviously worked in TI's BiPolar wafer fabrication family as a photo lithography engineer. He has a BS in electronicsengineering technology and a MS in electronics engineeringtechnology from Southeastern Oklahoma State University.Ji Park's Advanced Computing Solutions team at TI isresponsible for the strategic development of advanced logicdevices for PCs, workstations, and servers. Park received aBSEE from the University of Texas.。

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一种可校准的高精度低温偏的片内高速振荡设计

一种可校准的高精度低温偏的片内高速振荡设计

一种可校准的高精度低温偏的片内高速振荡设计饶喜冰;孙志欣【摘要】提出了一种可校准,高精度,低温偏的RC高速振荡器的设计.该高速振荡采用数字校准的方式实现目标频率±0.4％以内的偏差;通过温度补偿设计得到全温范围±1.5％以内的频率偏差.版图设计上,比较器和电容组的对称排列布置保证其振荡的稳定性.仿真计算及实际流片测试结果均表明,该HIRC具有较高的频率稳定性,满足各项设计指标.【期刊名称】《电子器件》【年(卷),期】2019(042)001【总页数】6页(P76-81)【关键词】RC振荡器;自校准;高精度;低温偏【作者】饶喜冰;孙志欣【作者单位】无锡中微爱芯电子有限公司,江苏无锡214072;无锡中微爱芯电子有限公司,江苏无锡214072【正文语种】中文【中图分类】TN751在MCU类电路中,都需要一个高速振荡时钟信号作为整个电路的节拍器。

怎么做到无需引入外围器件,实现高精度、低温偏、低功耗的片内稳定高速振荡时钟就是设计的重点。

本设计基于RC振荡原理,利用偏置电流对电容充放电来获得振荡信号。

采用简单易集成的RC振荡,实现高精度、低温偏、低功耗的片内高速振荡,是很有价值的。

在芯片制程中,由于光刻、刻蚀、扩散和离子注入等过程中图形会收缩或扩张,出现剂量误差、尺寸误差等都会导致理论设计与实际结果的偏差;同时,片与片之间也存在个体偏差。

为了保证每一颗芯片的振荡高精度,本设计通过对电阻电容值的校准,实现±0.4%以内的频率精度;通过负温度系数电阻与正温度系数MOS管的合理抵消匹配,实现±1.5%以内的全温-40 ℃～120 ℃的频率偏差。

满足整个MCU的稳定时钟设计需求。

本文将在0.11 μm 1.5V CMOS的工艺平台上,以24 MHz典型频率为例,完成高速振荡设计。

整个电路供电及其电流:1.5 V/150 mA。

按照本文设计思路的原理和原则,可以将该设计结构推广到各类工艺平台及其不同的振荡频率需求上。