AML8726-M3_4DDR3_TEST_REF_V1.0

DDR3L SDRAMMT41K1G4 – 128 Meg x 4 x 8 banksMT41K512M8 – 64 Meg x 8 x 8 banks MT41K256M16 – 32 Meg x 16 x 8 banksDescriptionDDR3L SDRAM (1.35V) is a low voltage version of the DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM (Die Rev :E) data sheet specifications when running in 1.5V compatible mode.Features•V DD = V DDQ = 1.35V (1.283–1.45V)•Backward compatible to V DD = V DDQ = 1.5V ±0.075V –Supports DDR3L devices to be backward com-patible in 1.5V applications•Differential bidirectional data strobe•8n-bit prefetch architecture•Differential clock inputs (CK, CK#)•8 internal banks•Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals •Programmable CAS (READ) latency (CL)•Programmable posted CAS additive latency (AL)•Programmable CAS (WRITE) latency (CWL)•Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])•Selectable BC4 or BL8 on-the-fly (OTF)•Self refresh mode•T C of 105°C–64ms, 8192-cycle refresh up to 85°C–32ms, 8192-cycle refresh at >85°C to 95°C–16ms, 8192-cycle refresh at >95°C to 105°C •Self refresh temperature (SRT)•Automatic self refresh (ASR)•Write leveling•Multipurpose register•Output driver calibrationOptions Marking •Configuration– 1 Gig x 41G4–512 Meg x 8512M8–256 Meg x 16256M16•FBGA package (Pb-free) – x4, x8–78-ball (9mm x 10.5mm) Rev. E RH–78-ball (7.5mm x 10.6mm) Rev. N RG–78-ball (8mm x 10.5mm) Rev. P DA •FBGA package (Pb-free) – x16–96-ball (9mm x 14mm) Rev. E HA–96-ball (7.5mm x 13.5mm) Rev. N LY–96-ball (8mm x 14mm) Rev. P TW •Timing – cycle time–938ps @ CL = 14 (DDR3-2133)-093– 1.07ns @ CL = 13 (DDR3-1866)-107– 1.25ns @ CL = 11 (DDR3-1600)-125•Operating temperature–Commercial (0°C T C +95°C)None–Industrial (–40°C T C +95°C)IT–Automotive (–40°C T C +105°C)AT •Revision:E/:N/:PTable 1: Key Timing ParametersNotes: 1.Backward compatible to 1600, CL = 11 (-125).2.Backward compatible to 1866, CL = 13 (-107).Table 2: AddressingFigure 1: DDR3L Part Numbers([DPSOH 3DUW 1XPEHU 07 . 0 '$ 3Note:1.Not all options listed can be combined to define an offered product. Use the part catalog search on for available offerings.4Gb: x4, x8, x16 DDR3L SDRAMDescription质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备祝您:工作顺利，生活愉快!以深圳市美光存储技术有限公司提供的参数为例，以下为MT41K512M8DA-107_P的详细参数，仅供参考DDR3L 1.35V Slew Rate Definitions for Differential Input SignalsInput slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and meas-ured, as shown in Table 31 and Figure 22. The nominal slew rate for a rising signal isdefined as the slew rate between V IL,diff,max and V IH,diff,min. The nominal slew rate for afalling signal is defined as the slew rate between V IH,diff,min and V IL,diff,max.Table 31: DDR3L 1.35V Differential Input Slew Rate DefinitionOutput Driver ImpedanceThe output driver impedance is selected by MR1[5,1] during initialization. The selected value is able to maintain the tight tolerances specified if proper ZQ calibration is per-formed. Output specifications refer to the default output driver unless specifically sta-ted otherwise. A functional representation of the output buffer is shown below. The out-put driver impedance R ON is defined by the value of the external reference resistor RZQ as follows:•R ON,x = RZQ /y (with RZQ = 240ȍ ±1%; x = 34ȍ or 40ȍ with y = 7 or 6, respectively)The individual pull-up and pull-down resistors R ON(PU) and R ON(PD) are defined as fol-lows:•R ON(PU) = (V DDQ - V OUT )/|I OUT |, when R ON(PD) is turned off •R ON(PD) = (V OUT )/|I OUT |, when R ON(PU) is turned offFigure 28: Output DriverOutput driverChip in drive mode V DDQV SSQV OUT DQ4Gb: x4, x8, x16 DDR3L SDRAMOutput Driver Impedance。

PCB-PF043BMB-06主板U1（TG1611ADJ）在路实测数据U2（TG1611ADJ）在路实测数据U3（TG1611ADJ）在路实测数据U4（RT9701CB）在路实测数据USB电源转换器/ST9001/RT9701CBU5（AIC1848）在路实测数据U6（SGM7222）在路实测数据USB模拟开关芯片U9 (AU6438GBS) 在路实测数据U8 (AM7213D)在路实测数据4．3寸图像浏览器常见故障维修不开机故障4．3寸图像浏览器正常开机电流在0.05—0.18之间正常工作组电压BA T4.2V VCC3.3V VCC1.8V无开机程序或主控AM7213D工作异常时，按键开机电流在0.05—0.08之间按键开机电流在0.02—0.05之间时则组电压输出开路或短路电流大故障浏览器能工作时常见L1（2.7UH）TG1611或AM7213D不良浏览器工作异常VCC33VCC18短路显示USB MODE3：U6（SGM7222）不良不读卡：U8（AM7213D）CF-DMARODRV-VBUSLCD-D7--LCD-D8Y3（32768HZ）不读外卡：Y1（12M）U7（AU6438JBS）U5（AIC1848）不锁内卡：SD-WP端短路自动开机：R100（1M）开路自动关机：EXT-INT1控制端短路读卡时自动关机：R2（60K）开路导致BA T42电压升高升级死机：U10（W25Q16）程序出错升级卡机：Y3（32768HZ）开机无显示：U10（W25Q16）程序出错L7（10UH）电感匝间短路升级后不能自动关机：SD-CLK C65短路显示失真：TCON输出端LCD-D0—LCD-D17 RP1—RP4开路或短路LOGO显示正常，进入图片显示失真，主控AM7213D工作异常复制错乱：LCD-D18—LCD-D19短路。