74ACT534FCX中文资料

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TL󰁋F󰁋996554ACT󰁋74ACT534

Octal

Flip-Flop

with

TRI-STATE

Outputs

March1993

54ACT󰁋74ACT534

OctalDFlip-FlopwithTRI-STATE󰀃Outputs

GeneralDescription

The’ACT534isahigh-speed󰀷low-poweroctalD-typeflip-

flopfeaturingseparateD-typeinputsforeachflip-flopand

TRI-STATEoutputsforbus-orientedapplications󰀟Abuff-

eredClock(CP)andOutputEnable(OE)arecommontoall

flip-flops󰀟The’ACT534isthesameasthe’ACT374except

thattheoutputsareinverted󰀟Features

YICCandIOZreducedby50%

YEdge-triggeredD-typeinputs

YBufferedpositiveedge-triggeredclock

YTRI-STATEoutputsforbus-orientedapplications

YOutputssource󰁋sink24mA

Y’ACT534hasTTL-compatibleinputs

YInvertedoutputversionof’ACT374

LogicSymbols

TL󰁋F󰁋9965–1IEEE󰁋IEC

TL󰁋F󰁋9965–2ConnectionDiagrams

PinAssignment

forDIP󰀷FlatpakandSOIC

TL󰁋F󰁋9965–3

PinAssignment

forLCC

TL󰁋F󰁋9965–4PinNamesDescription

D0–D7DataInputs

CPClockPulseInput

OETRI-STATEOutputEnableInput

O0–O7ComplementaryTRI-STATEOutputs

TRI-STATE󰀃isaregisteredtrademarkofNationalSemiconductorCorporation󰀟FACTTMisatrademarkofNationalSemiconductorCorporation󰀟

C1995NationalSemiconductorCorporationRRD-B30M75󰁋PrintedinU󰀟S󰀟A󰀟元器件交易网www.cecb2b.com

FunctionalDescription

The’ACT534consistsofeightedge-triggeredflip-flopswith

individualD-typeinputsandTRI-STATEcomplementary

outputs󰀟ThebufferedclockandbufferedOutputEnableare

commontoallflip-flops󰀟Theeightflip-flopswillstorethe

stateoftheirindividualDinputsthatmeetthesetupand

holdtimesrequirementsontheLOW-to-HIGHClock(CP)transition󰀟WiththeOutputEnable(OE)LOW󰀷thecontents

oftheeightflip-flopsareavailableattheoutputs󰀟Whenthe

OEisHIGH󰀷theoutputsgotothehighimpedancestate󰀟

OperationoftheOEinputdoesnotaffectthestateofthe

flip-flops󰀟

LogicDiagram

TL󰁋F󰁋9965–5

Pleasenotethatthisdiagramisprovidedonlyfortheunderstandingoflogicoperationsandshouldnotbeusedtoestimatepropagationdelays󰀟

FunctionTable

InputsOutput

CPOEDO

LLHL

LLLH

LLXO0XHXZ

HeHIGHVoltageLevelLeLOWVoltageLevelXeImmaterialLeLOW-to-HIGHClockTransitionZeHighImpedanceO0eValuestoredfrompreviousclockcycle

2元器件交易网www.cecb2b.com

AbsoluteMaximumRatings(Note1)

IfMilitary󰁋Aerospacespecifieddevicesarerequired󰀷

pleasecontacttheNationalSemiconductorSales

Office󰁋Distributorsforavailabilityandspecifications󰀟

SupplyVoltage(VCC)b0󰀟5Vtoa7󰀟0V

DCInputDiodeCurrent(IIK)

VIeb0󰀟5Vb20mA

VIeVCCa0󰀟5Va20mA

DCInputVoltage(VI)b0󰀟5VtoVCCa0󰀟5V

DCOutputDiodeCurrent(IOK)

VOeb0󰀟5Vb20mA

VOeVCCa0󰀟5Va20mA

DCOutputVoltage(VO)b0󰀟5VtoVCCa0󰀟5V

DCOutputSource

orSinkCurrent(IO)g50mA

DCVCCorGroundCurrent

perOutputPin(ICCorIGND)g50mA

StorageTemperature(TSTG)b65󰀄Ctoa150󰀄C

JunctionTemperature(TJ)

CDIP175󰀄C

PDIP140󰀄C

Note1󰀌Absolutemaximumratingsarethosevaluesbeyondwhichdamagetothedevicemayoccur󰀟Thedatabookspecificationsshouldbemet󰀷withoutexception󰀷toensurethatthesystemdesignisreliableoveritspowersupply󰀷temperature󰀷andoutput󰁋inputloadingvariables󰀟Nationaldoesnotrecom-mendoperationofFACTTMcircuitsoutsidedatabookspecifications󰀟RecommendedOperating

Conditions

SupplyVoltage(VCC)

’ACT4󰀟5Vto5󰀟5V

InputVoltage(VI)0VtoVCCOutputVoltage(VO)0VtoVCCOperatingTemperature(TA)

74ACTb40󰀄Ctoa85󰀄C

54ACTb55󰀄Ctoa125󰀄C

MinimumInputEdgeRate(DV󰁋Dt)

’ACTDevices

VINfrom0󰀟8Vto2󰀟0V

VCC󰀅4󰀟5V󰀷5󰀟5V125mV󰁋ns

DCCharacteristicsfor’ACTFamilyDevices

74ACT54ACT74ACT

SymbolParameterVCCTAeTAeTAeUnitsConditions(V)a25󰀄Cb55󰀄Ctoa125󰀄Cb40󰀄Ctoa85󰀄C

TypGuaranteedLimits

VIHMinimumHighLevel4󰀟51󰀟52󰀟02󰀟02󰀟0VVOUTe0󰀟1V

InputVoltage5󰀟51󰀟52󰀟02󰀟02󰀟0orVCCb0󰀟1V

VILMaximumLowLevel4󰀟51󰀟50󰀟80󰀟80󰀟8VVOUTe0󰀟1V

InputVoltage5󰀟51󰀟50󰀟80󰀟80󰀟8orVCCb0󰀟1V

VOHMinimumHighLevel4󰀟54󰀟494󰀟44󰀟44󰀟4VIOUTeb50mA

OutputVoltage5󰀟55󰀟495󰀟45󰀟45󰀟4

󰀁VINeVILorVIH4󰀟53󰀟863󰀟703󰀟76VIOHb24mA

5󰀟54󰀟864󰀟704󰀟76b24mA

VOLMaximumLowLevel4󰀟50󰀟0010󰀟10󰀟10󰀟1VIOUTe50mA

OutputVoltage5󰀟50󰀟0010󰀟10󰀟10󰀟1

󰀁VINeVILorVIH4󰀟50󰀟360󰀟500󰀟44VIOL24mA

5󰀟50󰀟360󰀟500󰀟4424mA

IINMaximumInputLeakageCurrent5󰀟5g0󰀟1g1󰀟0g1󰀟0mAVIeVCC󰀷GND

IOZMaximumTRI-STATE󰀃5󰀟5g0󰀟25g5󰀟0g2󰀟5mAVIeVIL󰀷VIHCurrentVOeVCC󰀷GND

ICCTMaximum5󰀟50󰀟61󰀟61󰀟5mAVIeVCCb2󰀟1V

ICC󰁋Input

󰀁Alloutputsloaded󰀥thresholdsoninputassociatedwithoutputundertest󰀟

3元器件交易网www.cecb2b.com

74hc14中文资料

74HC14中文资料

74HC14的作用：六反相斯密特触发器真值表：Y=A

Input输入output输出

图1引脚功能极限参数：SupplyVoltage电源电压7VInputVoltage输入电压7VOperatingFreeAirTemperatureRange自由空气温度范围0℃to+70℃

StorageTemperatureRange储存温度范围-65℃to+150℃RecommendedOperatingConditions建议操作条件Symbol符号Parameter参数最小典型最大UNIT单位

VCCSupplyVoltage电源电压4.7555.25V

VT+Positive-GoingInputThresholdVoltage正向输入阈值电压(Note2)1.41.61.9V

VT-Negative-GoingInputThresholdVoltage反向输入阈值电压(Note2)0.50.81V

HYSInputHysteresis输入滞后(Note2)0.40.8-V

IOHHIGHLevelOutputCurrent高电平输出电流---0.4mA

IOLLOWLevelOutputCurrent低电平输出电流--8mA

TAFreeAirOperatingTemperature工作温度0-70℃

Note2:VCC=5V.

ElectricalCharacteristics电气特性

overrecommendedoperatingfreeairtemperaturerange(unlessotherwisenoted)Symbol符号Parameter参数Conditions条件最小典型最大UNIT单位

VIInputClampVoltage输入钳位电压VCC=最小,II=-18mA---1.5V

VOHHIGHLevelOutputVoltage输出高电平电压VCC=最小,IOH=最大VIL=最大2.73.4-V

74LVC2G53资料

1.General description

The 74LVC2G53 is a low-power, low-voltage, high-speed, Si-gate CMOS device.

The 74LVC2G53 provides one analog multiplexer/demultiplexer with a digital selectinput(S),twoindependentinputs/outputs(Y0andY1),acommoninput/output(Z)andanactive LOW enable input (E). When pinE is HIGH, the switch is turned off.

Schmitt-trigger action at the select and enable inputs makes the circuit tolerant of slowerinput rise and fall times across the entire VCC range from 1.65 V to 5.5 V.

2.Features

sWide supply voltage range from 1.65V to 5.5V

sVery low ON resistance:

x7.5Ω (typical) at VCC=2.7V

x6.5Ω (typical) at VCC=3.3V

x6Ω (typical) at VCC=5V

sSwitch current capability of 32 mA

sHigh noise immunity

sCMOS low-power consumption

sTTL interface compatibility at 3.3 V

sLatch-up performance meets requirements of JESD 78 Class I

MC74AC163中文资料

5-1FACT DATASynchronous PresettableBinary CounterThe MC74AC161/74ACT161 and MC74AC163/74ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The MC74AC161/74ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. The MC74AC163/74ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock.•Synchronous Counting and Loading•High-Speed Synchronous Expansion•Typical Count Rate of 125 MHz•Outputs Source/Sink 24 mA•′ACT161 and ′ACT163 Have TTL Compatible Inputs15161413121110

HD74AC539资料

HD74AC539Dual 1-of-4 Decoder with 3-State Output

Description

The HD74AC539 contains two inpedendent decoders. Each accepts two Address (A0, A1) input signals anddecodes them to select one of four mutually exclusive outputs. A polarity control input (P) determineswhether the outputs are active HIGH (P = L) or active LOW (P = H). An active LOW input Enable (E) isavailable for data demultiplexing; data is routed to the selected output in non-inverted form in the activeLOW mode or in inverted form in the active HIGH mode. A HIGH signal on the active LOW OutputEnable (OE) input forces the 3-state outputs to the high impedance state.

Feature

• Outputs Source/Sink 24 mAHD74AC539

2Pin Arrangement

1011121314151617181920VCC

O3b

A1b

A0b

EaO2b

O1b

O0b

OEb

A0a

A1a

O3a

O2a

GNDOEaPa

O0d

O1a

(Top view)

Logic Symbol

DECODER aA0

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74ACT534FCX中文资料

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74hc14中文资料

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