A-25GA产品规格书

2）、压力和流量
所有氧气传感器均对样气压力变化敏感。当流量变化控制在 1~5SCFH 之间时，其 引起的压力变化在分析仪的有效范围之内并且不会对分析仪的读数发生影响，尽管样 气流量的控制并不对变送器/分析仪的分析产生关键的影响，采用必要的流量控制装置 对样气流量进行控制仍然是必备的。我们推荐的适宜流量为 2 SCFH（1L 每分钟）。
2． 压力和流量： 入口压力：推荐 5~30psi，最大不要超过 100psi。 出口压力：应该排空，或接入其他管路但不能堵塞。
3．建立： A． 氧传感器：要试图打开传感器，因为传感器中含有腐蚀性液体，如果接触会对人 体有害，当传感器发生液体泄漏时应根据当地有关环保制度及时处理掉。 B． 安装：本仪器用于便携式测量或在室内固定安装使用，如果在室外安装需另配置 专门的经厂家推荐的外壳体。 C． 电源：本仪器利用可充电电池供电，应按手册所示给仪器充电，充电时最好使用 仪器提供的充电器，并保证仪器离火电插座有一定距离。充完电后切忌猛拉充电 器拽离插座或分析仪。 D． 温度：最大操作温度+45℃。 E． 热源：操作和存贮仪器时请远离发热热源。 F． 液体：分析仪不能被侵入任何液体中，也要小心液体或固体掉入分析仪中。 G． 操作：不要太用力拨仪器开关或阀门，移动仪器前要确保断开所有连接线。
此仪器的序列号（8 位）能够在分析仪外部找到，请您将该系列号填在本手册中下 面标注处，以此作为您的永久使用标识，并作为质保和维护的唯一标识。
序列号（Serial Number）：
出于对用户最佳的使用及最小花费的考虑，此款仪器选用了最可靠的材料及元件 设计。此款仪器已经通过制造者完全的检验及检测，尽管如此，飞速发展的现代电子 设备始终是需要不断的维护，此手册提供的信息能够使您及时有效的维护您所购买的 分析仪表，并确保我们能够对每块售出仪表的有效保证。

GW22A-252Ⅲ型隔离开关安装维修使用说明书编号：0TK.466.5028山东泰开隔离开关有限公司二○一二年十一月目录一、概述 (3)二、使用环境 (3)三、产品特点 (4)四、产品分类与技术参数 (5)五、产品结构与动作原理 (6)六、包装和发运 (9)七、验货和储存 (9)八、卸货和吊装 (10)九、安装与调试 (11)十、安装现场验收前的验收和微调 (14)十一、随机文件 (15)十二、订货须知 (15)一、概述………………………………………………………………………………1.产品用途GW22A-252D(W)Ⅲ型单柱垂直断口单臂伸缩钳夹式户外三相高压交流隔离开关，（以下简称GW22A-252Ⅲ型隔离开关）是在额定频率50Hz，额定电压252kV的供电系统中，供高压线路在无载荷情况下进行换接，以及对被检修的高压母线、断路器等高压电气设备与带电的高压线路进行电气隔离之用。

同时还用于当电网系统中的运行方式需要改变，在不断开或关合负载电流的前提下，在倒闸操作过程中进行切合母线转移电流及电压互感器、避雷器等规定范围内的充电电流。

2.产品规格型号说明（举例说明）G W 22 A - 252 D (W) / J 3150- 50 -Ⅲ3.符合标准◆GB 1985-2004 《高压交流隔离开关和接地开关》◆GB/T 11022-1999 《高压开关设备和控制设备标准的共用技术要求》◆DL/T 486-2000 《高压交流隔离开关和接地开关订货技术条件》◆DL/T 593-2006 《高压交流隔离开关和接地开关》二、使用环境…………………………………………………………………………◆环境温度为-50℃～+50℃；◆海拔不超过2000m（2500m及以上可按用户要求提高产品适应能力）；◆风压不超过700Pa（相当于风速不超过34m/s）；◆地震烈度不超过9度；◆覆冰厚度不超过20mm；◆环境污秽等级为Ⅲ、Ⅳ级；◆安装场所应无易燃、易爆危险，化学腐蚀及剧烈振动。

底视图NPNPCOM -Vo+Vo-Vo1+Vo1-Vo2NP +Vo2L NFGL N FG -Vo NP NP8765NP NR25-BNR25-C NR25-APIN 管脚定义1234FG N +Vo L尺寸单位 : mm[inch]管脚直径公差 : ±0.20[±0.008]注:其他尺寸公差 : ±0.50[±0.020]前视图25W AC/DC模块电源产品性能★ 宽输入电压：85-264VAC /100-375VDC ★ 高效率，高功率密度，稳压输出★ PCB 双列直插安装方式/DIP★输出电压精度 ±1%★ 具有输出过流,短路等保护功能★ 输入输出高隔离:3000VAC ★ 工业级产品设计，小体积★ 三年质量保证NR25-A/B/Cxx 系列-----是尼博星为客户提供的小体积高功率密度绿色模块电源，该系列电源具有交直流两用、输入电压范围宽、高可靠性、高精度、安全隔离等优点。

广泛适用于工控和电力仪器仪表、智能家居，新能源领域等对体积要求苛刻的场合，产品EMC 性能好，适配相应 EMC 外围电路满足多行业产品需求。

NR25-A0316.5W3.3V/5000mA --77%3000μF 70.0×48.0×23.5mm NR25-A0525W 5V/5000mA --78%3000μF NR25-A099V/2800mA --78%2000μF NR25-A1212V/2100mA --80%2000μF NR25-A1515V/1660mA --81%1000μF NR25-A2424V/1050mA --84%820μF NR25-C0525W +5V/2500mA -5V/2500mA 75%1000μF 70.0×48.0×23.5mm NR25-C12+12V/1050mA -12V/1050mA 77%560μF NR25-C15+15V/830mA -15V/830mA 78%470μF NR25-C24+24V/520mA-24V/520mA80%220μFNR25-B050525W5V/4000mA 5V/1000mA 75%2000μF 70.0×48.0×23.5mmNR25-B05125V/4000mA 12V/420mA 76%1500μF NR25-B05155V/4000mA 15V/330mA 77%1500μF NR25-B05245V/4000mA24V/210mA78%1500μF输入电压范围交流输入85VAC --264VAC 直流输入100VDC --375VDC 输入频率范围47Hz -63Hz 空载功耗--0.2W --输入电流115VAC --520mA --230VAC--260mA--输出电压精度3.3V 输出--±3%--其他电压输出--±1%--线性调整率满载主路--±1%--辅路--±3%--负载调整率10%~100%负载单路输出--±3%--双路输出(平衡负载)①--±10%--输出纹波噪声②20MHz 带宽（峰-峰值）--100mV --输出短路保护可长期短路,自恢复输出过流保护≥110%Io最小负载0----启动延迟时间--1s --掉电保持时间--20ms--*注：①平衡负载是主路与辅路的输出负载以相同比例变化。

Features•High-performance, low-power Atmel ®AVR ®XMEGA ® 8/16-bit Microcontroller •Nonvolatile program and data memories–256KBytes of in-system self-programmable flash –8KBytes boot section –4KBytes EEPROM–16KBytes internal SRAM •Peripheral features–Four-channel DMA controller –Eight-channel event system –Seven 16-bit timer/countersFour timer/counters with four output compare or input capture channels Three timer/counters with two output compare or input capture channels High resolution extension on all timer/countersAdvanced waveform extension (AWeX) on one timer/counter –One USB device interfaceUSB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant 32 Endpoints with full configuration flexibility –Six USARTs with IrDA support for one USART–Two two-wire interfaces with dual address match (I 2C and SMBus compatible)–Two serial peripheral interfaces (SPIs)–AES and DES crypto engine–CRC-16 (CRC-CCITT) and CRC-32 (IEEE ® 802.3) generator–32-bit real time counter (RTC) with separate oscillator and battery backup system –Two sixteen-channel, 12-bit, 2msps Analog to Digital Converters –One two-channel, 12-bit, 1msps Digital to Analog Converter–Four Analog Comparators with window compare function, and current sources –External interrupts on all general purpose I/O pins–Programmable watchdog timer with separate on-chip ultra low power oscillator –QTouch ® library supportCapacitive touch buttons, sliders and wheels•Special microcontroller features–Power-on reset and programmable brown-out detection –Internal and external clock options with PLL and prescaler –Programmable multilevel interrupt controller –Five sleep modes–Programming and debug interfacesJTAG (IEEE 1149.1 compliant) interface, including boundary scan PDI (Program and Debug Interface)•I/O and packages–47 programmable I/O pins –64-lead TQFP –64-pad QFN •Operating voltage –1.6 – 3.6V•Operating frequency –0 – 12MHz from 1.6V –0 – 32MHz from 2.7VTypical Applications•Industrial control •Climate control •Low power battery applications •Factory automation •RF and ZigBee ®•Power tools •Building control •USB connectivity•HVAC•Board control •Networking •Utility metering •White goods•Optical•Medical applications8/16-bit Atmel XMEGA A3BU MicrocontrollerATxmega256A3BU8362E–AVR–01/121.Ordering InformationNotes: 1.This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.2.Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). AlsoHalide free and fully Green.3.For packaging information, see ”Packaging information” on page 70.4.Tape and reel.Ordering Code Flash EEPROMSRAM Speed [MHz]Power Supply Package (1)(2)(3)TempATxmega256A3BU-AU 256K + 8K 4K 16K 32 1.6 - 3.6V 64A-40°C - 85°CATxmega256A3BU-AUR (4)A Txmega256A3BU-MH 256K + 8K4K16K321.6 - 3.6V64M2A Txmega256A3BU-MHR (4)Package Type64A 64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)64M264-pad, 9 x 9 x 1.0mm body, lead pitch 0.50mm, 7.65mm exposed pad, quad flat no-lead package (QFN)2.Pinout/Block DiagramFigure 2-1.Block diagram and pinout.Notes: 1.For full details on pinout and pin functions refer to ”Pinout and Pin Functions” on page 59.2.The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure goodmechanical stability.3.OverviewThe Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bitmicrocontrollers based on the AVR enhanced RISC architecture. By executing instructions in asingle clock cycle, the AVR XMEGA device achieves CPU throughput approaching one millioninstructions per second (MIPS) per megahertz, allowing the system designer to optimize powerconsumption versus processing speed.The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32registers are directly connected to the arithmetic logic unit (ALU), allowing two independent reg-isters to be accessed in a single instruction, executed in one clock cycle. The resultingarchitecture is more code efficient while achieving throughputs many times faster than conven-tional single-accumulator or CISC based microcontrollers.The XMEGA A3BU devices provide the following features: in-system programmable flash withread-while-write capabilities; internal EEPROM and SRAM; four-channel DMA controller; eight-channel event system and programmable multilevel interrupt controller; 47 general purpose I/Olines; 32-bit real-time counter (RTC) with battery backup system; seven flexible 16-bitTimer/Counters with compare modes and PWM; one full speed USB 2.0 interface; six USARTs;two two-wire serial interfaces (TWIs); two serial peripheral interfaces (SPIs); AES and DES cryp-tographic engine; two 16-channel, 12-bit ADCs with programmable gain; one 2-channel 12-bitDAC; four analog comparators (ACs) with window mode; programmable watchdog timer withseparate internal oscillator; accurate internal oscillators with PLL and prescaler; and program-mable brown-out detection.The program and debug interface (PDI), a fast, two-pin interface for programming and debug-ging, is available. The devices also have an IEEE std. 1149.1 compliant JTAG interface, and thiscan also be used for boundary scan, on-chip debug and programming.The XMEGA A3BU devices have five software selectable power saving modes. The idle modestops the CPU while allowing the SRAM, DMA controller, event system, interrupt controller, andall peripherals to continue functioning. The power-down mode saves the SRAM and registercontents, but stops the oscillators, disabling all other functions until the next TWI, USB resume,or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter con-tinues to run, allowing the application to maintain a timer base while the rest of the device issleeping. In standby mode, the external crystal oscillator keeps running while the rest of thedevice is sleeping. This allows very fast startup from the external crystal, combined with lowpower consumption. In extended standby mode, both the main oscillator and the asynchronoustimer continue to run. To further reduce power consumption, the peripheral clock to each individ-ual peripheral can optionally be stopped in active mode and idle sleep mode.Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheelsfunctionality into AVR microcontrollers.The devices are manufactured using Atmel high-density, nonvolatile memory technology. Theprogram flash memory can be reprogrammed in-system through the PDI or JTAG interfaces. Aboot loader running in the device can use any interface to download the application program tothe flash memory. The boot loader software in the boot flash section will continue to run whilethe application flash section is updated, providing true read-while-write operation. By combiningan 8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerfulmicrocontroller family that provides a highly flexible and cost effective solution for many embed-ded applications.All Atmel AVR XMEGA devices are supported with a full suite of program and system develop-ment tools, including C compilers, macro assemblers, program debugger/simulators,programmers, and evaluation kits.3.1Block DiagramFigure 3-1.XMEGA A3BU block diagram.4.ResourcesA comprehensive set of development tools, application notes and datasheets are available fordownload on /avr.4.1Recommended reading•Atmel AVR XMEGA AU manual•XMEGA application notesThis device data sheet only contains part specific information with a short description of eachperipheral and module. The XMEGA AU manual describes the modules and peripherals indepth. The XMEGA application notes contain example code and show applied use of the mod-ules and peripherals.All documentations are available from /avr.5.Capacitive touch sensingThe Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaceson most Atmel AVR microcontrollers. The patented charge-transfer signal acquisition offersrobust sensing and includes fully debounced reporting of touch keys and includes Adjacent KeySuppression® (AKS®) technology for unambiguous detection of key events. The QTouch libraryincludes support for the QTouch and QMatrix acquisition methods.Touch sensing can be added to any application by linking the appropriate Atmel QTouch libraryfor the AVR microcontroller. This is done by using a simple set of APIs to define the touch chan-nels and sensors, and then calling the touch sensing API’s to retrieve the channel informationand determine the touch sensor states.The QTouch library is FREE and downloadable from the Atmel website at the following location:/qtouchlibrary. For implementation details and other information, refer to theQTouch library user guide - also available for download from the Atmel website.6.AVR CPU6.1Features•8/16-bit, high-performance Atmel AVR RISC CPU–142 instructions–Hardware multiplier•32x8-bit registers directly connected to the ALU•Stack in RAM•Stack pointer accessible in I/O memory space•Direct addressing of up to 16MB of program memory and 16MB of data memory•True 16/24-bit access to 16/24-bit I/O registers•Efficient support for 8-, 16-, and 32-bit arithmetic•Configuration change protection of system-critical features6.2OverviewAll Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is toexecute the code and perform all calculations. The CPU is able to access memories, performcalculations, control peripherals, and execute the program in the flash memory. Interrupt han-dling is described in a separate section, refer to ”Interrupts and Programmable MultilevelInterrupt Controller” on page 30.6.3Architectural OverviewIn order to maximize performance and parallelism, the AVR CPU uses a Harvard architecturewith separate memories and buses for program and data. Instructions in the program memoryare executed with single-level pipelining. While one instruction is being executed, the nextinstruction is pre-fetched from the program memory. This enables instructions to be executed onevery clock cycle. For details of all AVR instructions, refer to /avr.Figure 6-1.Block diagram of the AVR CPU architecture.The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers orbetween a constant and a register. Single-register operations can also be executed in the ALU.After an arithmetic operation, the status register is updated to reflect information about the resultof the operation.The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purposeworking registers all have single clock cycle access time allowing single-cycle arithmetic logicunit (ALU) operation between registers or between a register and an immediate. Six of the 32registers can be used as three 16-bit address pointers for program and data space addressing,enabling efficient address calculations.The memory spaces are linear. The data memory space and the program memory space aretwo different memory spaces.The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, theEEPROM can be memory mapped in the data memory.All I/O status and control registers reside in the lowest 4KB addresses of the data memory. Thisis referred to as the I/O memory space. The lowest 64 addresses can be accessed directly, or asthe data space locations from 0x00 to 0x3F. The rest is the extended I/O memory space, rangingfrom 0x0040 to 0x0FFF. I/O registers here must be accessed as data space locations using load(LD/LDS/LDD) and store (ST/STS/STD) instructions.The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessedthrough the five different addressing modes supported in the AVR architecture. The first SRAMaddress is 0x2000.Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.The program memory is divided in two sections, the application program section and the bootprogram section. Both sections have dedicated lock bits for write and read/write protection. TheSPM instruction that is used for self-programming of the application flash memory must reside inthe boot program section. The application section contains an application table section with sep-arate lock bits for write and read/write protection. The application table section can be used forsafe storing of nonvolatile data in the program memory.6.4ALU - Arithmetic Logic UnitThe arithmetic logic unit (ALU) supports arithmetic and logic operations between registers orbetween a constant and a register. Single-register operations can also be executed. The ALUoperates in direct connection with all 32 general purpose registers. In a single clock cycle, arith-metic operations between general purpose registers or between a register and an immediate areexecuted and the result is stored in the register file. After an arithmetic or logic operation, thestatus register is updated to reflect information about the result of the operation.ALU operations are divided into three main categories – arithmetic, logical, and bit functions.Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementa-tion of 32-bit aritmetic. The hardware multiplier supports signed and unsigned multiplication andfractional format.6.4.1Hardware MultiplierThe multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware mul-tiplier supports different variations of signed and unsigned integer and fractional numbers:•Multiplication of unsigned integers•Multiplication of signed integers•Multiplication of a signed integer with an unsigned integer•Multiplication of unsigned fractional numbers•Multiplication of signed fractional numbers•Multiplication of a signed fractional number with an unsigned oneA multiplication takes two CPU clock cycles.6.5Program FlowAfter reset, the CPU starts to execute instructions from the lowest address in the flash program-memory ‘0.’ The program counter (PC) addresses the next instruction to be fetched.Program flow is provided by conditional and unconditional jump and call instructions capable ofaddressing the whole address space directly. Most AVR instructions use a 16-bit word format,while a limited number use a 32-bit format.During interrupts and subroutine calls, the return address PC is stored on the stack. The stack isallocated in the general data SRAM, and consequently the stack size is only limited by the totalSRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highestaddress in the internal SRAM. The SP is read/write accessible in the I/O memory space,enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily beaccessed through the five different addressing modes supported in the AVR CPU.6.6Status RegisterThe status register (SREG) contains information about the result of the most recently executedarithmetic or logic instruction. This information can be used for altering program flow in order toperform conditional operations. Note that the status register is updated after all ALU operations,as specified in the instruction set reference. This will in many cases remove the need for usingthe dedicated compare instructions, resulting in faster and more compact code.The status register is not automatically stored when entering an interrupt routine nor restoredwhen returning from an interrupt. This must be handled by software.The status register is accessible in the I/O memory space.6.7Stack and Stack PointerThe stack is used for storing return addresses after interrupts and subroutine calls. It can also beused for storing temporary data. The stack pointer (SP) register always points to the top of thestack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Dataare pushed and popped from the stack using the PUSH and POP instructions. The stack growsfrom a higher memory location to a lower memory location. This implies that pushing data ontothe stack decreases the SP, and popping data off the stack increases the SP. The SP is auto-matically loaded after reset, and the initial value is the highest address of the internal SRAM. Ifthe SP is changed, it must be set to point above address 0x2000, and it must be defined beforeany subroutine calls are executed or before interrupts are enabled.During interrupts or subroutine calls, the return address is automatically pushed on the stack.The return address can be two or three bytes, depending on program memory size of the device.For devices with 128KB or less of program memory, the return address is two bytes, and hencethe stack pointer is decremented/incremented by two. For devices with more than 128KB of pro-gram memory, the return address is three bytes, and hence the SP is decremented/incrementedby three. The return address is popped off the stack when returning from interrupts using theRETI instruction, and from subroutine calls using the RET instruction.The SP is decremented by one when data are pushed on the stack with the PUSH instruction,and incremented by one when data is popped off the stack using the POP instruction.To prevent corruption when updating the stack pointer from software, a write to SPL will auto-matically disable interrupts for up to four instructions or until the next I/O memory write.After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 onpage 14.6.8Register FileThe register file consists of 32 x 8-bit general purpose working registers with single clock cycleaccess time. The register file supports the following input/output schemes:•One 8-bit output operand and one 8-bit result input•Two 8-bit output operands and one 8-bit result input•Two 8-bit output operands and one 16-bit result input•One 16-bit output operand and one 16-bit result inputSix of the 32 registers can be used as three 16-bit address register pointers for data spaceaddressing, enabling efficient address calculations. One of these address pointers can also beused as an address pointer for lookup tables in flash program memory.分销商库存信息:ATMELATXMEGA256A3BU-AU ATXMEGA256A3BU-MH。