SM5006 series SEIKO NPC CORPORATION —1 Crystal Oscillator Module ICs
OVERVIEW The SM5006 series are crystal oscillator module ICs, that incorporate high-frequency, low current consump-tion oscillator and output buffer circuits. Highly accurate thin-film feedback resistors and high-frequencycapacitors are built-in, eliminating the need for external components to make a stable 3rd overtone oscillator.
FEATURES
I Up to 107MHz operation I Capacitors C G , C D built-in I Inverter amplifier feedback resistor built-in I TTL input level I 16mA (V DD = 4.5V) drive capability I 4mA (V DD = 4.5V) drive capability (5006AH × ) I Output three-state function I 2.7 to 5.5V supply voltage
I Oscillator frequency output
I 8-pin SOP (SM5006 ××× S)
I Chip form (CF5006 ××× )
SERIES CONFIGURATION
Version *1 *1. Chip form devices have designation CF5006 ××× . gm ratio3V operating5V operatingBuilt-in capacitanceR f [k Ω ]Input levelOutput duty level
1/22PRELIMINARY DATAOctober 1999This is preliminary information on a new product now in development or undergoing evaluation.Details are subject to change without notice.M29F200BT M29F200BB2Mbit (256Kb x8or 128Kb x16,Boot Block)Single Supply Flash MemorysSINGLE 5V ±10%SUPPLY VOLTAGE forPROGRAM,ERASE and READ OPERATIONS s ACCESS TIME:45ns sPROGRAMMING TIME –8µs per Byte/Word typical s7MEMORY BLOCKS–1Boot Block (Top or Bottom Location)–2Parameter and 4Main BlockssPROGRAM/ERASE CONTROLLER –Embedded Byte/Word Program algorithm –Embedded Multi-Block/Chip Erase algorithm –Status Register Polling and Toggle Bits –Ready/Busy Output PinsERASE SUSPEND and RESUME MODES –Read and Program another Block during Erase SuspendsUNLOCK BYPASS PROGRAM COMMAND –Faster Production/Batch Programming sTEMPORARY BLOCK UNPROTECTION MODEsLOW POWER CONSUMPTION –Standby and Automatic Standby s100,000PROGRAM/ERASE CYCLES per BLOCKs20YEARS DATA RETENTION –Defectivity below 1ppm/year sELECTRONIC SIGNATURE –Manufacturer Code:0020h –M29F200BT Device Code:00D3h –M29F200BB Device Code:00D4h441TSOP48(N)12x 20mmSO44(M)Figure 1.Logic DiagramAI0291217A0-A16W DQ0-DQ14V CCM29F200BT M29F200BBE V SS15G RPDQ15A–1BYTE RBM29F200BT,M29F200BB2/22Figure 2A.TSOP ConnectionsDQ3DQ9DQ2A6DQ0W A3RB DQ6A8A9DQ13NC A10DQ14A2DQ12DQ10DQ15A–1V CC DQ4DQ5A7DQ7NC NC AI02913M29F200BT M29F200BB 121132425363748DQ8NC NC A1NC A4A5DQ1DQ11G A12A13A16A11BYTE A15A14V SSE A0RP V SS Figure 2B.SO ConnectionsG DQ0DQ8A3A0E V SS A2A1A13V SSA14A15DQ7A12A16BYTE DQ15A–1DQ5DQ2DQ3V CCDQ11DQ4DQ14A9W RB A4NC RPA7AI02914M29F200BT M29F200BB 8234567910111213141516323130292827262524232220191817DQ1DQ9A6A5DQ6DQ134439383736353433A11A10DQ1021DQ12404314241NC A8Table 1.Signal NamesA0-A16Address Inputs DQ0-DQ7Data Inputs/Outputs DQ8-DQ14Data Inputs/OutputsDQ15A–1Data Input/Output or Address Input E Chip Enable G Output Enable W Write EnableRP Reset/Block Temporary Unprotect RB Ready/Busy OutputBYTE Byte/Word Organization Select V CC Supply Voltage V SS GroundNC Not Connected InternallySUMMARY DESCRIPTIONThe M29F200B is a 2Mbit (256Kb x8or 128Kb x16)non-volatile memory that can be read,erased and reprogrammed.These operations can be per-formed using a single 5V supply.On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.The M29F200B is fully backward compatible with the M29F200.The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased.Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory.Program and Erase commands are writ-ten to the Command Interface of the memory.An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents.The end of a program or erase operation can be detected and any error conditions identified.The command set required to control the memory is consistent with JEDEC standards.3/22M29F200BT,M29F200BBThe blocks in the memory are asymmetrically ar-ranged,see Tables 3A and 3B,Block Addresses.The first or last 64Kbytes have been divided into four additional blocks.The 16Kbyte Boot Block can be used for small initialization code to start the microprocessor,the two 8Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the ap-plication may be stored.Chip Enable,Output Enable and Write Enable sig-nals control the bus operation of the memory.They allow simple connection to most micropro-cessors,often without additional logic.The memory is offered in TSOP48(12x 20mm)and SO44packages.Access times of 45ns,55ns,70ns and 90ns are available.The memory is sup-plied with all the bits erased (set to ’1’).SIGNAL DESCRIPTIONSSee Figure 1,Logic Diagram,and Table 1,Signal Names,for a brief overview of the signals connect-ed to this device.Address Inputs (A0-A16).The Address Inputs select the cells in the memory array to access dur-ing Bus Read operations.During Bus Write opera-tions they control the commands sent to the Command Interface of the internal state machine.Data Inputs/Outputs (DQ0-DQ7).The Data In-puts/Outputs output the data stored at the selected address during a Bus Read operation.During Bus Write operations they represent the commandssent to the Command Interface of the internal state machine.Data Inputs/Outputs (DQ8-DQ14).The Data In-puts/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High,V IH .When BYTE is Low,V IL ,these pins are not used and are high impedance.During Bus Write operations the Command Register does not use these bits.When reading the Status Register these bits should be ignored.Data Input/Output or Address Input (DQ15A-1).When BYTE is High,V IH ,this pin behaves as a Data Input/Output pin (as DQ8-DQ14).When BYTE is Low,V IL ,this pin behaves as an address pin;DQ15A–1Low will select the LSB of the Word on the other addresses,DQ15A–1High will select the MSB.Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address In-puts to include this pin when BYTE is Low except when stated explicitly otherwise.Chip Enable (E).The Chip Enable,E,activates the memory,allowing Bus Read and Bus Write op-erations to be performed.When Chip Enable is High,V IH ,all other pins are ignored.Output Enable (G).The Output Enable,G,con-trols the Bus Read operation of the memory.Write Enable (W).The Write Enable,W,controls the Bus Write operation of the memory’s Com-mand Interface.Table 2.Absolute Maximum Ratings (1)Note: 1.Except for the rating ”Operating Temperature Range”,stresses above those listed in the Table ”Absolute Maximum Ratings”maycause permanent damage to the device.These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied.Exposure to Absolute Maximum Rating condi-tions for extended periods may affect device reliability.Refer also to the STMicroelectronics SURE Program and other relevant qual-ity documents.2.Minimum Voltage may undershoot to –2V during transition and for less than 20ns during transitions.SymbolParameterValue Unit T AAmbient Operating Temperature (Temperature Range Option 1)0to 70°C Ambient Operating Temperature (Temperature Range Option 6)–40to 85°C Ambient Operating Temperature (Temperature Range Option 3)–40to 125°C T BIAS Temperature Under Bias –50to 125°C T STG Storage Temperature –65to 150°C V IO (2)Input or Output Voltage –0.6to 6V V CC Supply Voltage –0.6to 6V V IDIdentification Voltage–0.6to 13.5VM29F200BT,M29F200BB4/22Table 3A.M29F200BT Block AddressesSize (Kbytes)Address Range(x8)Address Range(x16)163C000h-3FFFFh 1E000h-1FFFFh 83A000h-3BFFFh 1D000h-1DFFFh 838000h-39FFFh 1C000h-1CFFFh 3230000h-37FFFh 18000h-1BFFFh 6420000h-2FFFFh 10000h-17FFFh 6410000h-1FFFFh 08000h-0FFFFh 6400000h-0FFFFh00000h-07FFFhReset/Block Temporary Unprotect (RP).The Re-set/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to tem-porarily unprotect all Blocks that have been pro-tected.A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low,V IL ,for at least t PLPX .After Reset/Block temporary unprotect goes High,V IH ,the memory will be ready for Bus Read and Bus Write operations after t PHEL or t RHEL ,whichever occurs last.See the Ready/Busy Out-put section,Table 14and Figure 10,Reset/Tem-porary Unprotect AC Characteristics for more details.Holding RP at V ID will temporarily unprotect the protected Blocks in the memory.Program and Erase operations on all blocks will be possible.The transition from V IH to V ID must be slower than t PHPHH .Ready/Busy Output (RB).The Ready/Busy pin is an open-drain output that can be used to identify when the memory array can be read.Ready/Busy is high-impedance during Read mode,Auto Select mode and Erase Suspend mode.After a Hardware Reset,Bus Read and Bus Write operations cannot begin until Ready/Busy be-comes high-impedance.See Table 14and Figure 10,Reset/Temporary Unprotect AC Characteris-tics.During Program or Erase operations Ready/Busy is Low,V OL .Ready/Busy will remain Low duringTable 3B.M29F200BB Block AddressesSize (Kbytes)Address Range(x8)Address Range(x16)6430000h-3FFFFh 18000h-1FFFFh 6420000h-2FFFFh 10000h-17FFFh 6410000h-1FFFFh 08000h-0FFFFh 3208000h-0FFFFh 04000h-07FFFh 806000h-07FFFh 03000h-03FFFh 804000h-05FFFh 02000h-02FFFh 1600000h-03FFFh00000h-01FFFhRead/Reset commands or Hardware Resets until the memory is ready to enter Read mode.The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor.A Low will then indicate that one,or more,of the memories is busy.Byte/Word Organization Select (BYTE).The Byte/Word Organization Select pin is used to switch be-tween the 8-bit and 16-bit Bus modes of the mem-ory.When Byte/Word Organization Select is Low,V IL ,the memory is in 8-bit mode,when it is High,V IH ,the memory is in 16-bit mode.V CC Supply Voltage.The V CC Supply Voltage supplies the power for all operations (Read,Pro-gram,Erase etc.).The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage,V LKO .This prevents Bus Write operations from ac-cidentally damaging the data during power up,power down and power surges.If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memo-ry contents being altered will be invalid.A 0.1µF capacitor should be connected between the V CC Supply Voltage pin and the V SS Ground pin to decouple the current surges from the power supply.The PCB track widths must be sufficient to carry the currents required during program and erase operations,I CC4.Vss Ground.The V SS Ground is the reference for all voltage measurements.5/22M29F200BT,M29F200BBTable 4A.Bus Operations,BYTE =V ILNote:X =V IL or V IH .Table 4B.Bus Operations,BYTE =V IHNote:X =V IL or V IH .Operation E G W Address Inputs DQ15A–1,A0-A16Data Inputs/Outpu ts DQ14-DQ8DQ7-DQ0Bus Read V IL V IL V IH Cell Address Hi-Z Data Output Bus Write V IL V IH V IL Command Address Hi-Z Data Input Output Disable X V IH V IH X Hi-Z Hi-Z StandbyV IH X X XHi-Z Hi-Z Read Manufacturer CodeV IL V IL V IH A0=V IL ,A1=V IL ,A9=V ID ,Others V IL or V IHHi-Z 20hRead Device CodeV ILV ILV IHA0=V IH ,A1=V IL ,A9=V ID ,Others V IL or V IHHi-ZD3h (M29F200BT)D4h (M29F200BB)Operation E G W Address InputsA0-A16Data Inputs/Outpu ts DQ15A–1,DQ14-DQ0Bus Read V IL V IL V IH Cell Address Data Output Bus Write V IL V IH V IL Command Address Data Input Output Disable X V IH V IH X Hi-Z StandbyV IH X X XHi-Z Read Manufacturer CodeV IL V IL V IH A0=V IL ,A1=V IL ,A9=V ID ,Others V IL or V IH0020hRead Device CodeV ILV ILV IHA0=V IH ,A1=V IL ,A9=V ID ,Others V IL or V IH00D3h (M29F200BT)00D4h (M29F200BB)BUS OPERATIONSThere are five standard bus operations that control the device.These are Bus Read,Bus Write,Out-put Disable,Standby and Automatic Standby.See Tables 4A and 4B,Bus Operations,for a summa-ry.Typically glitches of less than 5ns on Chip En-able or Write Enable are ignored by the memory and do not affect bus operations.Bus Read.Bus Read operations read from the memory cells,or specific registers in the Com-mand Interface.A valid Bus Read operation in-volves setting the desired address on the Address Inputs,applying a Low signal,V IL ,to Chip Enable and Output Enable and keeping Write Enable High,V IH .The Data Inputs/Outputs will output the value,see Figure 7,Read Mode AC Waveforms,and Table 11,Read AC Characteristics,for details of when the output becomes valid.Bus Write.Bus Write operations write to the Command Interface.A valid Bus Write operation begins by setting the desired address on the Ad-dress Inputs.The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable,whichever occurs last.The Data Inputs/Outputs are latched by the Com-mand Interface on the rising edge of Chip Enable or Write Enable,whichever occurs first.Output En-able must remain High,V IH ,during the whole Bus Write operation.See Figures 8and 9,Write AC Waveforms,and Tables 12and 13,Write AC Characteristics,for details of the timing require-ments.Output Disable.The Data Inputs/Outputs are in the high impedance state when Output Enable is High,V IH .M29F200BT,M29F200BB6/22Standby.When Chip Enable is High,V IH ,the Data Inputs/Outputs pins are placed in the high-impedance state and the Supply Current is re-duced to the Standby level.When Chip Enable is at V IH the Supply Current is reduced to the TTL Standby Supply Current,I CC2.To further reduce the Supply Current to the CMOS Standby Supply Current,I CC3,Chip Enable should be held within V CC ±0.2V.For Standby current levels see Table 10,DC Characteristics.During program or erase operations the memory will continue to use the Program/Erase Supply Current,I CC4,for Program or Erase operations un-til the operation completes.Automatic Standby.If CMOS levels (V CC ±0.2V)are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is re-duced to the CMOS Standby Supply Current,I CC3.The Data Inputs/Outputs will still output data if a Bus Read operation is in progress.Special Bus OperationsAdditional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection.These bus opera-tions are intended for use by programming equip-ment and are not usually used in applications.They require V ID to be applied to some pins.Electronic Signature.The memory has two codes,the manufacturer code and the device code,that can be read to identify the memory.These codes can be read by applying the signals listed in Tables 4A and 4B,Bus Operations.Block Protection and Blocks Unprotection.Each block can be separately protected against acci-dental Program or Erase.Protected blocks can be unprotected to allow data to be changed.There are two methods available for protecting and unprotecting the blocks,one for use on pro-gramming equipment and the other for in-system use.For further information refer to Application Note AN1122,Applying Protection and Unprotec-tion to M29Series Flash.COMMAND INTERFACEAll Bus Write operations to the memory are inter-preted by the Command mands consist of one or more sequential Bus Write oper-ations.Failure to observe a valid sequence of Bus Write operations will result in the memory return-ing to Read mode.The long command sequences are imposed to maximize data security.The address used for the commands changes de-pending on whether the memory is in 16-bit or 8-bit mode.See either Table 5A,or 5B,depending on the configuration that is being used,for a sum-mary of the commands.Read/Reset Command.The Read/Reset com-mand returns the memory to its Read mode where it behaves like a ROM or EPROM.It also resets the errors in the Status Register.Either one or three Bus Write operations can be used to issue the Read/Reset command.If the Read/Reset command is issued during a Block Erase operation or following a Programming or Erase error then the memory will take upto 10µs to abort.During the abort period no valid data can be read from the memory.Issuing a Read/Reset command during a Block Erase operation will leave invalid data in the memory.Auto Select Command.The Auto Select com-mand is used to read the Manufacturer Code,the Device Code and the Block Protection Status.Three consecutive Bus Write operations are re-quired to issue the Auto Select command.Once the Auto Select command is issued the memory remains in Auto Select mode until another com-mand is issued.From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0=V IL and A1=V IL .The other address bits may be set to either V IL or V IH .The Manufacturer Code for STMicroelectronics is 0020h.The Device Code can be read using a Bus Read operation with A0=V IH and A1=V IL .The other address bits may be set to either V IL or V IH .The Device Code for the M29F200BT is 00D3h and for the M29F200BB is 00D4h.7/22M29F200BT,M29F200BBTable mands,16-bit mode,BYTE =V IHTable mands,8-bit mode,BYTE =V ILNote:X Don’t Care,PA Program Address,PD Program Data,BA Any address in the Block.All values in the table are in hexadecimal.The Command Interface only uses A–1,A0-A10and DQ0-DQ7to verify the commands;A11-A16,DQ8-DQ14and DQ15are Don’t Care.DQ15A–1is A–1when BYTE is V IL or DQ15when BYTE is V IH .Read/Reset.After a Read/Reset command,read the memory as normal until another command is issued.Auto Select.After an Auto Select command,read Manufacturer ID,Device ID or Block Protection Status.Program,Unlock Bypass Program,Chip Erase,Block Erase.After these commands read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.Add additional Blocks during Block Erase Command with additional Bus Writ e Operations until the Timeout Bit is set.Unlock Bypass.After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.Unlock Bypass Reset.After the Unlock Bypass Reset command read the memory as normal until another command is issued.Erase Suspend.After the Erase Suspend command read non-erasing memory blocks as normal,issue Auto Select and Program commands on non-erasing blocks as normal.Erase Resume.After the Erase Resume command the suspended Erase operation resumes,read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode.CommandL e n g t hBus Write Operations1st 2nd 3rd 4th 5th 6th Addr Data AddrDataAddrDataAddrDataAddrDataAddrDataRead/Reset 1X F03555AA 2AA 55X F0Auto Select 3555AA 2AA 5555590Program 4555AA 2AA 55555A0P APDUnlock Bypass 3555AA 2AA 5555520Unlock Bypass Program2X A0PA PD Unlock Bypass Reset 2X 90X 00Chip Erase 6555AA 2AA 5555580555AA 2AA 5555510Block Erase 6+555AA 2AA5555580555AA2AA55BA30Erase Suspend 1X B0Erase Resume1X30CommandL e n g t hBus Write Operations1st 2nd 3rd 4th 5th 6th Addr Data AddrDataAddrDataAddrDataAddrDataAddrDataRead/Reset 1X F03AAA AA 55555X F0Auto Select 3AAA AA 55555AAA 90Program 4AAA AA 55555AAA A0P APDUnlock Bypass 3AAA AA 55555AAA20Unlock Bypass Program2X A0PA PD Unlock Bypass Reset 2X 90X 00Chip Erase 6AAA AA 55555AAA 80AAA AA 55555AAA 10Block Erase 6+AAA AA 55555AAA80AAAAA55555BA30Erase Suspend 1X B0Erase Resume1X30M29F200BT,M29F200BB8/22The Block Protection Status of each block can be read using a Bus Read operation with A0=V IL ,A1=V IH ,and A12-A16specifying the address of the block.The other address bits may be set to ei-ther V IL or V IH .If the addressed block is protect-ed then 01h is output on Data Inputs/Outputs DQ0-DQ7,otherwise 00h is output.Program Command.The Program command can be used to program a value to one address in the memory array at a time.The command re-quires four Bus Write operations,the final write op-eration latches the address and data in the internal state machine and starts the Program/Erase Con-troller.If the address falls in a protected block then the Program command is ignored,the data remains unchanged.The Status Register is never read and no error condition is given.During the program operation the memory will ig-nore all commands.It is not possible to issue any command to abort or pause the operation.Typical program times are given in Table 6.Bus Read op-erations during the program operation will output the Status Register on the Data Inputs/Outputs.See the section on the Status Register for more details.After the program operation has completed the memory will return to the Read mode,unless an error has occurred.When an error occurs the memory will continue to output the Status Regis-ter.A Read/Reset command must be issued to re-set the error condition and return to Read mode.Note that the Program command cannot change a bit set at ’0’back to ’1’and attempting to do so will cause an error.One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’to ’1’.Unlock Bypass Command.The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memo-ry.When the access time to the device is long (as with some EPROM programmers)considerable time saving can be made by using these com-mands.Three Bus Write operations are required to issue the Unlock Bypass command.Once the Unlock Bypass command has been is-sued the memory will only accept the Unlock By-pass Program command and the Unlock Bypass Reset command.The memory can be read as if in Read mode.Unlock Bypass Program Command.The Un-lock Bypass Program command can be used to program one address in memory at a time.The command requires two Bus Write operations,the final write operation latches the address and data in the internal state machine and starts the Pro-gram/Erase Controller.The Program operation using the Unlock Bypass Program command behaves identically to the Pro-gram operation using the Program command.A protected block cannot be programmed;the oper-ation cannot be aborted and the Status Register is read.Errors must be reset using the Read/Reset command,which leaves the device in Unlock By-pass Mode.See the Program command for details on the behavior.Table 6.Program,Erase Times and Program,Erase Endurance Cycles (T A =0to 70°C,–40to 85°C or –40to 125°C)Note: 1.T A =25°C,V CC =5V.ParameterMinTyp (1)Typical after 100k W/E Cycles (1)Max Unit Chip Erase (All bits in the memory set to ‘0’)0.80.8secChip Erase2.5 2.510sec Block Erase (64Kbytes)0.60.64sec Program (Byte or Word)88150µs Chip Program (Byte by Byte) 2.3 2.39sec Chip Program (Word by Word) 1.21.24.5sec Program/Erase Cycles (per Block)100,000cyclesM29F200BT,M29F200BBUnlock Bypass Reset Command.The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command.Chip Erase Command.The Chip Erase com-mand can be used to erase the entire chip.Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller.If any blocks are protected then these are ignored and all the other blocks are erased.If all of the blocks are protected the Chip Erase operation ap-pears to start but will terminate within about100µs, leaving the data unchanged.No error condition is given when protected blocks are ignored.During the erase operation the memory will ignore all commands.It is not possible to issue any com-mand to abort the operation.Typical chip erase times are given in Table6.All Bus Read opera-tions during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.After the Chip Erase operation has completed the memory will return to the Read Mode,unless an error has occurred.When an error occurs the memory will continue to output the Status Regis-ter.A Read/Reset command must be issued to re-set the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in un-protected blocks of the memory to’1’.All previous data is lost.Block Erase Command.The Block Erase com-mand can be used to erase a list of one or more blocks.Six Bus Write operations are required to select the first block in the list.Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block.The Block Erase operation starts the Program/Erase Controller about50µs after the last Bus Write operation.Once the Program/Erase Controller starts it is not possible to select any more blocks.Each additional block must therefore be selected within50µs of the last block.The50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation.See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased.If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about100µs,leaving the data un-changed.No error condition is given when protect-ed blocks are ignored.During the Block Erase operation the memory will ignore all commands except the Erase Suspend and Read/Reset commands.Typical block erase times are given in Table6.All Bus Read opera-tions during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the Status Register for more details.After the Block Erase operation has completed the memory will return to the Read Mode,unless an error has occurred.When an error occurs the memory will continue to output the Status Regis-ter.A Read/Reset command must be issued to re-set the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to’1’.All previous data in the selected blocks is lost.Erase Suspend Command.The Erase Suspend Command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode.The command requires one Bus Write operation.The Program/Erase Controller will suspend within 15µs of the Erase Suspend Command being is-sued.Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended.If the Erase Suspend command is issued during the period when the memory is waiting for an additional block(before the Program/Erase Controller starts)then the Erase is suspended immediately and will start im-mediately when the Erase Resume Command is issued.It will not be possible to select any further blocks for erasure after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks.Reading from blocks that are being erased will output the Status Register.It is also possible to enter the Auto Select mode:the memory will behave as in the Auto Select mode on all blocks until a Read/Reset command returns the memory to Erase Suspend mode.Erase Resume Command.The Erase Resume command must be used to restart the Program/ Erase Controller from Erase Suspend.An erase can be suspended and resumed more than once.9/22M29F200BT,M29F200BB10/22STATUS REGISTERBus Read operations from any address always read the Status Register during Program and Erase operations.It is also read during Erase Sus-pend when an address within a block being erased is accessed.The bits in the Status Register are summarized in Table 7,Status Register Bits.Data Polling Bit (DQ7).The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its opera-tion or if it has responded to an Erase Suspend.The Data Polling Bit is output on DQ7when the Status Register is read.During Program operations the Data Polling Bit outputs the complement of the bit being pro-grammed to DQ7.After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the ad-dress just programmed output DQ7,not its com-plement.During Erase operations the Data Polling Bit out-puts ’0’,the complement of the erased state of DQ7.After successful completion of the Erase op-eration the memory returns to Read Mode.In Erase Suspend mode the Data Polling Bit will output a ’1’during a Bus Read operation within a block being erased.The Data Polling Bit will change from a ’0’to a ’1’when the Program/Erase Controller has suspended the Erase operation.Figure 3,Data Polling Flowchart,gives an exam-ple of how to use the Data Polling Bit.A Valid Ad-dress is the address being programmed or an address within the block being erased.Toggle Bit (DQ6).The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has re-sponded to an Erase Suspend.The Toggle Bit is output on DQ6when the Status Register is read.During Program and Erase operations the Toggle Bit changes from ’0’to ’1’to ’0’,etc.,with succes-sive Bus Read operations at any address.After successful completion of the operation the memo-ry returns to Read mode.During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased.The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation.Figure 4,Data Toggle Flowchart,gives an exam-ple of how to use the Data Toggle Bit.Error Bit (DQ5).The Error Bit can be used to identify errors detected by the Program/Erase Controller.The Error Bit is set to ’1’when a Pro-gram,Block Erase or Chip Erase operation fails to write the correct data to the memory.If the Error Bit is set a Read/Reset command must be issued before other commands are issued.The Error bit is output on DQ5when the Status Register is read.Note that the Program command cannot change a bit set at ’0’back to ’1’and attempting to do so will cause an error.One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’to ’1’.Table 7.Status Register BitsNote:Unspecified data bits should be ignored.Operation Address DQ7DQ6DQ5DQ3DQ2RB ProgramAny Address DQ7Toggle 0––0Program During Erase Suspend Any Address DQ7Toggle 0––0Program Error Any Address DQ7Toggle 1––0Chip Erase Any Address 0Toggle 01Toggle 0Block Erase before timeout Erasing Block 0Toggle 00Toggle 0Non-Erasing Block 0Toggle 00No Toggle 0Block EraseErasing Block 0Toggle 01Toggle 0Non-Erasing Block 0Toggle 01No Toggle 0Erase SuspendErasing Block 1No Toggle1Toggle1Non-Erasing Block Data read as normal 1Erase ErrorGood Block Address 0Toggle 11No Toggle 0Faulty Block Address0Toggle11Toggle。
