锁相环常见问题解答(新)(ADI)

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锁相环实验报告引言在电子、通信和控制系统中，锁相环（Phase-Locked Loop，PLL）是一种广泛应用的反馈控制系统，用于提供稳定的频率和相位锁定。

本实验旨在探究锁相环的原理、结构和性能，并通过实际实验验证其工作原理。

锁相环原理锁相环是一种负反馈控制系统，通常由相频控振荡器（VCO）、相锁环比较器、波形整形电路和滤波器组成。

其基本原理是：通过不断调节VCO的频率，使其输出信号与参考信号的相位差保持在一个稳定的工作范围内。

实验目的1.了解锁相环的基本原理和结构；2.学习锁相环在频率和相位锁定中的应用；3.通过实际实验验证锁相环的工作原理。

实验器材1.锁相环实验台；2.函数信号发生器；3.示波器；4.电压表；5.连接线等。

实验步骤搭建实验平台1.将锁相环实验台与函数信号发生器、示波器和电压表连接；2.正确接入电源，打开锁相环实验台的电源开关； 3.确认各仪器仪表的正常工作。

设置参考信号1.使用函数信号发生器产生一个正弦波信号作为参考信号；2.设置参考信号的频率和幅度。

调节锁相环参数1.调节锁相环的增益参数，观察VCO输出信号的变化；2.尝试不同的锁相环参数组合，观察系统的稳定性和响应性。

改变输入信号1.改变函数信号发生器输出信号的频率；2.观察锁相环的相位锁定和频率锁定过程。

测量锁相环性能1.使用示波器观察锁相环输入信号、输出信号和参考信号的波形；2.使用电压表测量VCO输出信号的频率。

实验结果与分析通过实验我们可以观察到锁相环的工作原理和性能。

在不同的锁相环参数设置下，VCO输出信号的频率和相位与参考信号的变化情况不同。

根据实验数据，我们可以分析锁相环的稳定性、响应速度和抗干扰能力等性能。

结论锁相环是一种广泛应用于电子、通信和控制系统中的反馈控制系统。

通过本实验，我们深入了解了锁相环的原理和结构，并通过实际实验验证了其工作原理。

锁相环具有稳定的频率和相位锁定能力，可以在信号处理和调节控制中起到重要作用。

ADI的最新收发器产品ADRV9009实现杂散去相关的收发器功能在大型数字波束合成天线中，我们非常希望通过组合来自分布式波形发生器和接收器的信号这一波束合成过程改善动态范围。

如果关联误差项不相关，则可以在噪声和杂散性能方面使动态范围提升10logN。

这里的N是波形发生器或接收器通道的数量。

噪声在本质上是一个非常随机的过程，因此非常适合跟踪相关和不相关的噪声源。

然而，杂散信号的存在增加了强制杂散去相关的难度。

因此，可以强制杂散信号去相关的任何设计方法对相控阵系统架构都是有价值的。

在本文中，我们将回顾以前发布的技术，这些技术通过偏移LO 频率并以数字方式补偿此偏移，强制杂散信号去相关。

然后，我们展示ADI 的最新收发器产品 ADRV9009，说明其集成的特性如何实现这一功能。

最后，我们以测量数据结束全文，证明这种技术的效果。

已知杂散去相关方法在相控阵中，用于强制杂散去相关的各种方法问世已有些时日。

已知的第一份文献可以追溯到2002年，该文描述了用于确保接收器杂散不相关的一种通用方法。

在这种方法中，先以已知方式，，修改从接收器到接收器的信号。

然后，接收器的非线性分量使信号失真。

在接收器输出端，将刚才在接收器中引入的修改反转。

目标信号变得相干或相关，但不会恢复失真项。

在测试中实现的修改方法是将每个本振(LO)频率合成器设置为不同的频率，然后在数字处理过程中以数字方式调谐数控振荡器(NCO)，以校正修改。

实现杂散去相关的收发器功能图1所示为ADI公司收发器ADRV9009的功能框图。

每个波形发生器或接收器都是用直接变频架构实现的。

LO频率可以独立编程到各IC上。

数字处理部分包括数字上/下变频，其NCO也可跨IC独立编程。

图1. ADRV9009功能框图。

ADAM-4520 常见问题解答
1、Q：为什么要单独供电？LED工作情况？隔离是什么含义？为什么称为“透明”模块？
A：ADAM-4520的负载能力为50ohm，独立供电，驱动能力增强，电源要求：+10~+30V直流，额定功耗：+24V下为1.2W。

LED在下位设备RS-485通讯时，上电常亮绿，通讯时红绿交替闪烁；若是RS-422通讯，上电不亮，通讯时红绿闪烁。

隔离指光电隔离保护，隔离保护电压为直流3000V。

该模块称为“透明”模块可以理解为不可寻址，不需要配置软件，RS-232与RS-422/485可以互相转换。

2、Q：为什么不能和下位设备通讯？通讯时，怎么会出现乱码？
A：若是出现此问题，通常是通讯格式不匹配。

通讯涉及：波特率（拨码开关SW2选择），数据格式（拨码开关SW1选择）如起始位、数据位、停止位、校验位等，默认设置：波特率为9600（SW2的IP5拨到ON）；数据格式为1，8，1，无校验，即总共10位（SW1的IP1拨到ON，IP2拨到OFF）。

3、Q：RS-232/RS-422/RS-485怎么接线？
A：输入端与上位机直连的RS-232为4线制，DB-9的针脚定义分别是：2（TXD）、3（RXD）、5（GND）、7（RTS）；
输出端与下位设备连接，可以是RS-422或RS-485通讯。

若是RS-422通讯，采用4线制，为TX+、TX-、RX+、RX-，分别与下位设备的RX+、RX-、TX+、TX-相连。

若是RS-485通讯，采用2线制，为DATA+、DATA-，与下位设备DATA+（A）、DATA-（B）一一对应。

锁相环实验报告锁相环实验报告引言：锁相环（Phase-Locked Loop，简称PLL）是一种常见的电子系统控制技术，广泛应用于通信、测量、信号处理等领域。

本实验旨在通过设计和搭建一个基本的锁相环电路，深入理解锁相环的原理和应用。

一、实验目的本实验的主要目的是通过搭建锁相环电路，实现对输入信号的频率、相位的跟踪和稳定。

具体目标包括：1. 理解锁相环的基本原理和工作方式；2. 学会设计和搭建基本的锁相环电路；3. 通过实验验证锁相环的频率和相位跟踪性能。

二、实验原理1. 锁相环的基本原理锁相环是一种反馈控制系统，由相位比较器、低通滤波器、电压控制振荡器（Voltage Controlled Oscillator，简称VCO）和分频器组成。

其基本原理如下：（1）相位比较器：将输入信号和VCO输出信号进行相位比较，输出相位误差信号；（2）低通滤波器：对相位误差信号进行滤波，得到控制量；（3）VCO：根据控制量调整输出频率，使其与输入信号保持相位同步；（4）分频器：将VCO输出信号分频后反馈给相位比较器，形成闭环控制。

2. 锁相环的应用锁相环广泛应用于频率合成、时钟恢复、频率/相位调制解调等领域。

例如，在通信系统中，锁相环常用于时钟恢复电路，保证数据传输的稳定性和可靠性。

三、实验内容与步骤1. 实验器材与元件准备（1）信号发生器：产生待测频率的正弦信号；（2）锁相环芯片：如CD4046、PLL565等；（3）电阻、电容等元件：用于搭建锁相环电路；（4）示波器：用于观测和分析实验结果。

2. 搭建锁相环电路根据锁相环的基本原理和实验要求，设计和搭建一个简单的锁相环电路。

电路中包括相位比较器、低通滤波器、VCO和分频器等模块，并连接好电源和地线。

3. 实验操作步骤（1）将信号发生器的输出信号接入锁相环电路的输入端；（2）调节信号发生器的频率，观察锁相环的跟踪效果；（3）通过示波器观察锁相环输出信号的频率和相位稳定性。

AD9361 学习记录一、简介AD9361 是 ADI 推出的面向 3G 和 4G 基站应用的高性能、高集成度的射频解决方案。

该器件集 RF 前端与灵便的混杂信号基带部分为一体，集成频率合成器，为办理器供应可配置数字接口。

AD9361 接收器 LO 工作频率范围为70 MHz 至 6.0 GHz，发射器 LO 工作频率范围为 47 MHz 至 6.0 GHz，涵盖大部分特许执照和免执照频段，支持的通道带宽范围为 200 kHz 以下至 56 MHz。

两个独立的直接变频接收器拥有鹤立鸡群的噪声系数和线性度。

每个接收 (RX) 子系统都拥有独立的自动增益控制 (AGC)、直流失调校正、正交校正和数字滤波功能，从而除掉了在数字基带中供应这些功能的必要性。

The AD9361 还拥有灵便的手动增益模式，支持外面控制。

每个通道搭载两个高动向范围模数变换器 (ADC)，先将收到的 I 信号和 Q 信号进行数字化办理，尔后将其传过可配置抽取滤波器和 128 抽头有限脉冲响应 (FIR)滤波器，结果以相应的采样率生成 12 位输出信号。

发射器采用直接变频架构，可实现较高的调制精度和超低的噪声。

这种发射器设计带来了行业最正确的 TX误差矢量幅度 (EVM)，数值不到 - 40 dB，可为外面功率放大器(PA)的选择留出可观的系统裕量。

板载发射(TX)功率监控器可以用作功率检测器，从而实现高度精确的 TX 功率测量。

N 分频频完好集成的锁相环 (PLL)可针对所有接收和发射通道供应低功耗的小数率合成。

设计中集成了频分双工 (FDD)系统需要的通道隔断。

二、 AD9361 系统构成AD9361 的框架以以下图2-1 所示：图 2-1它支持 2x2 MIMO 通信，收发各有两条独立的射频通路。

TX 射频前端构成以以下图2-2 所示：ATTNTXRF OUTPUTSecondary TX Filter DAC INPUTFilterPhaseSpiltter图 2-2TX 数据通路以以下图2-3 所示：图 2-3RX射频前端构成以以下图2-4 所示：RF INPUT TIA RX Filter ADC OUTPUT LNAPhaseSpiltter图 2-4RX数据通路以以下图2-5 所示：图 2-5三、初始化及校准总述AD9361 在上电此后便会进入休眠状态。

Xilinx中DCM的问题解决方案引言概述：
Xilinx中的数字时钟管理（DCM）模块是用于时钟生成和时钟分频的重要组件。

然而，在实际应用中，DCM模块可能会遇到一些问题，如时钟抖动、时钟漂移等。

本文将针对Xilinx中DCM模块常见的问题提出解决方案，以帮助工程师更好地应
对这些挑战。

一、时钟抖动问题解决方案：
1.1 调整DCM的时钟输入端口的时钟源。

1.2 调整DCM的锁定时间。

1.3 使用PLL锁相环模块来代替DCM模块。

二、时钟漂移问题解决方案：
2.1 调整DCM的时钟输出频率。

2.2 调整DCM的相位偏移。

2.3 使用外部时钟源来代替DCM内部时钟源。

三、时钟信号失真问题解决方案：
3.1 调整DCM的时钟延迟。

3.2 使用低抖动的时钟源。

3.3 使用时钟数据恢复技术来减小时钟信号失真。

四、时钟频率不稳定问题解决方案：
4.1 调整DCM的时钟输入端口的时钟源。

4.2 使用更高精度的时钟源。

4.3 调整DCM的锁定时间和时钟延迟参数。

五、时钟相位偏移问题解决方案：
5.1 调整DCM的相位偏移参数。

5.2 使用外部相位校准电路。

5.3 使用PLL模块来代替DCM模块进行时钟相位调整。

结论：
通过本文提出的解决方案，工程师们可以更好地解决Xilinx中DCM模块可能遇到的问题，确保时钟信号的稳定性和精确性。

同时，建议在实际设计中，根据具体情况选择合适的解决方案，以提高系统的性能和可靠性。

AD9361RF and BB PLL SynthesizerUser GuideRev 2.4.Information furnished by Analog Devic es is believed to be ac c urate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Tec hnology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.GENERAL DESCRIPTIONThe AD9361 transceiver contains two identical RFPLL synthesizers to generate the required LO signals. One is programmed for the RX channel and the other for the TX channel. The transceiver also contains a BBPLL synthesizer to generate the required sampling and internal operational clocks. The PLL synthesizers are all of fractional–N architecture with completely integrated VCOs and loop filters. They require no external parts to cover the entire frequency range of the device. This configuration allows the use of any convenient reference frequency for operation on any channel with any sample rate. For FDD operation, the frequency of TX and RX can be different and both RFPLL synthesizers operate simultaneously. For TDD operation, the RFPLL synthesizers alternately turn on as appropriate for RX and TX frames.REVISION HISTORY3/11—1.0 Distribution4/11—1.1 Edit formatting add table. Applies to R1 version.6/11—2.0 Update fixed writes for R2. Add Fast Lock info, Ext LO.9/11—2.1 Include FDD and TDD tables for R2. Add BBPLL section. Examples updated.10/11—2.2 Fixed typos.11/11—2.3 Clarified BBPLL loop filter table value usage1/12—2.4 Added how to generate TDD script with FDD calibrations to TDD MODE – Faster Lock Times section.General Description (2)Revision History (2)RFPLL Introduction (4)AD9361 PLL Architecture (5)Reference Block (including Reference Scalers) (5)DCXO (6)Main PLL Block (6)VCO Divider Block (7)Calculating RFPLL Divider Values (7)Carrier Frequency setup (7)RX (or TX) VCO Divider (7)Charge Pump Current (9)RFPLL Loop Filter (10)VCO Configuration (10)Lock Detector (11)Synthesizer Look Up Table (11)Example Programming Sequence (26)TDD MODE – Faster Lock Times (28)Frequency Correction Words (29)FastLock Mode (30)FastLock Initial Wider-BW Option (30)Configuring and Using a Fast Lock Profile – Internal Registers (31)Configuring and Using a Fast Lock Profile – EXAMPLE (34)External LO (37)Baseband PLL (BBPLL) (39)BBPLL VCO (39)Calculating BBPLL Divider Values (40)BB PLL Charge Pump (41)BBPLL Loop Filter Values (41)BBPLL Typical Loop Filter and Charge Pump Configuration (44)APPENDIX: RFPLL Loop Filter (45)The AD9361 contains two identical RFPLL Synthesizers, one for RX and the other for TX, which are programmed independently. The two VCOs and loop filters are integrated on chip and have no external components. The fundamental frequency of the PLLs is from 6-12GHz. Local Oscillator frequencies ranging from 47MHz to 6GHz are created by dividing the PLL frequency.There are 6 areas of each PLL that will be configured for a given frequency of operation. These are:• Reference Scaler• PLL divider (N INT and N FRAC ) (register bits) • VCO divider (register bits) • Charge Pump (register bits)• Loop Filter components (register bits) • VCO tuning (self-calibration procedure)TX2A TX1A RADIOTX2BTX1B SPI PortJESD207/LVDS JESD207/LVDSFigure 1. AD9361 Block Diagram. RX and TX synthesizers operate independently.The synthesizers have identical but independent register sets in the device address space. Each synthesizer must be configured and calibrated separately.ADI provides Lookup Tables for synthesizer configuration based upon the desired reference frequency to be used. Each lookup table covers a specific reference clock input frequency and application (FDD or TDD). A particular lookup table is indexed by the VCO frequency. At that index, the configuration data in the table cells is retrieved, then it is formatted and stored into the appropriate registers. At power up, a few registers are programmed that will typically remain the same during normal operation. At this point, aparticular table is referenced to configure the VCO and loop filter settings for best performance over temperature. The tables provided by ADI include a column of VCO gains for different frequency settings so that users can customize their own loop filter if desired.The following sections show block diagrams of the AD9361 PLL that consist of the Reference Block, the main PLL Block, and the LO GEN Output Block. The VCO always operates between 6 to 12 GHz. Highlighted text indicates programmable items.REFERENCE BLOCK (including Reference Scalers)The reference frequency can be generated via the on-chip DCXO or an external clock source can provide this input to the device. If an external source is used, a 1.3Vpp clipped sinewave would be applied to the device XTAL_N input (with XTAL_P input OPEN). A MUX selects the desired source. The reference is then split and applied to 3 independent conditioning blocks also known as scalers (or Ref Dividers in the Register Map). The conditioning blocks provide 4 options such that the PLL reference frequency F REF (the loop reference applied to the PLL phase detector) is either buffered, doubled, halved, or divided by 4. Independent blocks make it possible to have a different F REF for each PLL if desired. For best RFPLL performance, ADI recommends selecting the reference scaler that will result in a reference frequency as high as possible with the result between 35MHz and 80 MHz after scaling. Also, the same scaler configuration should be used for both RX and TX PLLs so that the noise spectrums match. The same block functionality is provided for the BBPLL (see BBPLL section). For best BBPLL performance, the reference scaler would be configured to result in reference frequencies between 35 and 70MHz. See Table 1 for configuration information.Figure 2. Independent Reference Block for each PLL applies either Buffered, 2X, ½X, or ¼X Reference FrequencyFor best performance, Valid F REF for TX and RX is 35-80MHz NOTE: Apply External Reference to the XTAL_N pin (XTAL_P OPEN ) (DO NOT APPLY TO REF_CLK_IN pin). See DCXO document.Table 1 Reference Block Scaler ConfigurationREF _ C LK _I N DO NOT USEF R EFF R EF 80 M HzF R EF 80 M Hz FOR BEST PERFORMANCE: 35-70 MHzFOR BEST PERFORMANCE: 35-80MHzCONNECT H6 TO GROUNDThe DCXO on the AD9361 consists of a coarse cap DAC, a fine cap DAC and maintaining amplifier. Figure 3 shows a simplifiedschematic. The resistors, R D and R TAIL , in the maintaining amplifier are programmable for bias current adjustment. Sufficient flexibility has been incorporated for crystals with nominal 10pF load capacitance and less than 60Ω equivalent series resistance. See the DCXO document for details and configuration settings.Figure 3. Simplified DCXO schematic.MAIN PLL BLOCKThe independent RX and TX PLLs use fractional–N techniques to achieve the channel synthesis. The entire PLL is integrated on-chip, including the VCO and the loop filter. The PLL always operates over the range of 6-12GHz. The charge pump current is programmable as are all of the loop filter components allowing optimization of performance parameters for almost any application.Configuration for a given frequency consists of a combination of calculating the required divider values and referring to an ADI supplied lookup table to configure the VCO for stable performance over temperature. The lookup table also provides example loop filter parameters. This will be explained in the following sections.Figure 4. PLL Synthesizer Block Diagram. RX and TX Synthesizers are identical.R DDN INT 11 bits (range 75-1200)N FRAC 23 bitsThe Main PLL output is divided by the VCO Divider Block to create the frequency bands that allow the device to operate continuously from 47MHz to 6GHz. Figure 5 shows how the bands are created.Figure 5. VCO Divider.CALCULATING RFPLL DIVIDER VALUESThe modulus of the RFPLL is 8388593, resulting in frequency resolution of (Fref/Modulus/VCO divider).CARRIER FREQUENCY SETUPThe RX and TX synthesizers have independent register sets. The RX synthesizer register set is used below to illustrate the configuration process. The first step in determining the programming words is to determine the correct VCO output divider value for the desiredoperating frequency. Once the divider has been determined, the RFPLL (VCO) frequency is known, so the integer and fractional divider words can then be determined. In the following example, the reference frequency is 30.72MHz (either DCXO, or a 30.72MHz external reference). The reference scaler is configured to 2X so that the PLL Reference Frequency will be 61.44MHz.RX (OR TX) VCO DIVIDERThe RFPLL runs at frequencies between 6GHz and 12GHz, so the output divider is programmed to bring the PLL output down to the desired operating frequency. The local oscillator (LO) frequency, or the RX (or TX) carrier frequency, equals the RFPLL divided down by the appropriate power-of-two divider. Rearranged, it appears as shown in the equation below.RRFFRRRRRR (VVVVLL DDDD DD DD DD DDDD +1) Equation 1The “VCO Divider” is programmed in register 0x005.Table 2 VCO Divider Selection47 MHz to 6 GHz- 6 G H z.5 - 3 G H z50 M H z – 1.5 G H z75 - 750 M H z3.75 – 187.5 M H z87.5 - 375 M H z6.875 - 93.75 M H z VCO InputThis byte is the lower 8 bits of the synthesizer integer word. As mentioned above, the RFPLL frequency is always between 6-12GHz. It is defined by programming the fractional and integer words as well as the reference frequency (set by an external reference or by the internal DCXO).FF RRFFRRRRRR=FF RRRRFF∗�NN II II II DD IIDDDD+ NN FFDDFFFFII DD FF IIFFFF� Equation 2WhereF REF = Reference Clock Frequency (output of Ref Divider block)N Integer = 11-bit Integer word programmed in registers 0x231 and 0x232N Fractional = 23-bit Fractional word programmed in registers 0x233 through 0x235The integer and fractional words are calculated according to the following equations.NN II II II DD IIDDDD=FFFF FF FFDD�FF RRFFRRRRRR FF RRRRFF� Equation 3NN FFDDFFFFII DD FF IIFFFF=RRFFRRIIDD�8,388,593∗�FF RRFFRRRR RR FF RRRRFF−NN II II II DD IIDDDD��Equation 4The following table shows a typical process for determining the integer and fractional word, using an example.RX Operation Frequency: 902.2 MHzDevice Reference Frequency: 30.72 MHzReference Block Scaling: 2xPLL Fref: 61.44MHzTable 3 Programming RX Synthesizer Frequency WordsNOTE: The integer word is 11bits and spans 2 registers. The integer words in registers 0x231 and 0x271 should be written last because writing to these registers triggers the VCO calibration. Refer to the Initialization and Calibration Guide for further information.The charge pump current is 6-bit programmable and varies from 0.1mA to 6.4mA with 0.1mA steps. Charge pump current is programmed into register 0x23B for the RX synthesizer and 0x27B for the TX synthesizer.•Bits [5:0] Set the charge pump output current. 000000=0.1mA, 000011=0.4mA & 111111=6.4mA (64×0.1A)Figure 6. Charge PumpCharge Pump CalibrationThe charge pump calibration must be run once during chip initialization to match the up and down currents. Refer to the Initialization and Calibration Guide available from ADI for typical charge pump calibration procedure details. Below is a summary of the procedure with control word explanations.Writing Cp Cal Enable (register 0x23D[2] for RX, or 0x27D[2] for TX) to 1 starts the charge pump cal. The CP cal takes 64 reference clock cycles. Note: during initialization, calibration of both RX and TX charge pumps is easily accomplished by setting Dual Synth Mode bit (reg 0x015[2]) to 1, then writing the Cp Cal Enable bit for Rx and Tx.SPIWrite 015,0C // Set Dual Synth mode bit SPIWrite 014,15 // Set Force ALERT State bit SPIWrite 013,01 // Set ENSM FDD mode W AIT 1 // waits 1 ms SPIWrite 23D,04 // Start RX CP cal W AIT_CALDONE RXCP ,100 // Wait for CP cal to complete (Done when 0x244[7]==1) SPIWrite 27D,04 // Start TX CP cal W AIT_CALDONE TXCP ,100 // Wait for CP cal to complete (Done when 0x284[7]==1)If operating in FDD mode, skip the next instruction. If operating in TDD mode, clear the Dual Synth mode bit (0x015[2]). SPIWrite 015,08 // reset Dual Synth mode bitValid CalibrationA single charge pump calibration is performed at power-up will be valid for device operation over all rated conditions. After the cal is completed, the following bits will go high:CP Cal Valid , register 0x244[7] for RX or 0x284[7] for TX, is automatically set after successful CP Cal and the results are stored. This bit does not clear after the synthesizer has been powered down (the synthesizer powers up and down during TDD operation). When set, it indicates that it is not necessary to re-calibrate the charge pump after the synthesizer has been powered down and powered back up. Cp Cal Done register 0x244[5] for RX or 0x284[5] for TX. This bit will clear after synthesizer has been powered down.ChargePump0.1-6.4mA12.5 uA stepsThe loop filter is fully integrated on-chip and is a standard passive Type II 3rd order filter. Example loop filter values are included in the ADI provided synthesizer configuration tables (See the Synthesizer Look Up Table section) that typically result in excellent performance. It is possible to reconfigure the loop filter to tailor synthesizer performance either by substituting new values into the lookup table or by simply writing new values directly to the loop filter registers. See the Appendix: RFPLL Loop Filter section for more information. VCO CONFIGURATIONVCO configuration consists of writing a few static temperature compensation registers versus frequency from an ADI provided lookup table and then enabling an automatic calibration procedure to configure the VCO control voltage Vtune sufficiently away from both supply rails. The VCO calibration is triggered in one of three ways: when going from Wait State to Alert State, when going from the synthesizer powerdown state to the Alert State (TDD), or writing the LSBs of the frequency INTEGER word (RX register 0x231 and/or TX register 0x271). All VCO, Loopfilter, and other synthesizer settings should be written into the chip before triggering the VCO calibration. Note that charge pump calibration should be completed before a VCO calibration is started.When in TDD mode using hardware control (VS SPI control) and the device state machine is in the ALERT state, the synthesizers power up and down with the state of the TXNRX control line. A typical sequence for TDD operation is RX-ALERT-TX-ALERT-RX etc. The BB controller sets the level of the TXNRX line in ALERT to steer the device into the correct next state. Then state machine advances to the next state with the following ENABLE edge. During ALERT, as the BB controller changes the level of TXNRX from LOW to HIGH, the RX synthesizer turns off, the TX synthesizer will turn on, and a TX VCO calibration will be triggered. Similarly during a following cycle, as the BB controller changes the state of TXNRX from HIGH to LOW, the TX synthesizer turns off, the RX synthesizer will turn on, and a RX VCO calibration will be triggered. Operationally, the BB processor should transition the TXNRX line shortly after entering the Alert mode so that the synthesizer has as much of the time as possible between frames to calibrate and lock. Typical ‘normal’ TDD calibration plus lock times are on the order of 45-60us. For faster lock times, refer to the TDD MODE – FASTER LOCK TIMES section or the FASTLOCK MODE section of this document.VCO CalibrationThe time the calibration takes to complete is programmable. Usually a fast calibration is appropriate for TDD systems, and a slow calibration is appropriate for FDD. For TDD, the synthesizer will only be on for a short time, so the danger that temperature drift would cause it to lose lock is very small. For FDD, the synthesizer could potentially be locked indefinitely, so a longer more accurate calibration is called for to ensure that Vtune is sufficiently centered. Example calibration times are shown in the Initialization and Calibration Guide available from ADI.The device includes a Fast Lock mode that makes it possible to achieve faster than normal frequency changes by storing all synthesizer programming information, including the VCO cal result of this section, into either device registers or the BB processor memory space to be recalled at a later time. Please see the Fast Lock section later in the document for usage details.VCO Vtune MeasurementFor debug purposes the Vtune voltage can be output to a package pin. The Vtune voltage is MUXed with the corresponding (RX or TX) External_LO_IN pin. This is configured by setting Vtune Force bit 0x23B[6] (RX) or 0x27B[6] (TX). For normal operation, these bits should be cleared.A lock detector bit is provided to indicate that the corresponding synthesizer has achieved lock in the configured number of clock cycles (RX register 0x247[1], TX register 0x287[1]).The lock detector is configured by setting the mode and count values (RX register 0x24A, TX register 0x28A)[D3:D2] Lock Detect Count[1:0] These bits set the maximum time allowed for the RFPLL to lock. If it locks within the specified time, the “Lock” bit (0x247[D1]) goes high. The time is measured in reference clock cycles per Table 4 Lock Detect Count .Table 4 Lock Detect Count[D1:D0] Lock Detect Mode[1:0] These bits set the lock detect mode of operation per Table 5.Table 5 RFPLL Lock Detect ModeSYNTHESIZER LOOK UP TABLETwo sets of tables for 3 different RFPLL loop reference frequencies are provided below, one set for FDD operation and the other for TDD operation. The FDD tables enable the VCO temperature compensation with the intent that the user will use longer, more accurate calibration times for the device to remain in operation indefinitely. In the TDD tables, the temperature compensation is not enabled, because it is assumed that the VCO will be calibrated between TX and RX frames every few mS, which is insignificant compared to the temperature drift time constant. Note the VCO temperature compensation is completely independent from, and is not shared or slaved with the DCXO temperature compensation in any way.Tables are provided for 40MHz, 60MHz, and 80MHz reference frequencies. The correct table to use is the one that closest matches the loop F REF for the operating mode. For example, 19.2MHz is a popular reference frequency which could be the device reference frequency applied to the XTAL_N pin. Because the best RFPLL performance is had with the highest possible loop reference frequency up to80MHz, the RFPLL Reference Blocks would be configured to the X2 mode, resulting in F REF of 38.4MHz. In this case, the 40MHz reference table would be selected. Refer to Table 6 for other reference frequencies.Table 6 Lookup Table ReferenceTable 7 - Table 12 display the synthesizer tables. Loop Filter table entries are dependent on reference frequency. The setup parameters pre-configure the VCO for operation based on frequency of operation. In TDD, temperature compensation is not used since the synthesizer will only be operational during a frame for a few milliseconds at a time. In FDD temperature compensation is enabled allowing VCO calibration at any temperature (including either of the extremes) and the synthesizer will stay locked over the rated temperature range.To use the table, the RFPLL (Fvco) frequency is used to access the data in the corresponding row (refer to Equation 1). For a given row, Fvco represents the lower frequency boundary for the row data (use data in the row when VCO frequency is equal to or greater than the frequency in the current row, but below the VCO frequency in the row above). For example, if the operating frequency is 800MHz, then Fvco=6400MHz according to Equation 1. For this frequency, data from row index 45 is used. The columns marked band, fref, loop bw, index and kv are informational to allow for readability. The other columns contain data that is retrieved, formatted by the user and then written into the device. Above the table, the upper column labels show the appropriate registers and bit positions for both RX and TX synthesizers in the format of Register Address (in HEX) followed by the bit positions (from bit7 to bit0).Specific to this section, the VCO parameters are in the columns with ‘vco’ in the heading. The last 6 columns are for setting the charge pump current and loop filter for a specific configuration. The VCO parameters as provided by ADI should be pulled from the table and written into the device in the registers/positions indicated without modification. However the user can change charge pump and loop filter parameters to suit the particular application if desired.Fixed register writesBelow, the values shown do not change once the device has been configured. These can be written at power up. This is included to indicate that the below values do not necessarily need to bemodified when the synthesizer frequency is changed (unless the register contains more than one function).SPIWrite 261,00 // Set Rx LO Power modeSPIWrite 2A1,00 // Set Tx LO Power modeSPIWrite 248,0B // Enable Rx VCO LDOSPIWrite 288,0B // Enable Tx VCO LDOSPIWrite 246,02 // Power Down Cal Tcf (RX)SPIWrite 286,02 // Power Down Cal Tcf (TX)SPIWrite 243,0D // Set Prescaler BiasSPIWrite 283,0D // Set Prescaler BiasSPIWrite 245,00 // Set VCO Cal Ref Tcf[2:0] (RX)SPIWrite 250,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Ref[3:0] (RX)SPIWrite 285,00 // Set VCO Cal Ref Tcf[2:0] (TX)SPIWrite290,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Ref[3:0] (TX)SPIWrite 239,C1 // Init ALC Value (RX)SPIWrite 279,C1 // Init ALC Value (TX)SPIWrite 23B,80 // Ensure MSB Set (Set to 1 from Reg Map) (RX)SPIWrite 27B,80 // Ensure MSB Set (Set to 1 from Reg Map) (TX)SPIWrite 23D,00 // Clear Half VCO cal clock settingSPIWrite 27D,00 // Clear Half VCO cal clock settingIF TDD,IF (80 MHz TABLE) OR (60 MHz TABLE)SPIWrite 249,86 // VCO Cal Count 256 (RX)SPIWrite 289,86 // VCO Cal Count 256 (TX)IF (40 MHz TABLE)SPIWrite 249,82 // VCO Cal Count 128(RX)SPIWrite 289,82 // VCO Cal Count 128 (TX)End IFEnd IFIF FDD,SPIWrite 249,8E // VCO Cal Count 1024 (RX)SPIWrite 289,8E // VCO Cal Count 1024 (TX)End IFPage 25 of 47Page 26 of 47EXAMPLE PROGRAMMING SEQUENCEThe following example PLL sequence assumes a 40MHz Reference Frequency is applied to the device with 2X reference scaler, FDD mode, 800MHz RX frequency, 850MHz TX frequency, and therefore uses data from Table 9 FDD 80MHz Loop Reference . Once initialized, frequency adjustmentsrequire only changing the RFPLL dividers and the VCO parameters from the table (unless the charge pump and/or loop filter are updated as well).Because the RX programmed to 800MHz, the VCO will be operating at 6.4GHz, therefore RX data will be taken from the Index 45 line. Similarly, with the TX programmed to 850MHz, the VCO will be operating at 6.8GHz, therefore the TX data will be taken from the Index line 38.In operation, a charge pump cal would first be completed, then the synthesizer is configured.//************************************************************ // FDD RX/TX Synth Frequency: 800.000000,850.000000 MHz //************************************************************ //************************************************************ // Setup Synthesizer (RX)//************************************************************ SPIWrite 23A,4A // Set VCO Output level[3:0] SPIWrite 239,C3 // Set Init ALC Value[3:0] and VCO Varactor[3:0] SPIWrite 242,1F // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] SPIWrite 238,78 // Set VCO Cal Offset[3:0]SPIWrite 245,00 // Set VCO Cal Ref Tcf[2:0] (NOTE: ACCOMPLISHED IN FIXED WRITE SECTION)SPIWrite 251,0C // Set VCO Varactor Reference[3:0]SPIWrite250,70// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Ref[3:0] (NOTE: ACCOMPLISHED IN FIXED WRITE SECTION)SPIWrite 240,09 // Set Rx Synth Loop filter R3 SPIWrite 23F,DF // Set Rx Synth Loop filter R1 and C3 SPIWrite 23E,D4 // Set Rx Synth Loop filter C2 and C1 SPIWrite 23B,92 // Set Rx Synth Loop filter Icp//************************************************************ // Setup Synthesizer (TX)//************************************************************ SPIWrite 27A,4A // Set VCO Output level[3:0] SPIWrite 279,C1 // Set Init ALC Value[3:0] and VCO Varactor[3:0] SPIWrite 282,17 // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0] SPIWrite 278,70 // Set VCO Cal Offset[3:0]SPIWrite 285,00 // Set VCO Cal Ref Tcf[2:0] (NOTE: ACCOMPLISHED IN FIXED WRITE SECTION)SPIWrite 291,0E // Set VCO Varactor Reference[3:0] SPIWrite290,70// Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Ref[3:0] (NOTE: ACCOMPLISHED IN FIXED WRITE SECTION)SPIWrite 280,09 // Set Tx Synth Loop filter R3SPIWrite 27F,DF // Set Tx Synth Loop filter R1 and C3 SPIWrite 27E,D4 // Set Tx Synth Loop filter C2 and C1 SPIWrite 27B,98// Set Tx Synth Loop filter IcpPage 27 of 47SPIWrite 233,00 // Write Rx Synth Fractional Freq Word[7:0] SPIWrite 234,00 // Write Rx Synth Fractional Freq Word[15:8] SPIWrite 235,00 // Write Rx Synth Fractional Freq Word[22:16] SPIWrite 232,00 // Write Rx Synth Integer Freq Word[10:8] SPIWrite231,50// Write Rx Synth Integer Freq Word[7:0]SPIWrite005,22// Set LO divider setting (NOTE: ACCOMPLISHED IN FIXED WRITE SECTION)SPIWrite 273,00 // Write Tx Synth Fractional Freq Word[7:0] SPIWrite 274,00 // Write Tx Synth Fractional Freq Word[15:8] SPIWrite 275,00 // Write Tx Synth Fractional Freq Word[22:16] SPIWrite 272,00 // Write Tx Synth Integer Freq Word[10:8]SPIWrite271,55// Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)SPIWrite005,22// Set LO divider setting (NOTE: ACCOMPLISHED IN FIXED WRITE SECTION)SPIRead 247 // Check RX RF PLL lock status (0x247[1]==1 is locked) SPIRead 287 // Check TX RF PLL lock status (0x287[1]==1 is locked) //************************************************************Page 28 of 47TDD MODE – FASTER LOCK TIMESIn TDD mode, the RX and TX synthesizers are alternately turned on and off, following the state of the TXNRX control line. Typically the synthesizer is set to trigger a VCO calibration every time it powers up so that it has a ‘fresh’ calibration value. If the LO frequency in TDD does not change from frame to frame, it is not necessary to recalibrate the VCO every time. The synthesizers retain the VCO cal result even after the synthesizer is powered down. When bursting between TX/ALERT/RX … on the same LO frequency, the synthesizer only needs to relock and can possibly be completed in 25µs or less, depending on the loop bandwidth. To setup synth:1.Setup VCO for FDD applications (longest, most accurate cal. with Temp compensation enabled) 2. Perform VCO calibration3. Write Bypass LD Synth to one (reg. 0x230[0] RX and 0x270[0] TX)Step 3 disables the triggering of all VCO cals, including writing of new Integer word. If a new cal is needed, this must be cleared.NOTE: If the LO frequency is changed, the VCOs will need to be recalibrated so it will retain the information pertaining to the new frequency.。

ADI 推新款频率合成器ADF4371 支持各种射频/微波
系统设计
中国，北京—Analog Devices，Inc. （ADI）近日宣布推出一款先进的频率合成器ADF4371，采用了锁相环（PLL）、完全集成式压控振荡器（VCO）并集成低压差调节器（LDO）和跟踪滤波器技术。

全新ADF4371
支持各种射频/微波系统设计，能够满足航空航天、测试/测量、通信基础设施以及高速转换器时钟等多个市场严苛的下一代产品设计要求。

ADF4371 运用ADI 公司在射频和微波频率合成器领域25 年的专业知识进行设计，是当今市场上性能最高的频率合成器，提供62MHz 至32GHz 最宽的连续射频输出范围。

此器件结合超低PLL FOM
（-234dBc/Hz）、超低杂散（-100dBc 典型值）、低VCO 相位噪声（8GHz 下1MHz 失调时为-134dBc/Hz）以及内置的跟踪滤波器技术，具有出色的性能和适用性。

它采用功能丰富的可灵活配置架构，因此设计人员只需
选用一种超紧凑的频率合成器解决方案，就能满足这些频率范围内的几乎任。

AD9361学习记录一、简介AD9361是ADI推出的面向3G和4G基站应用的高性能、高集成度的射频解决方案。

该器件集RF前端与灵活的混合信号基带部分为一体，集成频率合成器，为处理器提供可配置数字接口。

AD9361接收器LO工作频率范围为70 MHz至6.0 GHz，发射器LO工作频率范围为47 MHz至6.0 GHz，涵盖大部分特许执照和免执照频段，支持的通道带宽范围为200 kHz以下至56 MHz。

两个独立的直接变频接收器拥有首屈一指的噪声系数和线性度。

每个接收(RX)子系统都拥有独立的自动增益控制(AGC)、直流失调校正、正交校正和数字滤波功能，从而消除了在数字基带中提供这些功能的必要性。

The AD9361还拥有灵活的手动增益模式，支持外部控制。

每个通道搭载两个高动态范围模数转换器(ADC)，先将收到的I 信号和Q信号进行数字化处理，然后将其传过可配置抽取滤波器和128抽头有限脉冲响应(FIR)滤波器，结果以相应的采样率生成12位输出信号。

发射器采用直接变频架构，可实现较高的调制精度和超低的噪声。

这种发射器设计带来了行业最佳的TX误差矢量幅度(EVM)，数值不到−40 dB，可为外部功率放大器(PA)的选择留出可观的系统裕量。

板载发射(TX)功率监控器可以用作功率检测器，从而实现高度精确的TX功率测量。

完全集成的锁相环(PLL)可针对所有接收和发射通道提供低功耗的小数N分频频率合成。

设计中集成了频分双工(FDD)系统需要的通道隔离。

二、AD9361系统构成AD9361的框架如下图2-1所示：图2-1它支持2x2 MIMO 通信，收发各有两条独立的射频通路。

TX 射频前端构成如下图2-2所示：PhaseSpiltter TX SecondaryFilter TX FilterATTNDAC INPUTRF OUTPUT图2-2TX 数据通路如下图2-3所示：图2-3RX 射频前端构成如下图2-4所示：PhaseSpiltter TIA RX Filter LNAADC OUTPUTRF INPUT图2-4RX 数据通路如下图2-5所示：图2-5三、初始化及校准总述AD9361在上电之后便会进入休眠状态。