ssd1963ql9使用手册
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5.1 5.2 80 BALLS TFBGA................................................................................................................................................10 128 PINS LQFP ....................................................................................................................................................11
7.1 MCU INTERFACE .................................................................................................................................................16 7.1.1 6800 Mode ..................................................................................................................................................16 7.1.2 8080 Mode ..................................................................................................................................................16 7.1.3 Register Pin Mapping .................................................................................................................................16 7.1.4 Pixel Data Format ......................................................................................................................................16 7.1.5 Tearing Effect Signal (TE) ..........................................................................................................................17 7.2 SYSTEM CLOCK GENERATION .............................................................................................................................18 7.3 FRAME BUFFER....................................................................................................................................................19 7.4 SYSTEM CLOCK AND RESET MANAGER ...............................................................................................................19 7.5 LCD CONTROLLER ..............................................................................................................................................20 7.5.1 Display Format ...........................................................................................................................................20 7.5.2 General Purpose Input/Output (GPIO) ......................................................................................................20
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1963
Advance Information
1215KB Embedded Display SRAM LCD Display Controller
This document contains information on a new product. Specifications and information herein are subject to change without notice. SSD1963 Rev 1.1 P 1/93 Copyright © 2010 Solomon Systech Limited
6 7
PIN DESCRIPTIONS ................................................................................................................ 13 FUNCTIONAL BLOCK DESCRIPTIONS ...................................................................-09
18-May-09
1.1 23-Dec-09
18-Jan-10
Solomon Systech
Jan 2010
P 2/93
Rev 1.1
SSD1963
CONTENTS 1 2 3 4 5 GENERAL DESCRIPTION ....................................................................................................... 8 FEATURES................................................................................................................................... 8 ORDERING INFORMATION ................................................................................................... 8 BLOCK DIAGRAM .................................................................................................................... 9 PIN ARRANGEMENT.............................................................................................................. 10
Jan 2010
Appendix: IC Revision history of SSD1963 Specification Version 0.10 21-Nov-08 0.10 08-Dec-08 Change Items 1st Release 1. 2. 3. 4. Changed the set_pll_mnk to set_pll_mn in section 7.2 Change register name in section 8 Removed ABC Revised description for REG 0x00, 0x01, 0x0C, 0x0D, 0x0E, 0x10, 0x11, 0x21, 0x26, 0x28, 0x2A, 0x2B, 0x2C, 0x2E, 0x33, 0x34, 0x35, 0x36, 0x37, 0x3A, 0x3C, 0x3E, 0x44, 0x45, 0xA1, 0xB0, 0xB1, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBE, 0xBF, 0xD0, 0xD1, 0xD4, 0xE5. 5. Added max VIH in Table 12-1 6. Added Table 9-1 7. Added Table 11-1 8. Revised Figure 9-19 9. Revised Figure 14-2 10. Revised Figure 13-5 11. Corrected typo for Table 7-2 12. Revised test condition for 12 and 13 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 1. 2. Changed status to Advance Information Update min/max rating of VDDD and VDDPLL in Table 11-1 Added tape and reel drawing of 128-pin LQFP package in Section 15.3 Revised Section 13.2 5. Added 12 bits for Table 7-1 Removed TTL interface Revised section 7.1.5 Change the title of section 7.2 Revised command description in section 8 Removed the command 0x0C and 0x3A Added figures in section 13.4 Revised figures in section 13.3 Revise Table 6-1 Update Table 7-1 Revised section 9.72 Effective Date 24-Nov-08 10-Dec-08
7.1 MCU INTERFACE .................................................................................................................................................16 7.1.1 6800 Mode ..................................................................................................................................................16 7.1.2 8080 Mode ..................................................................................................................................................16 7.1.3 Register Pin Mapping .................................................................................................................................16 7.1.4 Pixel Data Format ......................................................................................................................................16 7.1.5 Tearing Effect Signal (TE) ..........................................................................................................................17 7.2 SYSTEM CLOCK GENERATION .............................................................................................................................18 7.3 FRAME BUFFER....................................................................................................................................................19 7.4 SYSTEM CLOCK AND RESET MANAGER ...............................................................................................................19 7.5 LCD CONTROLLER ..............................................................................................................................................20 7.5.1 Display Format ...........................................................................................................................................20 7.5.2 General Purpose Input/Output (GPIO) ......................................................................................................20
SOLOMON SYSTECH
SEMICONDUCTOR TECHNICAL DATA
SSD1963
Advance Information
1215KB Embedded Display SRAM LCD Display Controller
This document contains information on a new product. Specifications and information herein are subject to change without notice. SSD1963 Rev 1.1 P 1/93 Copyright © 2010 Solomon Systech Limited
6 7
PIN DESCRIPTIONS ................................................................................................................ 13 FUNCTIONAL BLOCK DESCRIPTIONS ...................................................................-09
18-May-09
1.1 23-Dec-09
18-Jan-10
Solomon Systech
Jan 2010
P 2/93
Rev 1.1
SSD1963
CONTENTS 1 2 3 4 5 GENERAL DESCRIPTION ....................................................................................................... 8 FEATURES................................................................................................................................... 8 ORDERING INFORMATION ................................................................................................... 8 BLOCK DIAGRAM .................................................................................................................... 9 PIN ARRANGEMENT.............................................................................................................. 10
Jan 2010
Appendix: IC Revision history of SSD1963 Specification Version 0.10 21-Nov-08 0.10 08-Dec-08 Change Items 1st Release 1. 2. 3. 4. Changed the set_pll_mnk to set_pll_mn in section 7.2 Change register name in section 8 Removed ABC Revised description for REG 0x00, 0x01, 0x0C, 0x0D, 0x0E, 0x10, 0x11, 0x21, 0x26, 0x28, 0x2A, 0x2B, 0x2C, 0x2E, 0x33, 0x34, 0x35, 0x36, 0x37, 0x3A, 0x3C, 0x3E, 0x44, 0x45, 0xA1, 0xB0, 0xB1, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBE, 0xBF, 0xD0, 0xD1, 0xD4, 0xE5. 5. Added max VIH in Table 12-1 6. Added Table 9-1 7. Added Table 11-1 8. Revised Figure 9-19 9. Revised Figure 14-2 10. Revised Figure 13-5 11. Corrected typo for Table 7-2 12. Revised test condition for 12 and 13 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 1. 2. Changed status to Advance Information Update min/max rating of VDDD and VDDPLL in Table 11-1 Added tape and reel drawing of 128-pin LQFP package in Section 15.3 Revised Section 13.2 5. Added 12 bits for Table 7-1 Removed TTL interface Revised section 7.1.5 Change the title of section 7.2 Revised command description in section 8 Removed the command 0x0C and 0x3A Added figures in section 13.4 Revised figures in section 13.3 Revise Table 6-1 Update Table 7-1 Revised section 9.72 Effective Date 24-Nov-08 10-Dec-08
