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PHD10N10E中文资料

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Philips SemiconductorsProduct Specification PowerMOS transistorPHD10N10E

GENERAL DESCRIPTIONQUICK REFERENCE DATA

N-channel enhancement modeSYMBOLPARAMETERMAX.UNITfield-effect power transistor in aplastic envelope suuitable forVDSDrain-source voltage100Vsurface mounting. The device isIDDrain current (DC)11Aintended for use in Switched ModePtotTotal power dissipation60WPower Supplies (SMPS), motorTjJunction temperature175˚Ccontrol, welding, DC/DC and AC/DCRDS(ON)Drain-source on-state resistance0.25Ωconverters, and in general purposeswitching applications.

PINNING - SOT428PIN CONFIGURATIONSYMBOL

PINDESCRIPTION

1gate

2drain

3source

tabdrain

LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)SYMBOLPARAMETERCONDITIONSMIN.MAX.UNITVDSDrain-source voltage--100VVDGRDrain-gate voltageRGS = 20 kΩ-100V±VGSGate-source voltage--30VIDDrain current (DC)Tmb = 25 ˚C-11AIDDrain current (DC)Tmb = 100 ˚C-7.7AIDMDrain current (pulse peak value)Tmb = 25 ˚C-44APtotTotal power dissipationTmb = 25 ˚C-60WTstgStorage temperature-- 55175˚CTjJunction Temperature--175˚C

THERMAL RESISTANCES

SYMBOLPARAMETERCONDITIONSTYP.MAX.UNITRth j-mbThermal resistance junction to-2.5K/Wmounting baseRth j-aThermal resistance junction topcb mounted, minimum50-K/Wambientfootprint123tabd

g

s

September 19971Rev 1.000元器件交易网www.cecb2b.comPhilips SemiconductorsProduct Specification PowerMOS transistorPHD10N10E

STATIC CHARACTERISTICSTj = 25 ˚C unless otherwise specifiedSYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNITV(BR)DSSDrain-source breakdownVGS = 0 V; ID = 0.25 mA100--VvoltageVGS(TO)Gate threshold voltageVDS = VGS; ID = 1 mA2.13.04.0VIDSSZero gate voltage drain currentVDS = 100 V; VGS = 0 V; Tj = 25 ˚C-110µAIDSSZero gate voltage drain currentVDS = 100 V; VGS = 0 V; Tj = 125 ˚C-0.11.0mAIGSSGate source leakage currentVGS = ±30 V; VDS = 0 V-10100nARDS(ON)Drain-source on-stateVGS = 10 V; ID = 5.5 A-0.220.25Ωresistance

DYNAMIC CHARACTERISTICSTj = 25 ˚C unless otherwise specifiedSYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNITgfsForward transconductanceVDS = 25 V; ID = 5.5 A34.2-SCissInput capacitanceVGS = 0 V; VDS = 25 V; f = 1 MHz-400500pFCossOutput capacitance-90120pFCrssFeedback capacitance-3550pFtd onTurn-on delay timeVDD = 30 V; ID = 3 A;-914nstrTurn-on rise timeVGS = 10 V; RGS = 50 Ω;-2540nstd offTurn-off delay timeRgen = 50 Ω-3045nstfTurn-off fall time-2040nsLdInternal drain inductanceMeasured from tab to centre of die-4.5-nHLsInternal source inductanceMeasured from source lead solder-7.5-nHpoint to source bond pad

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICSTj = 25 ˚C unless otherwise specifiedSYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNITIDRContinuous reverse drain---11AcurrentIDRMPulsed reverse drain current---44AVSDDiode forward voltageIF = 11 A ; VGS = 0 V-1.21.5VtrrReverse recovery timeIF = 11 A; -dIF/dt = 100 A/µs;-90-nsQrrReverse recovery chargeVGS = 0 V; VR = 30 V-0.35-µC

AVALANCHE LIMITING VALUETmb = 25 ˚C unless otherwise specifiedSYMBOLPARAMETERCONDITIONSMIN.TYP.MAX.UNITWDSSDrain-source non-repetitiveID = 11 A ; VDD ≤ 50 V ;--35mJunclamped inductive turn-offVGS = 10 V ; RGS = 50 Ωenergy

September 19972Rev 1.000元器件交易网www.cecb2b.comPhilips SemiconductorsProduct Specification PowerMOS transistorPHD10N10E

Fig.1. Normalised power dissipation.PD% = 100⋅PD/PD 25 ˚C = f(Tmb)

Fig.2. Normalised continuous drain current.ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V

Fig.3. Safe operating area. Tmb = 25 ˚CID & IDM = f(VDS); IDM single pulse; parameter tpFig.4. Transient thermal impedance.Zth j-mb = f(t); parameter D = tp/T

Fig.5. Typical output characteristics, Tj = 25 ˚C.ID = f(VDS); parameter VGS

Fig.6. Typical on-state resistance, Tj = 25 ˚C.RDS(ON) = f(ID); parameter VGS020406080100120140160180Tmb / CPD%Normalised Power Derating120 110 100 90 80 70 60 50 40 30 20 10 0 1E-071E-051E-031E-011E+01t / sZth j-mb / (K/W)1E+01

1E+00

1E-01

1E-02 00.50.20.10.050.02D = tptp

TTP

tDBUKX52

020406080100120140160180Tmb / CID%Normalised Current Derating120 110 100 90 80 70 60 50 40 30 20 10 0 0246810BUK452-100A

VDS / V20

15

10

5

0 45678101520ID / A

VGS / V =

1100VDS / VID / A100

10

1

0.1BUK452-100

10tp = 10 us

100 us1 ms10 ms100 msDCRDS(ON) = VDS/IDAB

02468101214161820BUK452-100A

ID / A1.0

0.8

0.6

0.4

0.2

0 4.555.566.577.5810

20RDS(ON) / Ohm

VGS / V =

September 19973Rev 1.000元器件交易网www.cecb2b.comPhilips SemiconductorsProduct Specification PowerMOS transistorPHD10N10E

Fig.7. Typical transfer characteristics.ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj

Fig.8. Typical transconductance, Tj = 25 ˚C.gfs = f(ID); conditions: VDS = 25 V

Fig.9. Normalised drain-source on-state resistance.a = RDS(ON)/RDS(ON)25 ˚C = f(Tj); ID = 5.5 A; VGS = 10 VFig.10. Gate threshold voltage.VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS

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BH-10中文资料

BH-10中文资料

Adam Technologies, Inc.

909 Rahway Avenue• Union, New Jersey 07083• T: 908-687-5000• F: 908-687-5710• 360BATTERY HOLDERSAAA, D SINGLE & MULTIPLE CELLSBH SERIES

[25.20][29.20]BH-132 CELL"C" BH-13-32.430 [61.70].9921.150ø.090 [2.30]2.410 [61.20]2.210[56.10].900[22.80]ø.157 [4.00]ø.130 [3.30]4.303 [109.30]2.146[54.5]2.130 [54.10]1.012[25.7].153 [3.90].264 [6.70]ø.157 [4.00]BH-144 CELL"C" BH-14-3.4[11]1.2 [31].1 [3].52[13.2]2.06 [52.3].97[24.7]ø.09 [2.4].5 [13]2.06 [52.3].96 [24.5].93 [23.7]BH-102 CELL"AAA" BH-10-3元器件交易网

78L10中文资料

78L10中文资料

D3-Terminal RegulatorsDOutput Current up to 100 mADNo External ComponentsDInternal Thermal-Overload ProtectionDInternal Short-Circuit Current LimitingDProvided Pb-Free packages from the endof 2004descriptionThis series of fixed-voltage integrated-circuitvoltage regulators is designed for a wide range ofapplications. These applications include on-cardregulation for elimination of noise and distributionproblems associated with single-point regulation.In addition, they can be used with power-passelements to make high-current voltage regulators.One of these regulators can deliver up to 100 mAof output current. The internal limiting andthermal-shutdown features of these regulatorsmake them essentially immune to overload. Whenused as a replacement for a zener diode-resistorcombination, an effective improvement in outputimpedance can be obtained, together with lowerbias current.electrical characteristics at specified virtual junction temperature, VI = otherwise noted)PARAMETERTEST CONDITIONST‡UNITMINTYPMAX25°COutput voltage Full rangeVIO = 1 mA to 70 mAFull rangeInputVI = °voltage regulationVI = Ripple rejectionVI = f = 120 Hz25°CdBOutputIO = 1 mA to 100 mA°voltage regulationIO = 1 mA to 40 mAOutputnoise voltagef = 10 Hz to 100 kHz25°CµVDropout voltage25°CV25°C6 125°C5.5BiasVI = 1.5current changeIO = 1 mA to 40 mA range0.1‡Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All characteristics aremeasured with a 0.33-µF capacitor across the input and a 0.1-µF capacitor across the output. Full range for the 78L05 is TJ = 0°C to 70°CWing Shing Computer Components Co., (H.K.)Ltd.Tel:(852)2341 9276 Fax:(852)2797 8153Homepage:E-mail: wsccltd@元器件交易网Positive-Voltage Regulators

FPGA可编程逻辑器件芯片EP3C10E144I7N中文规格书

FPGA可编程逻辑器件芯片EP3C10E144I7N中文规格书

Table 65.Example: Generating Output Clocks Using an IOPLL IP (Receiver in DPA or

Soft-CDR Mode)

This table lists the parameter values that you can set in the IOPLL IP parameter editor to generate four output

clocks using an IOPLL IP if you are using the DPA or soft-CDR receiver.Parameteroutclk0

(Connects as

lvds_clk[1:0] to the

ext_lvds_clk[1:0]ports of LVDS SERDES

IP transmitter or

receiver)outclk1

(Connects as

loaden[1:0] to the

ext_loaden[1:0]ports of LVDS SERDES

IP transmitter or

receiver)

Not required for the

soft-CDR receiver.outclk4

(Used as the core clock

for the parallel data

registers for both

transmitter and

receiver, and connects

to the ext_coreclock

port of LVDS SERDES

IP)VCO Frequency

(Connects as

phout[7:0] to the

ext_vcoph[7:0] portof LVDS SERDES IP)

Frequencydata ratedata rate/serialization

factordata rate/serialization

SS8PH10中文资料

SS8PH10中文资料

New ProductSS8PH9 & SS8PH10Vishay General Semiconductor

Document Number: 88989Revision: 30-Jul-08For technical questions within your region, please contact one of the following:PDD-Americas@, PDD-Asia@, PDD-Europe@1High Current Density Surface MountHigh-Voltage Schottky RectifierFEATURES •Very low profile - typical height of 1.1 mm •Ideal for automated placement •Guardring for overvoltage protection •High barrier technology, TJ = 175 °Cmaximum •Low leakage current •Meets MSL level 1, per J-STD-020, LF maximumpeak of 260 °C •Component in accordance to RoHS 2002/95/ECand WEEE 2002/96/EC •Halogen-freeMECHANICAL DATACase: TO-277A (SMPC)Molding compound meets UL 94V-0 flammabilityrating.Base P/N-E3 - RoHS compliant, commercial gradeBase P/NHE3 - RoHS compliant, high reliability/automotive grade (AEC-Q101 qualified)Base P/N-M3 - halogen-free and RoHS compliant,commercial gradeBase P/NHM3 - halogen-free and RoHS compliant,high reliability/automotive grade (AEC-Q101 qualified)Terminals: Matte tin plated leads, solderable perJ-STD-002 and JESD22-B102E3 and M3 suffix meets JESD 201 class 1A whiskertest, HE3 and HM3 suffix meets JESD 201 class 2