MDM-25PCBRM7-A174中文资料

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电力与能源电力石油石化交通工业与机器矿业/建材水利/水处理汽车数据中心IT高科技互联网商业网络银行保险金融机构电信运营楼宇办公楼宇工业建筑基础设施住宅住宅建设公共建设小区设施剩余电流保护断路器逆变器直流断路器直流塑壳断路器直流框架断路器光伏箱变直流熔断器直流浪涌保护器终端新能源HS11FH系列防护型开启式刀开关B -117HD11F系列防误型开启式刀开关B -119RDM1系列塑料外壳式断路器B -001RDM10系列塑料外壳式断路器B -010DZ20系列塑料外壳式断路器B -015DZ15系列塑料外壳式断路器B -020RDM1E系列电子式塑壳断路器B -023RDM1L系列漏电断路器B -043RDL20系列漏电断路器B -057DZL25系列漏电断路器B -064DZ15LE系列漏电断路器B -060RDL18系列漏电断路器B -068RDWQ2系列双电源自动转换开关B -080RDQ6系列双电源自动转换开关B -082RDH5D系列双电源自动转换开关B -088HD 、HS系列开启式刀开关B -101RDQH系列双电源自动转换开关B -070RDQ1系列双电源自动转换开关B -077HD11FH系列防护型开启式刀开关B -121RDH5系列隔离开关B -123HR3系列熔断器式刀开关B -130HR5系列熔断器式隔离开关B -133RDH5DS系列双电源自动转换开关B -096RDM1EL系列电子式塑壳断路器B -051HR17B系列熔断器隔离开关B -141RDT16系列有填料封闭管式刀型触头熔断器B -155HH15系列隔离开关熔断器组B -146RDH5R系列隔离开关熔断器组B -143NGT系列快速熔断器B -174RS0、RS3系列快速熔断器B -171RT0系列有填料封闭管式刀型触头熔断器B -168RT14系列有填料封闭式管圆筒形帽熔断器B -165HG30熔断器式隔离器B -163RT18系列有填料封闭管式圆筒形帽熔断器B -160HR6系列熔断器式隔离开关B -136RDHG2B系列条型熔断器式隔离开关B -139全国统一客服热线: 400 898 1166 001选型指南产品概述RDM1系列塑料外壳式断路器具有体积小、分断能力高、飞弧短、抗震动的特点, 是陆地及船舶使用的理想产品。

ADL-025SH中文资料Delay LinesADL SeriesActive Delay LinesLeadFEATURESWaveform shaping circuits are not required for the built-in TTL IC.Integration into a dual-inline package achieves a compact size only 5.08mm in height.These delay lines are transfer molded using high-performance resins.They can be used with automated inserters. MAXIMUM RATINGSELECTRICAL CHARACTERISTICSRepeat cycle T=Td × 30?Measuring conditionsPower supply vo ltage Vcc: 5±0.1V/Ambient temperature: 25±1°C/No load between each tapPower supply voltage Vcc 7VInput voltage Vin–0.5 to +5.5V T emperature rangeOperating 0 to +70°C Storage–55 to +125°CPart No.T otal delay time Td(ns)Delay time between each tap td(ns)Rise time (ns)max.Minimum input pulse width ?(ns)min.ADL-020SH 20±24±248ADL-025SH 25±35±2410ADL-050SH 50±310±2420ADL-060SH 60±312±3424ADL-075SH 75±5%15±3430ADL-100SH 100±5%20±3440ADL-125SH 125±5%25±3450ADL-150SH 150±5%30±3460ADL-200SH 200±5%40±3480A DL-250SH 250±5%50±34100元器件交易网E121_ADL980601Delay LinesADL SeriesActive Delay LinesLeadMEASURING CONDITIONSWAVEFORMSINPUT/OUTPUT CHARACTERISTICSOUTPUT LOAD CONDITIONSInput voltage Vi3.2VPulse width conversion Pw Td(T otal delay time) × 3Repeat cycle T Pw × 10 [Duty: 10%]Input rise time T ri5ns max.Power supply voltage V CC 5±0.1V Ambient temperature T a25±1°CItemMeasuring conditionsStandard value Minimum Nominal Maximum Power supply voltage V CC 4.75V 5V 5.25V Input voltage (H level) V IH 2V ——Input voltage (L level) V IL ——0.8V Output voltage (H level) V OH V CC =4.75VV IH =2V I OH =–1mA 2.7V3.4V—Output voltage (L level) V OLV CC =4.75V V IL =0.8V I OL =20mA ——0.5VInput current (H level) I IH V CC =5.25V V I =2.7V ——50μA Input current (L level) I IL V CC =5.25V V I =0.5V ——–2mA Power supply current I CCLV CC =5.25V V IL =0V—47mA65mALogic 1 output 20TTL load/tap [I OH /I IH =1mA/50μA=20]Logic 0 output10TTL load/tap [I OH /I IL=20mA/2mA=10]元器件交易网。

UA741中文资料pdf 应用电路（组图） uA741M，uA741I，uA741C（单运放）是高增益运算放大器，用于军事，工业和商业应用.这类单片硅集成电路器件提供输出短路保护和闭锁自由运作。

这些类型还具有广泛的共同模式，差模信号范围和低失调电压调零能力与使用适当的电位。

uA741M，uA741I，uA741C芯片引脚和工作说明：1和5为偏置(调零端)，2为正向输入端，3为反向输入端，4接地，6为输出，7接电源 8空脚温度等级Package 封装 Part Number零件型号 Temperature Range 工作温度范围 N D UA741C 0℃ - +70℃ ? ? UA741I -40℃ - +105℃ ? ? UA741M -55℃ - +125℃ ? ? 例如 : UA741CN ABSOLUTE MAXIMUM RATINGS最大额定值 Symbol符号 Parameter参数 UA741M UA741I UA741C Unit单位 VCC Supply voltage电源电压±22V Vid Differential Input Voltage差分输入电压±30V Vi Input Voltage输入电压±15V Ptot Power Dissipation功耗500mW Toper Output Short-circuit Duration输出短路持续时间 Infinite无限制Operating Free-air Temperature Range工作温度 -55 to +125 -40 to +105 0 to +70℃Tstg Storage Temperature Range储存温度范围 -65 to +150 ELECTRICAL CHARACTERISTICS VCC = ±15V, Tamb = +25°C (unless otherwise specified) 电气特性虚拟通道连接= ± 15V ， Tamb = 25 ℃（除非另有说明） Symbol符号Parameter参数最小. 典型. 最大. Unitd单位 Vio Input Offset Voltage (Rs ≤ 10K?)输入失调电压 - mV Tamb = +25℃ - 1 5 Tmin ≤ Tamb ≤ Tmax - - 6 Iio Input Offset Current 输入失调电流 nA Tamb = +25℃ - 2 30 Tmin ≤ Tamb ≤ Tmax - - 70 Iib Input Bias Current 输入偏置电流 nA Tamb = +25℃ - 10 100 Tmin ≤ Tamb ≤ Tmax - - 200 Avd Large Signal Voltage Gain (Vo=±10V, RL=2K?) 大信号电压增益 V/mV Tamb = +25℃ 50 200 - Tmin ≤ Tamb ≤ Tmax 25 -SVR Supply Voltage Rejection Ratio (Rs ≤ 10K?)电源电压抑制比 dB Tamb = +25℃ 77 90 - Tmin ≤ Tamb ≤ Tmax 77 - - ICC Supply Current, no load 电源电流（空载） mA Tamb = +25℃ - 1.7 2.8 Tmin ≤ Tamb ≤ Tmax - - 3.3 Vicm Input Common Mode Voltage Range 输入共模电压范围 V Tamb = +25℃±12 - - Tmin ≤ Tamb ≤ Tmax ±12 - - CMR Common Mode Rejection Ratio (RS ≤ 10K?)共模抑制比 dB Tamb = +25℃ 70 90 - Tmin ≤ Tamb ≤ Tmax 70 - - IOS Output short Circuit Current输出短路电流 10 25 40 mA ±Vopp Output Voltage Swing输出电压摆幅 Tamb=+25℃ RL=10K? 12 14 - V RL=2K? 10 13 - Tmin≤Tamb ≤Tmax RL=10K? 12 - - RL=2K? 10 - - SR Slew Rate Vi=±10V,RL=2K?,CL=100pF,unity Gain 转换率单位增益 0.25 0.5 - V/μs tr Rise Time Vi = ±20mV, RL =2K?,CL = 100pF, u- 0.3 - μs nity Gain 上升时间单位增益Kov Overshoot Vi=20mV,RL=2K?,CL=100pF,unity Gain 超虚拟单位增益 - 5 - % Ri Input Resistance输入阻抗 0.3 2 - M? GBP Gain Bandwith Product Vi = 10mV, RL =2K?,CL= 100pF, f =100kHz 带宽增益 0.7 1 - MHz THD Total Harmonic Distortion f = 1kHz, Av = 20dB, RL=2K?,Vo=2Vpp, CL=100pF,Tamb=+25℃总谐波失真 - 0.06 - % en Equivalent Input Noise Voltage f=1kHz,Rs=100?等效输入噪声电压 - 23 - nV√Hz ￠m Phase Margin 相位裕度 - 50 - Degrees UA741/ LM741应用电路：图 6 12V的电池监视器图7 低功耗放大器图8 741驱动三极管的5瓦功率放大器图9 自动感光电路图。

Mode Register 1Mode register 1 (MR1) controls various device operating modes as shown in the follow-ing register definition table. Not all settings listed may be available on a die; only set-tings required for speed bin support are available. MR1 is written by issuing the MRS command while controlling the states of the BG x , BA x , and A x address pins. The map-ping of address pins during the MRS command is shown in the following MR1 Register Definition table.Table 9: Address Pin Mapping Address bus BG1BG0BA1BA0A17RAS _n CAS _n WE _nA13A12A11A10A9A8A7A6A5A4A3A2A1A0Moderegister 2120191817–––13121110987654321Note: 1.RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.Table 10: MR1 Register Definition8Gb: x8, x16 Automotive DDR4 SDRAM Mode Register 1does not activate DQS outputs. If WRITE CRC is enabled and a WRITE CRC occurs during the t PAR_UNKNOWN window, the WRITE CRC Error Status Bit located at MR5[3] may or may not get set. When CA Parity and WRITE CRC are both enabled and a CA Parity occurs, the WRITE CRC Error Status Bit should be reset.2.Log the error by storing the erroneous command and address bits in the MPR er-ror log.3.Set the parity error status bit in the mode register to 1. The parity error status bit must be set before the ALERT_n signal is released by the DRAM (that is,t PAR_ALERT_ON + t PAR_ALERT_PW (MIN)).4.Assert the ALERT_n signal to the host (ALERT_n is active LOW) within t PAR_ALERT_ON time.5.Wait for all in-progress commands to complete. These commands were received t PAR_UNKOWN before the erroneous command.6.Wait for t RAS (MIN) before closing all the open pages. The DRAM is not executing any commands during the window defined by (t PAR_ALERT_ON +t PAR_ALERT_PW).7.After t PAR_ALERT_PW (MIN) has been satisfied, the device may de-assertALERT_n.a.When the device is returned to a known precharged state, ALERT_n is al-lowed to be de-asserted.8.After (t PAR_ALERT_PW (MAX)) the DRAM is ready to accept commands for nor-mal operation. Parity latency will be in effect; however, parity checking will not re-sume until the memory controller has cleared the parity error status bit by writing a zero. The DRAM will execute any erroneous commands until the bit is cleared;unless persistent mode is enabled.•It is possible that the device might have ignored a REFRESH command during t PAR_ALERT_PW or the REFRESH command is the first erroneous frame, so it is rec-ommended that extra REFRESH cycles be issued, as needed.•The parity error status bit may be read anytime after t PAR_ALERT_ON +t PAR_ALERT_PW to determine which DRAM had the error. The device maintains the error log for the first erroneous command until the parity error status bit is reset to a zero or a second CA parity occurs prior to resetting.The mode register for the CA parity error is defined as follows: CA parity latency bits are write only, the parity error status bit is read/write, and error logs are read-only bits. The DRAM controller can only program the parity error status bit to zero. If the DRAM con-troller illegally attempts to write a 1 to the parity error status bit, the DRAM can not be certain that parity will be checked; the DRAM may opt to block the DRAM controller from writing a 1 to the parity error status bit.The device supports persistent parity error mode. This mode is enabled by setting MR5[9] = 1; when enabled, CA parity resumes checking after the ALERT_n is de-asser-ted, even if the parity error status bit remains a 1. If multiple errors occur before the er-ror status bit is cleared the error log in MPR Page 1 should be treated as "Don’t Care." In persistent parity error mode the ALERT_n pulse will be asserted and de-asserted by the DRAM as defined with the MIN and MAX value t PAR_ALERT_PW. The DRAM controller must issue DESELECT commands once it detects the ALERT_n signal, this response time is defined as t PAR_ALERT_RSP . The following figures capture the flow of events on the CA bus and the ALERT_n signal.8Gb: x8, x16 Automotive DDR4 SDRAM Command/Address Parity。