北京交通大学考试试题A
课程名称：数字电子技术2014—2015学年第1学期命题教师集体
班级：学号：姓名：
I Concepts (20 points, 2 points/question)
1. of the following binary number is the two's complement representation of the decimal number 14?
(A) 0000 1110 (B) 1111 0010
(C) 0111 1110 (D) 1000 1110
2. The speed of CMOS devices mainly depend on and .
(A) Stray capacitance (B) Source voltage
(C) Load resistance (D) Transistor resistance
3.For a CMOS circuit, of the following conditions has the largest power consumption.
(A) Have large load resistance (B) Whose output is not changing
(C) Have small external capacitances (D) Both of the PMOS and NMOS are on
4. The result of timing hazards is ?
(A) Cause unpredictable outputs (B) Produce a glitch
(C) The output is unstable (D) Make the circuit get into metastability
5. Device is designed for transferring data from one of n sources to the output.
(A) Decoder (B) Encoder
(C) Multiplexer (D) Three state buffer
6. will sample its input and change its output to the state of its input at the rising edge of a clock signal?
(A) Edge-Triggered D Flip-Flop (B) Edge-Triggered J-K Flip-Flop
(C) T Flip-Flop (D) Master/Slave J-K Flip-Flop
7.How to make digital systems deal with asynchronous input signals that are not synchronized with the system clock?
(A)Change the clock frequency (B) Employ a D Flip-Flop as a synchronizer
(C)Use a S-R latch to control the input (D) Add a combinational logic circuit
8.When the high-impedance output of a three-state device and a signal A is connected to the inputs of a TTL AND gate, the output will be .
(A) 0 (B) 1
(C) signal A(D) Inverse of signal A
9. The original transition table of a sequential circuit is given in Table 1, it can be simplified into states.
(A) 2 (B) 1
(C) 3 (D) 0
Table1 Transition table
S n+1/F
10. Of the following memory types，and belong to the volatile memory type.
（A）FPGA （B）EROM （C）SRAM （D）FLASH
II (20 points)
e two CMOS transmission gates and a CMOS inverter to construct the circuit in the
block in Figure 2 (1) to realize the following function, when the input X=1, the output Z =C; when the input X=0, the output Z=B.
2.Two circuits constructed of Edge-Triggered J-K flip-flops are given in Figure 2 (2) (a)
(b). Please analyze the similarities and differences of their logic functions.
Figure 2 (2) （b）
（a）
Z
Figure 2 (1)
III (20 points)
1. Please design the combinational circuit in block A in Figure 3, where three flip-flops are connected (FF0 has an asynchronous set input, FF1 and FF2 have asynchronous reset inputs ), to realize the following function. When the inputs of block A provided by the outputs of the three flip-flops do not include just one logic 1, the output Z of block A is 0, otherwise it is 1.
2. Analyze the logic function of the circuit in Figure
3.
Figure 3 Circuit
