![[VIP专享]肖临骏：声音是第一生产力](https://imgs-1438308264.cos.ap-hongkong.myqcloud.com/b249a258581b6bd97f19eaf0.webp)
没有文化考试，没有粉丝投票，选秀进化成比赛，音乐统治音乐。
这一切是可能的吗？中国电视音乐选秀节目，经历了山寨、收视疲劳、“限娱令”、“去掉一个最高分，去掉一个最低分”……归根结蒂，我们不相信单纯的“音乐”和“声音”是有力量的。
2012年《中国好声音》异军突起，这是《The Voice》的中国版，二百多页的正版“宝典”总结成一句话：如何让声音成为惟一的主角。
世界上有43个声音，中国好声音是普适的声音吗？比赛不必沦落为选秀。
我们能否更狠一点：把声音背后的故事留给观众，只把声音留给评委。
上海，华东师范大学体育馆，远远就可以看到《中国好声音》的巨幅海报，海报前是《中国好声音》高举麦克风做V字状标志性的拳头。
2012年7月26日下午，《中国好声音》正在这里录制导师盲选部分，观众席上座无虚席，连走道里也站满了人。
整个体育馆已经被《中国好声音》节目组租用，第一季的10期节目全部在这里录制。
一位叫妞妞的黑龙江学员演唱那英的《白天不懂夜的黑》，唱功扎实、声情并茂。
一曲终了，却没有一位导师按铃，这意味着她已被淘汰。
四位导师转过椅子，那英泪流满面，哽咽地解释道：“她一开口我就知道是谁了，她的声音我太熟悉了，她是我在演出时的合音。
”但那英没有拍她。
“我不能拍她，观众知道了我们这层关系，一定会说三道四。
但她又唱得这么好，我很后悔没有拍她。
我以前只叫你妞妞，现在才知道你叫王崇……”此时，学员和那英都已经哭成了泪人。
拿到巨人的“宝典”《中国好声音》的四位导师是刘欢、那英、杨坤和庾澄庆，导师背对学员，只听声音定取舍。
节目从2012年7月13日开播后，收视率节节攀升，甚至一直“严打”选秀节目的国家广电总局，也对其做了表扬，7月18日《中国好声音》第一期播出后，国家广电总局宣传管理司副司长高长力公开表态：“以前那么多纯选秀、纯音乐评论节目，为什么不火？《中国好声音》火，就是（因为）导师是顶级的，来唱歌的老百姓的声音也是顶级的，这个节目做到了关照现实和注重品质。
Delta SW Release NotesLE910Cx-EU 25.20.xx2-xx680582DSW10200A Rev. 1 – 2019-11-13 ]61SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICENOTICEWhile reasonable efforts have been made to assure the accuracy of this document, Telit assumes no liability resulting from any inaccuracies or omissions in this document, or from use of the information obtained herein. The information in this document has been carefully checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies or omissions. Telit reserves the right to make changes to any products described herein and reserves the right to revise this document and to make changes from time to time in content hereof with no obligation to notify any person of revisions or changes. Telit does not assume any liability arising out of the application or use of any product, software, or circuit described herein; neither does it convey license under its patent rights or the rights of others.It is possible that this publication may contain references to, or information about Telit products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Telit intends to announce such Telit products, programming, or services in your country. COPYRIGHTSThis instruction manual and the Telit products described in this instruction manual may be, include or describe copyrighted Telit material, such as computer programs stored in semiconductor memories or other media. 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Accordingly, any copyrighted Telit or other 3rd Party supplied SW computer programs contained in the Telit products described in this instruction manual may not be copied (reverse engineered) or reproduced in any manner without the express written permission of Telit or the 3rd Party SW supplier. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit or other 3rd Party supplied SW, except for the normal non-exclusive, royalty free license to use that arises by operation of law in the sale of a product.USAGE AND DISCLOSURE RESTRICTIONSI. License AgreementsThe software described in this document is the property of Telit and its licensors. It is furnished by express license agreement only and may be used only in accordance with the terms of such an agreement.II. Copyrighted MaterialsSoftware and documentation are copyrighted materials. Making unauthorized copies is prohibited by law. No part of the software or documentation may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, without prior written permission of Telit III. High Risk MaterialsComponents, units, or third-party products used in the product described herein are NOT fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control equipment in the following hazardous environments requiring fail-safe controls: the operation of Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life Support, or Weapons Systems (High Risk Activities"). Telit and its supplier(s) specifically disclaim any expressed or implied warranty of fitness for such High Risk Activities.IV. TrademarksTELIT and the Stylized T Logo are registered in Trademark Office. All other product or service names are the property of their respective owners.V. Third Party RightsThe software may include Third Party Right software. In this case you agree to comply with all terms and conditions imposed on you in respect of such separate software. In addition to Third Party Terms, the disclaimer of warranty and limitation of liability provisions in this License shall apply to the Third Party Right software.TELIT HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY “OTHER CODE”), AND THE USE OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE.NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENSE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.APPLICABILITY TABLE PRODUCTSLE910C1-EULE910C4-EUCONTENTSNOTICE 2COPYRIGHTS (2)COMPUTER SOFTWARE COPYRIGHTS (2)USAGE AND DISCLOSURE RESTRICTIONS (3)I.License Agreements (3)II.Copyrighted Materials (3)III.High Risk Materials (3)IV.Trademarks (3)V.Third Party Rights (3)APPLICABILITY TABLE (4)CONTENTS (5)1.INTRODUCTION (6)2.DELTA SW 25.20.XX3 – 25.20.XX6 (8)New Features (8)General Enhancements (8)3.DELTA SW 25.20.XX2 – 25.20.XX3 (14)New Features (14)General Enhancements (15)4.DOCUMENT HISTORY (17)1. INTRODUCTION1.1. ScopeScope of this document is to detail the corrections, changes or enhancements made to the software of Telit modules.1.2. AudienceThis document is intended for Telit customers.1.3. Contact Information, SupportFor general contact, technical support services, technical questions and report documentation errors contact Telit Technical Support at:•*****************•*********************•*****************Alternatively, use:/supportFor detailed information about where you can buy the Telit modules or for recommendations on accessories and components visit:Our aim is to make this guide as helpful as possible. Keep us informed of your comments and suggestions for improvements.Telit appreciates feedback from the users of our information.1.4. Related Documents•80502ST10950A AT Commands Reference Guide for LE910Cx Rev.52. DELTA SW 25.20.XX3 – 25.20.XX6New FeaturesType Description SW 25.20.xx6 NA Introduced new Telit sw naming convention2063 Enabled AP_AP mode 2.4G & 5G hotspot support2114 New LAN bridge driver supported2109 Implemented AT#WLANAPCLIND interface through atfwd_daemon 1938 Supported HSIC interface2058 Added #PDPAUTH command2146Implemented audio loop-back command #OAP47458 Added AT command for PDP type1925 Added support of simultaneous multi sockets2120 Changed SDHN timing to 150msGeneral EnhancementsType Description SW 25.20.xx6 46463 Added fix to avoid OOM after FOTA update47241 Fixed Jammer wrong detected issue47780 Fixed at#wlanmac and at#wlanapclist to support dual AP46973 Modified at#wlanmode command to support "AP+AP" mode and added at#wlancmifsel command which forwards to atfwd-daemon47707 Added Linux Parser47547 Added 5 Cipher suites as QCT original47445 Flashed CNV to stream_flex partition in TFI47543 Modified RFC code of split band for LTE Band 28.47517 Increased timeout when try to attach WE866C346832 Fixed kernel panic when resume from suspend after the WLAN started 47451 Fixed network-connect client issue47387 Enhanced fastboot entering procedure in TFI46630 Fixed wrong action for connection44967 Added SIM power down in case of power-off alarm active45078 [+CGCONTRDP] empty parameter checking (<DNS_prim_addr>) 46011 [#SD] Fixed unexpected "NO CARRIER" when trying to upload the file 47367 Fixed memory leackage in #ECM, #ECMC, #ECMD, #RNDIS, #RNDIC, #RNDISD and #USBCFG commands47312 Fixed memory leackage in #ADELF and #ADELA command47251 Allowed TFI to download with blank IMEI47273 Fixed [+CESQ] Unexpected <ber> when AT+WS46=2847292 Fixed issue when <cid> value is removed and rewrote, Read command return value of +CGEQOS was not displayed in order47300 FOTA update engine47275 Freed dsm memory on ERROR in +CPINR47270 Freed dsm memory about ERROR in #AGPSRCV.47269 Added to dealloc memory when dsat_get_cmd_buf returns NULL, dsatm2mip_exec_ha_srecv_cmd()46991 [+COPS] Read command was returning wrong <Mode> value after set manual/automatic mode46275 Fixed memory leackage in SIMTK_SETUP_MENU support SIM47031 [#SLASTCLOSURE] Fixed socket disconnection when socket inactivity timeout46726 Enhanced #TEMPMON's shutdown feature and temperature ranges 46518 Enabled SPI47130 Enhanced TFI to perform factory reset before first boot47112 Improved AT#SWPKGV behavior46823 [ATD] Fixed type address wrong when in voice call46879 Repeated at#dwconn, AT#DWSEND, AT#DWRCV, end up ATcommands not being answered47020 Improved Telit-sdaemon current consumption in sleep mode47013 M2MB platform upgrade to 30.00.00546978 AT#WLANSSID and AT#WLANSECURITY fixed command parsing error 46227 Fixed TCP connection failure analysis46856 [#CGPADDR] Fixed IP display for PDP context2097 AT#WLANAPING command fixed46802 Fixed the wrong default value of #ENCALG cmd45888 [#CGPADDR] Fixed return value46805 Fixed context deactivation before SSL socket closure46441 Fixed #JDR alerting with incoming calls ( SF #00084723 )46876 Improved ATT CMAS LTE-BTR-5-4100 +CSCB behavior after +CFUN=4 46874 Prevented suspend when the WIFI operate46821 Improved [+CGDCONT] AT+CGDCONT=<cid><CR>46819 Improved [+CGEQOS] command46850 Improved #ALARMPIN disabling46815 Improved URC response for async mode #AGPSSND when there is no response from network46299 Enhanced SMEM's features for APPS GPIO46795 Added TZ and RPM to partition list on FOTA update engine46634 [#RNDIS][#ECM] <cid> range changed fro (0-4) into (0-5)46652 Added HSIC configuration control for apps46668 Set Echo_delay default to 0 in ACDB config45915 [+COPS,+CREG] Fixed URC issue when forbidden network operator is set46650 [WE866C3] AT#WLANCONFIG improved command behavior46228 Fixed the unexpected ber value of +CESQ command46479 #WLANSECURITY fixed open security info display issue46585 [#SGACT] Fixed the AT interface behavior after AT#SGACT=1,0 during data connection(cellular)46214 [+CEER] Fixed extended Error Report46259 Reduction #TONE commend delay46293 [+CGEQMIN][+CGEQREQ][+CGDCONT] fixed read command issue for default defined cid set by TFI download46294 [+CGEQMIN] fixed read command response issue46570 Fixed AT#WLANBD behavior if the option parameter <size> used 46009 Modified for #STUNEANT command for CR2083.46546 [ATRUN] improved Port mapping for URC45388 Fixed fail during file download using HTTP over AT#SD46531 Corrected #CALLINFO test command46542 Fixed DeviceWise URC output issue when multiple raw data mode 46481 Improved socket dial behavior46501 Changed BTM and KTM range46471 Fixed behavior when #HTTPQRY gets to invalid server address of HTTP server46469 [+CPBS] Improved "LD" Phonebook storage.45108 Modified RFC_code for GSM 900, 180046447 +CLCC: When the phonebook memory is selected as the call list, the <alpha> parameter is now displayed.46277 [WE866C3] Applied new bdwlan.bin to solve Tx power degradation issue 46431 [#PSMWDISACFG] Improved response to wrong command46173 Fixed call hung-up the call when ATA & Simultaneously are sent46346 +CEMODE improved dependency on SIM card46340 Improved WE865C3 time for Association ( L2 + L3 ) in LE910+C3 bundle46184 Improved #DNS command45369 [#NITZ] Fixed Date/Time update (#NITZ=2,0 #NITZ=4,0 #NITZ=8,0) 46307 Fixed the display issue of duplicated CMAS for ATT LTE-BTR-5-4073/LTE-BTR-5-408645732 Enhanced port selection in TFI downloader46255 Fixed behavior of oemhp_xxx scripts46235 [#SI] fixed <ack_waiting> parameter behavior46181 [ATD] Improved response during call of a stored phonebook number 45078 [+CGCONTRDP] Fixed empty parameter checking (<DNS_prim_addr>) 46224 Improved backup NV/EFS item on FOTA update3. DELTA SW 25.20.XX2 – 25.20.XX3New FeaturesType Description SW 25.20.xx3 1695 Dual SIM slot supported directly on the xE910 form factor1750 LTE and GNSS jamming detection1774 Implemented #APLAY command1818 Implemented #TONE command1819 Implemented fast shutdown1859 Supported larger file size of certificates on #SSLSECDATA1865 Implemented Remote SIM feature: AT#RSEN1866 Support I2S for DVIGeneral EnhancementsType Description SW 25.20.xx3 43232 Applied TCP linger option for HTTP AT commands43238 SSL Error codes unified as in SSL-TLS User Guide42975 AT[#SGACTCFG] fixed anomalous behavior right after running "AT+COPS=2"command, when <retry> is set 2 or higher43039 Enhancement of call list issue relevant with IMS42053 Fixed issues with AT commands +CPSMS37892 Fixed SSL connection to Amazon AWS, Applied QCT SSL libraries.43052 AT[#FTPOPEN] When trying to do reconnection with AT#FTPOPEN command using the PDP context of CID=3, the FTP command failed to set up FTP session. 42842 AT[#BND] GSM parameter now initiates to default value42980 Fixed an issue of powering up a SIM without checking the SIMIN status at boot time.42390 Volte DTMF tone sound did not stop immediately even if call was disconnected 42861 Jamming was returning false alarm41788 AT[+CESQ] value was different from #MONI RSCP42614 AT[#RNDIS][#ECM][#IMSUA][+CGEQOS] set correct response format42977 Report the jamming status when GLONASS constellation is disabled.42937 AT [#SSLD] <Timeout> parameter fixed.42899 3GPP TS 36.523-1 - 17.1.1 failed regarding to MBMS42912 CLIR facility issue - 34.229-142677 QMI FOTA daemon, wake lock enhancement41729 Fixed FTP Operation problem in the interruption test scenario with MT voice call.42921 AT[#FASTSHDN] Abnormal behavior when GPIO4 is set42903 Fixed wrong and mismatched default value on $SLP command according to $SLPTYPE42605 AT[#TONE] fixed wrong response for dial tone42857 Fixed the behavior of +CEDRXRDP cmd according to rat42833 AT[+CESQ] Wrong value of <rxlev> was reported when module was not GSM registered41707 AT[&C] DCD pin was not working correctly41615 Added AT+CPINR command42616 Implement GPS NMEA over 2nd UART42648 AT[#SSEND] On the command mode with socket AT command, the AT command tended to fail to transmit the given user data if the transmission is suspendedfor internal temporary error.42718 Updated latest TS.25 Network Code42493 Fixed the command #FTPGETOTAENH response issue42820 Enhanced sdhc_1 max_clock for WIFI42875 Fixed anomalous behavior of #FASTSHDN command which operated like a normal shut down.4. DOCUMENT HISTORYRevision Date Changes0 2019-02-15 Delta SW 25.20.xx2 – 25.20.xx31 2019-11-13 Delta SW 25.20.xx3 – 25.20.xx6] 6 1。
RTL8111E-VB-GRINTEGRATED GIGABIT ETHERNET CONTROLLER FOR PCI EXPRESS APPLICATIONSLAYOUT GUIDE(CONFIDENTIAL: Development Partners Only)Rev. 1.325 January 2010Track ID: JATR-2265-11No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, TaiwanTel.: +886-3-578-0211. Fax: +886-3-577-6047Integrated Gigabit Ethernet Controller for PCI Express Applications ii Track ID: JATR-2265-11 Rev. 1.3COPYRIGHT©2010 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of Realtek Semiconductor Corp.DISCLAIMERRealtek provides this document “as is”, without warranty of any kind. Realtek may make improvements and/or changes in this document or in the product described in this document at any time. This document could include technical inaccuracies or typographical errors.TRADEMARKSRealtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners.LICENSEThis product is covered by one or more of the following patents: US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and US6,327,625.USING THIS DOCUMENTThis document is intended for the software engineer’s reference and provides detailed programming information.Though every effort has been made to ensure that this document is current and accurate, more information may have become available subsequent to the production of this guide.REVISION HISTORYRevision Release Date Summary1.0 2009/09/29Firstrelease.1.1 2009/11/06 Added PCI-E differential signal requirements on section2.1 General Guidelines, page3.Added Figure 14 Separate Transformer, page 14.Revised Table 1 Inductor and Capacitor Parts List, page 15.Revised Figure 29 Switching Regulator Efficiency Measurement Checkpoint, page 24.1.2 2009/12/17 Corrected typing errors.1.3 2010/01/25 Revised section 5 Center-Tapping, page 14.Revised section 6.1 Inductor and Capacitor Parts List, page 15.Added Figure 20 L=GLK2510P-2R2M, C=Ceramic 22µF 1206 X5R WISIN (Ripple10.4mV), page 18.Added Figure 23 L=GLK2510P-4R7M, C=Ceramic 22µF 1206 X5R WISIN (Ripple9.2mV), page 20.Revised section 6.5 Power Sequence, page 25.Integrated Gigabit Ethernet Controller for PCI Express Applicationsiii Track ID: JATR-2265-11 Rev. 1.3 Table of Contents1.INTRODUCTION (1)2.DESIGN AND LAYOUT (3)2.1.G ENERAL G UIDELINES (3)2.2.D IFFERENTIAL S IGNAL L AYOUT G UIDELINES (4)2.3.P LACING THE RTL8111E (5)2.4.M AGNETICS (5)2.5.C RYSTAL (5)2.6.F ERRITE B EADS AND D E-C OUPLING C APACITORS (5)3.SIGNAL AND TRACE ROUTING (6)4.GROUND AND POWER PLANE LAYOUT (8)4.1.G ROUND P LANE L AYOUT (8)4.2.P OWER P LANE L AYOUT (10)4.3.F OUR-L AYER B OARD P LANE L AYOUT (11)4.3.1.Signal 1 Plane Layout (Top Layer) (12)4.3.2.Ground Plane Layout (Layer 2) (12)4.3.3.Power Plane Layout (Layer 3) (13)4.3.4.Signal 2 Plane Layout (Bottom Layer) (13)5.CENTER-TAPPING (14)6.SWITCHING REGULATOR (15)6.1.I NDUCTOR AND C APACITOR P ARTS L IST (15)6.2.M EASUREMENT C RITERIA (16)6.3.E FFICIENCY M EASUREMENT (23)6.4.PCB L AYOUT (24)6.5.P OWER S EQUENCE (25)7.PARTS RECOMMENDATIONS (26)7.1.10/100/1000M M AGNETIC (26)7.2.R EFERENCE C LOCK (26)7.3.R ESISTORS (27)7.4.C APACITORS (27)7.5.F ERRITE B EAD (27)7.6.P OWER I NDUCTOR (27)7.7.RJ-45J ACK (27)8.SPECIAL NOTES (28)Integrated Gigabit Ethernet Controller for PCI Express Applicationsiv Track ID: JATR-2265-11 Rev. 1.3 List of FiguresF IGURE 1.S IGNAL T RACE A NGLES (4)F IGURE 2.S IGNAL &T RACE R OUTING (6)F IGURE 3.G ROUND P LANE L AYOUT-1 (8)F IGURE 4.G ROUND P LANE L AYOUT-2 (8)F IGURE 5.G ROUND P LANE S EPARATION (9)F IGURE 6.D ECOUPLED C APACITOR E XAMPLE (10)F IGURE 7.P OWER P LANE (10)F IGURE 8.P OWER S OURCE D ISTRIBUTION (11)F IGURE 9.S IGNAL 1P LANE L AYOUT (T OP L AYER) (12)F IGURE 10.G ROUND P LANE L AYOUT (L AYER 2) (12)F IGURE 11.P OWER P LANE L AYOUT (L AYER 3) (13)F IGURE 12.S IGNAL 2P LANE L AYOUT (B OTTOM L AYER) (13)F IGURE 13.C ENTER-T APPING (14)F IGURE 14.S EPARATE T RANSFORMER (14)F IGURE 15.I NPUT V OLTAGE O VERSHOOT <4V(G OOD) (16)F IGURE 16.I NPUT V OLTAGE O VERSHOOT >4V(B AD) (16)F IGURE 17.C ERAMIC 10µF0603(X5R)(G OOD) (17)F IGURE 18.L=GLK2510P-2R2M,C=C ERAMIC 4.7µF0805X5R TDK(R IPPLE 12.4M V) (17)F IGURE 19.L=GLK2510P-2R2M,C=C ERAMIC 10µF0603X5R YAGEO(R IPPLE 13.2M V) (18)F IGURE 20.L=GLK2510P-2R2M,C=C ERAMIC 22µF1206X5R WISIN(R IPPLE 10.4M V) (18)F IGURE 21.L=GLK2510P-4R7M,C=C ERAMIC 4.7µF0805X5R TDK(R IPPLE 12M V) (19)F IGURE 22.L=GLK2510P-4R7M,C=C ERAMIC 10µF0603X5R YAGEO(R IPPLE 11.2M V) (19)F IGURE 23.L=GLK2510P-4R7M,C=C ERAMIC 22µF1206X5R WISIN(R IPPLE 9.2M V) (20)F IGURE 24.L=GTSD32P-2R2M,C=C ERAMIC 4.7µF0805X5R TDK(R IPPLE 9.2M V) (20)F IGURE 25.C ERAMIC 10µF(Y5V)(B AD) (21)F IGURE 26.E LECTROLYTIC 100µF(R IPPLE T OO H IGH) (21)F IGURE 27.GTSD32P-2R2M(G OOD) (22)F IGURE 28.1µH B EAD (B AD) (22)F IGURE 29.S WITCHING R EGULATOR E FFICIENCY M EASUREMENT C HECKPOINT (24)F IGURE 30.P OWER S EQUENCE (25)Integrated Gigabit Ethernet Controller for PCI Express Applications 1Track ID: JATR-2265-11 Rev. 1.31.IntroductionThe Realtek RTL8111E-VB-GR Gigabit Ethernet controller combines a triple-speed IEEE 802.3 compliant Media Access Controller (MAC) with a triple-speed Ethernet transceiver, PCI Express bus controller, and embedded memory. With state-of-the-art DSP technology and mixed-mode signal technology, the RTL8111E-VB-GR offers high-speed transmission over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable. Functions such as Crossover Detection and Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented to provide robust transmission and reception capability at high speeds.The RTL8111E supports the PCI Express 1.1 bus interface for host communications with power management, and is compliant with the IEEE 802.3u specification for 10/100Mbps Ethernet and the IEEE 802.3ab specification for 1000Mbps Ethernet. It also supports an auxiliary power auto-detect function, and will auto-configure related bits of the PCI power management registers in PCI configuration space. The RTL8111E features embedded One-Time-Programmable (OTP) memory to replace the external EEPROM (93C46/93C56/93C66).Advanced Configuration Power management Interface (ACPI)—power management for modern operating systems that are capable of Operating System-directed Power Management (OSPM)—is supported to achieve the most efficient power management possible. PCI MSI (Message Signaled Interrupt) and MSI-X are also supported.In addition to the ACPI feature, remote wake-up (including AMD Magic Packet™ and Microsoft®Wake-up frame) is supported in both ACPI and APM (Advanced Power Management) environments. To support WOL from a deep power down state (e.g., D3cold, i.e., main power is off and only auxiliary exists), the auxiliary power source must be able to provide the needed power for the RTL8111E.The RTL8111E is fully compliant with Microsoft® NDIS5, NDIS6 (IPv4, IPv6, TCP, UDP) Checksum and Segmentation Task-offload (Large send and Giant send) features, and supports IEEE 802 IP Layer 2 priority encoding and IEEE 802.1Q Virtual bridged Local Area Network (VLAN). The above features contribute to lowering CPU utilization, especially benefiting performance when in operation on a network server.The RTL8111E supports Receive Side Scaling (RSS) to hash incoming TCP connections and load-balance received data processing across multiple CPUs. RSS improves the number of transactions per second and number of connections per second, for increased network throughput.Integrated Gigabit Ethernet Controller for PCI Express Applications 2Track ID: JATR-2265-11 Rev. 1.3Alert Standard Format (ASF 2.0) is also supported to provide system manageability in OS-absent environments. The ASF defines remote control and alerting interfaces that serve managed PCs in OS-absent states. With the ASF capability, we are able to minimize on-site I/T maintenance, to improve system availability, and also to control power management remotely.The RTL8111E supports IEEE 802.3az Draft 2, also known as Energy Efficient Ethernet (EEE). IEEE 802.3az operates with the IEEE 802.3 Media Access Control (MAC) Sublayer to support operation in Low Power Idle mode. When the Ethernet network is in low link utilization, EEE allows systems on both sides of the link to save power.The device also features inter-connect PCI Express technology. PCI Express is a high-bandwidth, low-pin-count, serial, interconnect technology that offers significant improvements in performance over conventional PCI and also maintains software compatibility with existing PCI infrastructure.The RTL8111E is suitable for multiple market segments and emerging applications, such as desktop, mobile, workstation, server, communications platforms, and embedded applications.Integrated Gigabit Ethernet Controller for PCI Express Applications 3Track ID: JATR-2265-11 Rev. 1.32.Design and LayoutSystem designers should follow basic rules in layout and placement, general termination, power supply filtering, plane partitioning, and EMI reduction in order to optimize designs that use the RTL8111E. Following these rules will greatly contribute to a properly functioning hardware system.This guide has the following goals:(1) Create a low-noise, power-stable environment.(2) Reduce the degree of EMI/EMC and their influence on the RTL8111E.(3) Simplify the task of routing signal traces.2.1.General GuidelinesIn order to achieve maximum performance using the RTL8111E, good design practices are required throughout the process. The following are some recommendations for implementing a high-performance system.•Provide a good power source, minimizing noise from switching power supply circuits (<100mV peak-to-peak)•Verify that critical components such as the clock source and transformer meet application requirements •Keep power and ground noise levels below 100mV peak-to-peak•Use bulk capacitors (4.7µF~10µF) between the power and ground planes•Use 0.1µF de-coupling capacitors to reduce high-frequency noise on the power and ground planes •Keep de-coupling capacitors close to the RTL8111E (within 200 mil)•Provide termination on all high-speed switching signals•Use a smaller package for the capacitor to reduce the package inductanceIntegrated Gigabit Ethernet Controller for PCI Express Applications 4Track ID: JATR-2265-11 Rev. 1.3Use the following signal integrity techniques to reduce crosstalk.•Shorter parallel routes•Thinner dielectrics•Proper termination•Provide a solid ground planePCI Express TX/RX differential pairs should comply with the following requirements:•Differential Return Loss ≥ 10dB (measured within a 50MHz~1.25GHz range)•Common Mode Return Loss ≥ 6dB (measured within a 50MHz~1.25GHz range)•Differential Impedance should be limited from 80 to 120ohms (100ohm recommended)•Only PCB traces are allowed for signal routing (do not use flat/shielded cable)2.2.Differential Signal Layout Guidelines•Keep differential pairs as close as possible and route both traces as identically as possible, meaning width, length, and location•Avoid vias and layer changes if possible•Keep transmit and receive pairs away from each other. Run orthogonally or separate by a ground plane if possible•0.1µF common mode noise filter capacitors should be placed near the RTL8111E chip•Ninety-degree trace angles should be avoided. We recommend that the traces turn at 45° angles as shown in Figure 1. Sharp edges may add unexpected parasitic effects into the circuitry. Reducing the trace length will reduce trace inductance during quick energy burstsA BA BBetterBadFigure 1. Signal Trace AnglesIntegrated Gigabit Ethernet Controller for PCI Express Applications 5Track ID: JATR-2265-11 Rev. 1.32.3.Placing the RTL8111E•The RTL8111E should be placed as close as possible to the magnetics2.4.Magnetics•The 10/100/1000M magnetics should be placed as close as possible to the RJ-45 connector•The magnetics device, or devices with magnetic fields, should be separated and mounted at 90 degrees to each other2.5.Crystal•The Crystal should be placed away from I/O ports, important or high frequency signal traces (Tx, Rx, power), magnetics, and board edges•The outer shield of the Crystal requires good grounding to avoid induction of EMC/EMI•The retaining straps of the OSC, if any, need good grounding2.6.Ferrite Beads and De-Coupling CapacitorsEach PCB design has its unique noise coupling behavior. Ferrite beads are used to suppress power noise. System designers are suggested to provide the option to replace the ferrite beads with 0Ω resistors. Decoupling capacitors should be placed as close as possible to the power pins, such that the distance from the IC power pin to the capacitor is less than 200 mils.Integrated Gigabit Ethernet Controller for PCI Express Applications 6 Track ID: JATR-2265-11 Rev. 1.33. Signal and Trace RoutingNoise, ringing, and data lines should be controlled with proper termination. Power supply pins should be protected by proper filtering techniques. Good routing of traces can reduce propagation delay, crosstalk, and high frequency noise. It will also improve the signal quality to the receiver and reduce transmit signal losses.• Traces routed from the RTL8111E to the 10/100/1000M magnetics, and to the RJ-45 connector, should be as short as possible. The 12cm maximum length between the RTL8111E and magnetics is achievable only when there is no interference. It is also very important to keep all four differential pair signal traces(MDI0+/-, MDI1+/-, MDI2+/-, MDI3+/-) equal in length. The two traces of each pair should be placed close to each other (D1) since they are differential pair signals to each other and provide a strong canceling effect on noise. The width of D1 should be calculated to have 100Ω impedance (Figure 2).Figure 2. Signal & Trace Routing• We suggest that there should be more than 30 mil spacing between different differential pairs tominimize crosstalk coupled from other pairs (D2 in Figure 2). In addition, Ground Plane shielding can be used to separate all four signal pairs. However, a good layout should avoid the following situations: Intersection of any two pairs of signal tracesIntersection of the two signal traces of the same differential pair• To minimize impedance mismatch, we recommend not to use vias on the four differential pairsIntegrated Gigabit Ethernet Controller for PCI Express Applications 7Track ID: JATR-2265-11 Rev. 1.3•Ninety-degree trace corners should be avoided. We recommend that the traces turn at 45° angles as shown in Figure 1 , page 4. Sharp edges may add unexpected parasitic effects into the circuitry.Reducing the trace length will reduce trace inductance during quick energy bursts.•The trace length and the ratio of trace width to trace height above the ground planes should be carefully considered. If running power on the trace is unavoidable, the trace width should be wider than 60 mils, and properly filtered to minimize power noise effects. The clock and other high speed signal traces should be as short and wide as possible (compared to normal digital traces). It is better to have a ground plane under these traces. If possible, use a ground plane to surround them.•It is important to separate Digital Signals (e.g., BOOTROM, Flash, EEPROM) from Analog Signals(e.g., MDI0+/-, MDI1+/-, MDI2+/-, and MDI3+/-, RSET) in order to avoid interference. If it isunavoidable to cross digital signals with analog power, do it at 90° angles.•The power into the RTL8111E digital power pins can be improved with de-coupling capacitors. The Power signal traces (de-coupling cap traces, power traces, grounding traces) should be as short and wide as possible. The vias of the de-coupling capacitor should be large enough in diameter. All analog power pins on the RTL8111E need to be de-coupled with a capacitor. The de-coupling capacitors should be placed as close to the IC as possible and the traces should be kept short.•The PCI-Express signal differential pairs should be 5mils wide, with a spacing of 7mils between them (REFCLK+ & REFCLK-, HSOP & HSON, HSIP & HSIN). The length difference of the signals in a pair should not exceed 5 mils. For example, if HSON is 900 mils and HSOP is 890mils, it may result in data transmit error.Integrated Gigabit Ethernet Controller for PCI Express Applications 8Track ID: JATR-2265-11 Rev. 1.34. Ground and Power Plane Layout4.1. Ground Plane LayoutThere is only one ground plane for analog power (AVDD33), digital power (DVDD33, DVDD10) and PCI-Express power (EVDD10). In the center of the IC, there is an Exposed Pad (EPAD) ground. The size of the center EPAD ground is 4mm x 4mm. The PCB layout requires 9 vias to connect the EPAD to the lower layer ground plane (see Figure 3).Isolated separation between Analog and Digital Ground domains is not recommended since bad ground plane partitioning could cause serious EMI emissions and degrade analog performance due to bouncing noise.Whether there is sufficient space on the PCB for an isolated separation layout must also be taken into consideration. The key point of such a layout is to keep the analog GND return path approximately equal to the common GND. If the system designer is not comfortable doing this, just place a single ground plane with no partition.Figure 3. Ground Plane Layout-1To achieve better ground plane performance, it is recommended to keep the plane as large and uniform as possible. Figure 4 illustrates a not so good (left) and a good ground plane layout (right).Figure 4. Ground Plane Layout-2Integrated Gigabit Ethernet Controller for PCI Express Applications 9Track ID: JATR-2265-11 Rev. 1.3The plane area beneath the magnetics should be left void. The void area is to keep transformer inducednoise away from the power and system ground planes (Figure 5).Figure 5. Ground Plane SeparationThe Chassis Ground as shown in Figure 5 is known as an ‘Isolated Ground’. It connects directly to the RJ-45 connector (fully shielded is recommended). In addition, a 2kV (3kV recommended) high voltage capability capacitor is needed to connect to this chassis ground for ESD protection.It is also important to keep the gap (D in Figure 5) between Chassis GND and System GND wider than 60 mils for better isolation.Integrated Gigabit Ethernet Controller for PCI Express Applications 10Track ID: JATR-2265-11 Rev. 1.34.2. Power Plane LayoutThe digital power plane should be separated from analog areas, which are extremely sensitive to noise. It is recommended to use at least a 4-layer PCB.A low-pass filter combination of a ferrite bead and capacitors should be used to provide a clean, filtered power plane for analog consideration. It is important to avoid using unnecessary power traces to the RTL8111E. If it is unavoidable, try to keep these traces as short and wide as possible and make good use of vias.(a) Decoupled Capacitor ExampleFigure 6. Decoupled Capacitor Example(b) Use a Ferrite Bead or 0 ohm Resistor to Connect Digital and Analog PowerFigure 7. Power PlaneIntegrated Gigabit Ethernet Controller for PCI Express Applications 11Track ID: JATR-2265-11 Rev. 1.3To further improve the performance of the power plane, try to keep the contact area between the RTL8111EVDD pins and power plane as large as possible rather than using small narrow traces (Figure 8).Figure 8. Power Source Distribution• Keep power noise levels below 100mV peak-to-peak in gigabit mode• All 3.3V/1.05V decoupling capacitors shown in the reference schematic should be used in all designs • Keep the analog power (1.05V) plane as whole and as large as possible4.3. Four-Layer Board Plane Layout1. Signal 1 (top layer)2. GND3. Power4. Signal 2 (bottom)Integrated Gigabit Ethernet Controller for PCI Express Applications12Track ID: JATR-2265-11 Rev. 1.34.3.1. Signal 1 Plane Layout (Top Layer)Figure 9. Signal 1 Plane Layout (Top Layer)4.3.2. Ground Plane Layout (Layer 2)Figure 10. Ground Plane Layout (Layer 2)Integrated Gigabit Ethernet Controller for PCI Express Applications13 Track ID: JATR-2265-11 Rev. 1.34.3.3. Power Plane Layout (Layer 3)Figure 11. Power Plane Layout (Layer 3)4.3.4. Signal 2 Plane Layout (Bottom Layer)Figure 12. Signal 2 Plane Layout (Bottom Layer)Integrated Gigabit Ethernet Controller for PCI Express Applications 14Track ID: JATR-2265-11 Rev. 1.35. Center-Tapping•A center-tapped fine-tuned capacitor (C1 Value: 0.4µF~50pF) can improve EMI for single tone noise. The capacitor default is NC • Changing the R1 resistor to a capacitor (Value: 0.4µF~50pF), and fine-tuning the connection to GND can improve EMI for single tone noise. The resistor default is 0 ohmFigure 13. Center-Tapping• When using a separate transformer, the center-tap MUST be aggregated (pins 10, 7, 4, 1) (C26 Value: 0.4µF~50pF) (see Figure 14)Figure 14. Separate TransformerIntegrated Gigabit Ethernet Controller for PCI Express Applications 15Track ID: JATR-2265-11 Rev. 1.36.Switching RegulatorThe RTL8111E incorporates a state-of-the-art switching regulator that requires a well-designed PCB layout in order to achieve good power efficiency and lower the output voltage ripple and input overshoot. Note that the switching regulator 1.05V output pin (REGOUT) must be connected only to DVDD10, AVDD10, and EVDD10 (do not provide this power source to other devices).6.1.Inductor and Capacitor Parts ListTable 1. Inductor and Capacitor Parts ListInductor Type Inductance ESR at 1MHz(mΩ) Max IDC(mA)Variation Output Ripple (mV)GLK2510P-2R2M 2.2µH 791 1000 ≤ 20% (See Figure 18, Figure 19) GLK2510P-4R7M 4.7µH 1745 750 ≤ 20% (See Figure 21, Figure 22) GTSD32P-2R2M 2.2µH 332 1500 ≤ 20% (See Figure 24)Note 1: The ESR is equivalent to RDC or DCR. Lower ESR inductor values will promote a higher efficiency switching regulator.Note 2: The power inductor used by the switching regulator must be able to withstand 600mA of current.Note 3: Typically, if the power inductor’s ESR at 1MHz is below 0.8Ω, the switching regulator efficiency will be above 75%. However the actual switching regulator efficiency should be measured according to the method described in section 6.3 Efficiency Measurement, page 23.Capacitor Type Capacitance ESR at 1MHz (mΩ) Output Ripple (mV)4.7µF 0805 X5R TDK 4.838 40.28 (See Figure 18, Figure 21) 10µF 0603 X5R YAGEO 11.956 58.29 (See Figure 19, Figure 22) 22µF 1206 X5R WISIN 22µF 40.72 (See Figure 20, Figure 23) Note 1: Capacitors (Cin1 & Cin2) are must be ceramic due to their low ESR value. Lower ESR values will yield lower output voltage ripple.Note 2: Only the following combinations of power inductor and capacitor can be used with the RTL8111E.Inductor: 2.2µH, 4.7µH.Capacitor: 4.7µF, 10µF, 22µF.Integrated Gigabit Ethernet Controller for PCI Express Applications 16Track ID: JATR-2265-11 Rev. 1.36.2. Measurement CriteriaIn order for the switching regulator to operate properly, the input and output voltage measurement criteria must be met. From the input side, the voltage overshoot cannot exceed 4V; otherwise the chip may be damaged. Note that the voltage signal must be measured directly at the VDDREG pin, not at the capacitor. In order to reduce the input voltage overshoot, the Cin1 and Cin2 must be placed close to the VDDREG pin. The following figures show what a good input voltage and a bad one look like.Figure 15. Input Voltage Overshoot <4V (Good)Figure 16. Input Voltage Overshoot >4V (Bad)Integrated Gigabit Ethernet Controller for PCI Express Applications 17Track ID: JATR-2265-11 Rev. 1.3From the output side measured at the REGOUT pin, the voltage ripple must be within100mV peak-to-peak. Choosing different types and values of input and output capacitor (Cin1, Cin2; Cout1, Cout2) and power inductor (Lx) will seriously affect the efficiency and output voltage ripple of switching regulators. The following figures show the effects of different types of capacitors on the switching regulator’s output voltage.The blue square wave signal (top row) is measured at the output of the REGOUT pin before the power inductor (Lx). The yellow signal (second row) is measured after the power inductor (Lx), and shows there is a voltage ripple. The green signal (lower row) is the current. Data in the following figures was measured at gigabit speed.Figure 17. Ceramic 10µF 0603 (X5R) (Good)Figure 18. L=GLK2510P-2R2M, C=Ceramic 4.7µF 0805 X5R TDK (Ripple 12.4mV)Integrated Gigabit Ethernet Controller for PCI Express Applications18 Track ID: JATR-2265-11 Rev. 1.3Figure 19. L=GLK2510P-2R2M, C=Ceramic 10µF 0603 X5R YAGEO (Ripple 13.2mV)Figure 20. L=GLK2510P-2R2M, C=Ceramic 22µF 1206 X5R WISIN (Ripple 10.4mV)Integrated Gigabit Ethernet Controller for PCI Express Applications19 Track ID: JATR-2265-11 Rev. 1.3Figure 21. L=GLK2510P-4R7M, C=Ceramic 4.7µF 0805 X5R TDK (Ripple 12mV)Figure 22. L=GLK2510P-4R7M, C=Ceramic 10µF 0603 X5R YAGEO (Ripple 11.2mV)Integrated Gigabit Ethernet Controller for PCI Express Applications20 Track ID: JATR-2265-11 Rev. 1.3Figure 23. L=GLK2510P-4R7M, C=Ceramic 22µF 1206 X5R WISIN (Ripple 9.2mV)Figure 24. L=GTSD32P-2R2M, C=Ceramic 4.7µF 0805 X5R TDK (Ripple 9.2mV)Integrated Gigabit Ethernet Controller for PCI Express Applications 21 Track ID: JATR-2265-11 Rev. 1.3Figure 25. Ceramic 10µF (Y5V) (Bad)A ceramic 10µF (X5R) will have a lower voltage ripple compared to an electrolytic 100µF. The key to choosing a proper output capacitor is to choose the lowest ESR to reduce the output voltage ripple. Choosing a ceramic 10µF (Y5V) in this case will cause malfunction of the switching regulator. Placing several Electrolytic capacitors in parallel will help lower the output voltage ripple.Figure 26. Electrolytic 100µF (Ripple Too High)Integrated Gigabit Ethernet Controller for PCI Express Applications 22Track ID: JATR-2265-11 Rev. 1.3The following figures show how different inductors affect the REGOUT pin output waveform. The typical waveform should look like Figure 27, which has a square waveform with a dip at the falling edge and the rising edge. If the inductor is not carefully chosen, the waveform may look like Figure 28, where the waveform looks like a distorted square. This will cause insufficient current supply and will undermine the stability of the system at gigabit speed. Data in the following figures was measured at gigabit speed.Figure 27. GTSD32P-2R2M (Good)Figure 28. 1µH Bead (Bad)Integrated Gigabit Ethernet Controller for PCI Express Applications 23Track ID: JATR-2265-11 Rev. 1.36.3.Efficiency MeasurementThe efficiency of the switching regulator is designed to be above 75% in gigabit traffic mode. It is very important to choose a suitable inductor before Gerber certification, as the Inductor ESR value will affect the efficiency of the switching regulator. An inductor with a lower ESR value will result in a higher efficiency switching regulator.The efficiency of the switching regulator is easily measured using the following method.Figure 29, page 24, shows two checkpoints, checkpoint A (CP_A) and checkpoint B (CP_B). The switching regulator input current (Icpa) should be measured at CP_A, and the switching regulator output current (Icpb) should be measured at CP_B.To determine efficiency, apply the following formula:Efficiency = Vcpb*Icpb / Vcpa*IcpaWhere Vcpb is 1.05V; Vcpa is 3.3V. The measurements should be performed in gigabit traffic mode.For example: The inductor used in the evaluation board is a GOTREND GTSD32-4R7M:•The ESR value @ 1MHz is approximately 0.712ohm•The measured Icpa is 101mA at CP_A•The measured Icpb is 263mA at CP_BThese values are measured in gigabit traffic mode, so the efficiency of the GOTREND GTSD32-4R7M can be calculated as follows:Efficiency = (1.05V*263mA) / (3.3V*101mA) = 0.823 = 82.3%.We strongly recommend that when choosing an inductor for the switching regulator, the efficiency should be measured, and that the inductor should yield an efficiency rating higher than 75%. If the efficiency does not meet this requirement, there may be risk to the switching regulator reliability in the long run.。
