CD74AC32M96G4中文资料

MultiMediaCard SpecificationVersion : Ver. 0.9Date 4 – June - 2004Samsung Electronics Co., LTDSemiconductor Flash Memory Product Planning & Applications1 Introduction to the MultiMediaCard ----------------------------------------------------------- 51.1 System Features ----------------------------------------------------------------------------------------- 5-------------------------------------------------------------------------------------- 51.2 ProductModel2 Function Description ------------------------------------------------------------------------------- 72.1 Flash Technology Independence ------------------------------------------------------------------ 72.2 Defect and Error Management --------------------------------------------------------------------- 72.3 Endurance ----------------------------------------------------------------------------------------------- 72.4 Automatic Sleep Mode ------------------------------------------------------------------------------- 72.5 Hot Insertion -------------------------------------------------------------------------------------------- 82.6 MultiMediaCard Mode -------------------------------------------------------------------------------- 82.6.1 MultiMediaCard Standard Compliance ----------------------------------------------------------- 82.6.2 Negotiation Operation Conditions ----------------------------------------------------------------- 82.6.3 Card Acquisition and Identification ---------------------------------------------------------------- 82.6.4 Card Status ---------------------------------------------------------------------------------------------- 82.6.5 Memory Array Partitioning --------------------------------------------------------------------------- 92.6.6 Read and Write Operations ------------------------------------------------------------------------- 92.6.7 Data Transfer Rate ------------------------------------------------------------------------------------102.6.8 Data Protection in the Flash Card -----------------------------------------------------------------10-----------------------------------------------------------------------------------------------------10 2.6.9 Erase2.6.10 Write Protection ----------------------------------------------------------------------------------------102.6.11 Copy Bit ------------------------------------------------------------------------------------------------- 102.6.12 The CSD Register ------------------------------------------------------------------------------------ 112.7 SPI Mode ----------------------------------------------------------------------------------------------- 112.7.1 Negotiating Operation Conditions ---------------------------------------------------------------- 112.7.2 Card Acquisition and Identification --------------------------------------------------------------- 112.7.3 Card Status --------------------------------------------------------------------------------------------- 112.7.4 Memory Array Partitioning -------------------------------------------------------------------------- 112.7.5 Read and Write Operations ------------------------------------------------------------------------- 112.7.6 Data Transfer Rate ------------------------------------------------------------------------------------ 112.7.7 Data Protection in the MultiMediaCard ----------------------------------------------------------- 1212-----------------------------------------------------------------------------------------------------2.7.8 Erase2.7.9 Write Protection ---------------------------------------------------------------------------------------- 123 Product Specifications ----------------------------------------------------------------------------- 133.1 Recommended Operating Conditions ------------------------------------------------------------------------- 133.2 Operating Characteristis ----------------------------------------------------------------- 143.3 System Environmental Specifications ----------------------------------------------------------------- 153.4 System Reliability and Maintenance -------------------------------------------------------------- 153.5 Physical Specifications ------------------------------------------------------------------------------- 164 MultiMediaCard Interface Description --------------------------------------------------------- 174.1 Pin Assignments in MultiMediaCard Mode ------------------------------------------------------- 174.2 Pin Assignments in SPI Mode ---------------------------------------------------------------------- 184.3 MultiMediaCard Bus Topology ---------------------------------------------------------------------- 184.4 SPI Bus Topology -------------------------------------------------------------------------------------------------- 194.4.1 SPI Interface Concept ------------------------------------------------------------------------------------------- 194.4.2 SPI Bus Topology ------------------------------------------------------------------------------------------------ 1920------------------------------------------------------------------------------------------------- 4.5 Registers4.5.1 Operation Condition Register (OCR) ---------------------------------------------------------------------------204.5.2 Card Identification (CID) ------------------------------------------------------------------------------214.5.3 Relative Card Address (RCA) ----------------------------------------------------------------------- 21 4.5.4 Card Specific Data (CSD) ---------------------------------------------------------------------------- 22 4.6 MultiMediaCard Communication -------------------------------------------------------------------- 3030----------------------------------------------------------------------------------------------- 4.6.1 Commands4.7 Read, Write and Erase Time-out Conditions ----------------------------------------------------- 33 4.8 Card Identification Mode ------------------------------------------------------------------------------ 34 4.8.1 Operating Voltage Range Validation --------------------------------------------------------------- 35 4.9 Data Transfer Mode ------------------------------------------------------------------------------------ 35 4.9.1 Block Read ----------------------------------------------------------------------------------------------- 37 4.9.2 Block Write ----------------------------------------------------------------------------------------------- 3738------------------------------------------------------------------------------------------------------ 4.9.3 Erase4.9.4 Write Protect Management -------------------------------------------------------------------------- 38 4.9.5 Card Lock/Unlock Operation ------------------------------------------------------------------------ 38----------------------------------------------------------------------------------------------- 41 4.9.6 Responses4.9.7 Status ------------------------------------------------------------------------------------------------------ 42 4.9.8 Command Response Timing ------------------------------------------------------------------------ 4448 4.9.9 Reset------------------------------------------------------------------------------------------------------ 4.10 SPI Communication ----------------------------------------------------------------------------------- 49 4.10.1 Mode Selection ----------------------------------------------------------------------------------------- 49 4.10.2 Bus Transfer Protection ------------------------------------------------------------------------------ 49 4.10.3 Data Read Overview ---------------------------------------------------------------------------------- 50 4.10.4 Data Write Overview ---------------------------------------------------------------------------------- 51 4.10.5 Erase and Write Protect Management ----------------------------------------------------------- 52 4.10.6 Reading CID/CSD Registers ------------------------------------------------------------------------ 53 4.10.7 Reset Sequence --------------------------------------------------------------------------------------- 53 4.10.8 Error Conditions ---------------------------------------------------------------------------------------- 53 4.10.9 Memory Array Partitioning --------------------------------------------------------------------------- 53 4.10.10 Card Lock/Unlock -------------------------------------------------------------------------------------- 53 4.10.11 Commands ----------------------------------------------------------------------------------------------- 54 4.10.12 Responses ----------------------------------------------------------------------------------------------- 56 4.10.13 Data Tokens --------------------------------------------------------------------------------------------- 58 4.10.14 Data Error Token --------------------------------------------------------------------------------------- 59 4.10.15 Clearing Status Bits ------------------------------------------------------------------------------------ 60 4.11 SPI Bus Timing ----------------------------------------------------------------------------------------- 61 4.12 Error Handling ------------------------------------------------------------------------------------------ 64 4.12.1 Error Correction Code (ECC) ----------------------------------------------------------------------- 64 4.12.2 Cyclic Redundancy Check (CRC) ----------------------------------------------------------------- 642 Function Description2.1 Flash Technology IndependenceThe 512 byte sector size of the MultiMediaCard is the same as that in an IDE magnetic disk drive. To write or read a sector (or multiple sectors), the host computer software simply issues a Read or Write command to the MultiMediaCard. This command contains the address and the number of sectors to write/read. The host software then waits for the command to complete. The host software does not get involved in the details of how the flash memory is erased, programmed or read. This is extremely important as flash devices are expected to get more and more complex in the future. Because the MultiMediaCard uses an intelligent on-board controller, the host system software will not require changing as new flash memory evolves. In other words, systems that support the MultiMediaCard today will be able to access future MultiMediaCards built with new flash technology without having to update or change host software.2.2 Defect and Error ManagementMultiMediaCards contain a sophisticated defect and error management system. This system is analogous to the systems found in magnetic disk drives and in many cases offers enhancements. For instance, disk drives do not typically perform a read after write to confirm the data is written correctly because of the performance penalty that would be incurred. MultiMediaCards do a read after write under margin conditions to verify that the data is written correctly (except in the case of a Write without Erase Command). In the rare case that a bit is found to be defective, MultiMediaCards replace this bad bit with a spare bit within the sector header. If necessary, MultiMediaCards will even replace the entire sector with a spare sector. This is completely transparent to the host and does not consume any user data space.The MultiMediaCards soft error rate specification is much better than the magnetic disk drive specification. In the extremely rare case a read error does occur, MultiMediaCards have innovative algorithms to recover the data. This is similar to using retries on a disk drive but is much more sophisticated. The last line of defense is to employ powerful ECC to correct the data. If ECC is used to recover data, defective bits are replaced with spare bits to ensure they do not cause any future problems.These defect and error management systems coupled with the solid-state construction give MultiMediaCards unparalleled reliability2.3 EnduranceMultiMediaCards have an endurance specification for each sector of 1,000,000 writes (reading a logical sector is unlimited). This is far beyond what is needed in nearly all applications of MultiMediaCards. Even very heavy use of the MultiMediaCard in cellular phones, personal communicators, pagers and voice recorders will use only a fraction of the total endurance over the typical device’s five year lifetime. For instance, it would take over 100 years to wear out an area on the MultiMediaCard on which a files of any size (from 512 bytes to capacity) was rewritten 3 times per hour, 8 hours a day, 365 days per year.With typical applications the endurance limit is not of any practical concern to the vast majority of users.2.4 Automatic Sleep ModeAn important feature of the MultiMediaCard is automatic entrance and exit from sleep mode. Upon completion of an operation, the MultiMediaCard will enter the sleep mode to conserve power if no further commands are received within 5 msec The host does not have to take any action for this to occur. In most systems, the MultiMediaCard is in sleep mode except when the host is accessing it, thus conserving power. When the host is ready to access the MultiMediaCard and it is in sleep mode, any command issued to the MultiMediaCard will cause it to exit sleep and respond. The host does not have to issue a reset first. It may do this if desired, but it is not needed. By not issuing the reset, performance is improved through the reduction of overhead.2.5 Hot InsertionSupport for hot insertion will be required on the host but will be supported through the connector. Connector manufacturers will provide connectors that have power pins long enough to be powered before contact is made with the other pins. Please see connector data sheets for more details. This approach is similar to that used in PCMCIA to allow for hot insertion. This applies to both MultiMediaCard and SPI modes.2.6 MultiMediaCard Mode2.6.1 MultiMediaCard Standard ComplianceThe MultiMediaCard is fully compliant with MultiMediaCard standard specification V3.31.The structure of the Card Specific Data (CSD) register is compliant with CSD structure V1.2.2.6.2 Negotiating Operation ConditionsThe MultiMediaCard supports the operation condition verification sequence defined in the MultiMediaCard standard specifications. The MultiMediaCard host should define an operating voltage range that is not supported by the MultiMediaCard. It will put itself in an inactive state and ignore any bus communication. The only way to get the card out of the inactive state is by powering it down and up again. In addition the host can explicitly send the card to the inactive state by using the GO_INACTIVE_STATE command.2.6.3 Card Acquisition and IdentificationThe MultiMediaCard bus is a single master (MultiMediaCard host) and multi-slaves (cards) bus. The host can query the bus and find out how many cards of which type are currently connected. The MultiMediaCard’s CID register is pre-programmed with a unique card identification number which is used during the acquisition and identification procedureIn addition, the MultiMediaCard host can read the card’s CID register using the READ_CID MultiMediaCard command. The CID register is programmed during the MultiMediaCard testing and formatting procedure, on the manufacturing floor. The MultiMediaCard host can only read this register and not write to it.2.6.4 Card StatusMultiMediaCard status is stored in a 32 bit status register which is sent as the data field in the card respond to host commands. Status register provides information about the card’s current state and completion codes for the last host command. The card status can be explicitly read (polled) with the SEND_STATUS command.2.6.7 Data Protection in the Flash CardEvery sector is protected with an Error Correction Code (ECC). The ECC is generated (in the memory card) when the sectors are written and validated when the data is read. If defects are found, the data is corrected prior to transmission to the host.The MultiMediaCard can be considered error free and no additional data protection is needed. However, if an application uses additional, external, ECC protection, the data organization is defined in the user writeable section of the CSD register2.6.8 EraseThe smallest erasable unit in the MultiMediaCard is a erase group. In order to speed up the erase procedure, multiple erase groups can be erased in the same time. The erase operation is divided into two stages.Tagging - Selecting the Sectors for ErasingTo facilitate selection, a first command with the starting address is followed by a second command with the final address, and all erase groups within this range will be selected for erase.Erasing - Starting the Erase ProcessTagging can address erase groups. An arbitrary selection of erase groups may be erased at one time. Tagging and erasing must follow a strict command sequence (refer to the MultiMediaCard standard specification for details).2.6.9 Write ProtectionThe MultiMediaCard erase groups are grouped into write protection groups. Commands are provided for limiting and enabling write and erase privileges for each group individually. The current write protect map can be read using SEND_WRITE_PROT command.In addition two, permanent and temporary, card levels write protection options are available.Both can be set using the PROGRAM_CSD command (see below). The permanent write protect bit, once set, cannot be cleared.The One Time Programmable (OTP) characteristic of the permanent write protect bit is implemented in the MultiMediaCard controller firmware and not with a physical OTP cell.2.6.10 Copy BitThe content of an MultiMediaCard can be marked as an original or a copy using the copy bit in the CSD register. Once the Copy bit is set (marked as a copy) it cannot be cleared.The Copy bit of the MultiMediaCard is programmed (during test and formatting on the manufacturing floor) as a copy. The MultiMediaCard can be purchased with the copy bit set (copy) or cleared, indicating the card is a master.The One Time Programmable (OTP) characteristic of the Copy bit is implemented in the MultiMediaCard controller firmware and not with a physical OTP cell.2.6.11 The CSD RegisterAll the configuration information of the MultiMediaCard is stored in the CSD register. The MSB bytes of the register contain manufacturer data and the two least significant bytes contains the host controlled data - the card Copy and write protection and the user ECC register.The host can read the CSD register and alter the host controlled data bytes using the SEND_CSD and PROGRAM_CSD commands.2.7 SPI ModeThe SPI mode is a secondary (optional) communication protocol offered for MultiMediaCard. This mode is a subset of the MultiMediaCard protocol, designed to communicate with an SPI channel, commonly found in Motorola’s (and lately a few other vendors’) microcontrollers.2.7.1 Negotiating Operation ConditionsThe operating condition negotiation function of the MultiMediaCard bus is not supported in SPI mode. The host must work within the valid voltage range (2.7 to 3.6 volts) of the card.2.7.2 Card Acquisition and IdentificationThe card acquisition and identification function of the MultiMediaCard bus is not supported in SPI mode. The host must know the number of cards currently connected on the bus. Specific card selection is done via the CS signal.2.7.3 Card StatusIn SPI mode only 16 bits (containing the errors relevant to SPI mode) can be read out of the MultiMediaCard status register.2.7.4 Memory Array PartitioningMemory partitioning in SPI mode is equivalent to MultiMediaCard mode. All read and write commands are byte addressable.2.7.5 Read and Write OperationsIn SPI mode, only single block read/write mode is supported.2.7.6 Data Transfer RateIn SPI mode only block mode is supported. The typical access time (latency) for each data block, in read operation, is 1.5mS. The write typical access time (latency) for each data block, in read operation, is 1.5mS. The write block operation is done in handshake mode. The card will keep DataOut line low as long as the write operation is in progress and there are no write buffers available.2.7.7 Data Protection in the MultiMediaCardSame as for the MultiMediaCard mode.2.7.8 EraseSame as in MultiMediaCard mode2.7.9 Write ProtectionSame as in MultiMediaCard modeFigure 3-1 Timing Diagram of Data Input and Output3.5 Physical SpecificationsDimensions of Normal MMC(24mm x 32mm x 1.4mm)Dimensions of RS-MMC(24mm x 18mm x 1.4mm)rising and falling edges). If the host does not allow the switchable R OD implementation, a fix R CMD can be used. Consequently the maximum operating implementation, a fix R CMD can be used. Consequently the maximum operating frequency in the open drain mode has to be reduced in this case.4.4 SPI Bus Topology4.4.1 SPI Interface ConceptThe Serial Peripheral Interface (SPI) is a general-purpose synchronous serial interface originally found on certain Motorola micro-controllers. The MultiMediaCard SPI interface is compatible with SPI hosts available on the market. As any other SPI device the MultiMediaCard SPI channel consists of the following 4 signals:- CS : Host to card chip select signal- CLK : Host to card clock signal- DataIn : Host to card data signal- DataOut : Card to host data signalAnother SPI common characteristic, which is implemented in the MultiMediaCard card as well, is byte transfers. All data tokens are multiples of 8 bit bytes and always byte aligned to the CS signal. The SPI standard defines the physical link only and not the complete data transfer protocol. The MultiMediaCard uses a subset of the MultiMediaCard protocol and command set.4.4.2 SPI Bus TopologyThe MultiMediaCard card identification and addressing algorithms are replaced by hardware Chip Select (CS) signal. There are no broadcast commands. A card (slave) is selected, for every command, by asserting (active low) the CS signal (see Figure 4-3). The CS signal bust is continuously active for the duration of the SPI transaction (command, response and data). The only exception is card-programming time. At this time the host can de-assert the CS signal without affecting the programming process. The bi-directional CMD and DAT lines are replaced by unidirectional dataIn and dataOut signals. This eliminates the ability of executing commands while data is being read or written and, therefore, eliminates the sequential and multi block read/write operations. The SPI channel supports only single block read/write.Figure 4-3 SPI Bus SystemReadThe read access time is defined as the sum of the two times given by the CSD parameters TAAC and NSAC (refer to Table “Card Specific Data (CSD)”). These card parameters define the typical delay between the end bit of the read command and the start bit of the data block. This number is card dependent and should be used by the host to calculate throughput and the maximal frequency for stream read.WriteThe R2W_FACTOR field in the CSD is used to calculate the typical block program time obtained by multiplying the read access time by this factor. It applies to all write/erase commands (e.g. SET(CLEAR)_WRITE_PROTECT, PROGRAM_CSD(CID) and the block write commands). It should be used by the host to calculate throughput.EraseThe duration of an erase command will be (order of magnitude) the number of sectors to be erased multiplied by the block write delay.4.8 Card Identification ModeAll the data communication in the card identification mode uses only the command line (CMD). MultiMediaCard State Diagram (Card Identification Mode)Figure 4-2 MultiMediaCard State Diagram (Card Identification Mode)The host starts the card identification process in open drain mode with the identification clock rate f OD(generated by a push pull driver stage). The open drain driver stages on the CMD line allow the parallel card operation during card identification. After the bus is activated the host will request the cards to send their valid operation conditions with the command SEND_OP_COND (CMD1). Since the bus is in open drain mode, as long as there is more than one card with operating conditions restrictions, the host gets in the response to the CMD1 a “wired or” operation condition restrictions of those cards. The host then must pick a common denominator for operation and notify the application that cards with out of range parameters (from the host perspective) are connected to the bus. Incompatible cards go into Inactive State (refer to also Chapter “Operating Voltage Range Validation”). The busy bit in the CMD1 response can be used by a card to tell the host that it is still working on its power-up/reset procedure (e.g. downloading the register information from memory field) and is not ready yet for communication. In this case the host must repeat CMD1 until the busy bit is cleared. After an operating mode is established, the host asks all cards for their unique card identification (CID) number with the broadcast command ALL_SEND_CID (CMD2).All not already identified cards (i.e. those which are in Ready State) simultaneously start sending their CID numbers serially, while bit-wise monitoring their outgoing bitstream. Those cards, whose outgoing CID bits do not match the corresponding bits on the command line in any one of the bit periods, stop sending their CID immediately and must wait for the next identification cycle (cards stay in the Ready State). There should be only one card which successfully sends its full CID-number to the host. This card then goes into the Identification State. The host assigns to this card (using CMD3, SET_RELATIVE_ADDR) a relative card address (RCA, shorter than CID), which will be used to address the card in future communication (faster than with the CID). Once the RCA is received the card transfers to the Standby State and does not react to further identification cycles. The card also switches the output drivers from the open-drain to the push-pull mode in this state. The host repeats the identification process as long as it receives a response (CID) to its identification command (CMD2). When no card responds to this command, all cards have been identified. The time-out condition to recognize this, is waiting for the start bit for more than 5 clock periods after sending CMD24.8.1 Operating Voltage Range ValidationThe MultiMediaCard standards operating range validation is intended to support reduced voltage range MultiMediaCards. The MultiMediaCard supports the range of 2.7 V to 3.6V supply voltage. So the MultiMediaCard sends a R3 response to CMD1 which contains an OCR value of 0x80FF8000 if the busy flag is set to “ready” or 0x00FF8000 if the busy flag is active (refer to Chapter “Responses”). By omitting the voltage range in the command, the host can query the card stack and determine the common voltage range before sending out-of-range cards into the Inactive State. This bus query should be used if the host is able to select a common voltage range or if a notification to the application of non usable cards in the stack is desired. Afterwards, the host must choose a voltage for operation and reissue CMD1 with this condition sending incompatible cards into the Inactive State.4.9 Data Transfer ModeWhen in Standby State, both CMD and DAT lines are in the push-pull mode. As long as the content of all CSD registers is not known, the f PushPull clock rate is equal to the slow f OpenDrain clock rate. SEND_CSD (CMD9) allows the host to get the Card Specific Data (CSD register), e.g. ECC type, block length, card storage capacity, maximum clock rate etc..。

Advance Information128KB/256KB Secondary CacheModuleWith Tag, Valid, and Dirty for i486Processor SystemsThis family of cache modules is well suited to provide the secondary cache forthe Intel 82420 PCI chipset. This family provides the 128K Byte and 256K Bytecache sizes with valid, dirty and a choice of 7, 8, or 9 tag bits. The tag/valid bitshave 12 ns access times for zero wait states at 33 MHz clock speeds. The PDpins map into the configuration register of the 82420 for auto–configuration of thecache controller during system startup.•Low Profile Edge Connector: Burndy Part Number: CELP2X56SC3Z48•Single 5 V ±10% Power Supply•All Inputs and Outputs are TTL Compatible•Three State Outputs•Fast Module Cycle Time: Up to External Processor Bus Speed of 33 MHz•Cache Byte Write, Bank Chip Enable, Bank Output Enable•Decoupling Capacitors are Used for Each Fast Static RAM•High Quality Multi–Layer FR4 PWB With Separate Power and Ground PlanesBurstRAM is a registered trademark of Motorola.I486 is a registered trademark Intel Corp.This document contains information on a new product. Specifications and information herein are subject to change without notice.Order this document by MCM32A732/DMOTOROLASEMICONDUCTOR TECHNICAL DATAMCM32A732MCM32A832MCM32A932MCM32A764MCM32A864MCM32A964 REV 1ORDERING INFORMATION(Order by Full Part Number)Motorola Memory Prefix Part Number (x = T Package (SG = Gold Pad SIMM)Speed (33 = 33 MHz)32Ax32Full Part Numbers —MCM32A732SG33MCM32A764SG33MCM32A832SG33MCM32A864SG33MCM32A932SG33MCM32A964SG33Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.Literature Distribution Centers:USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan.ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM32A732/764•MCM32A832/86412。

Standard EEPROM ICs SLx 24C3232 Kbit (4096 × 8 bit)Serial CMOS-EEPROM withI2C Synchronous 2-Wire BusData Sheet1999-02-02Edition 1999-02-02Published by Siemens AG,Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73,81541 München© Siemens AG 1999.All Rights Reserved.Attention please!As far as patents or other rights of third par-ties are concerned, liability is only assumed for components, not for applications, pro-cesses and circuits implemented within components or assemblies.The information describes the type of component and shall not be considered as assured characteristics.Terms of delivery and rights to change design reserved.For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list).Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group.Siemens AG is an approved CECC manufacturer.PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG.1 A critical component is a component usedin a life-support device or system whose failure can reasonably be expected tocause the failure of that life-supportdevice or system, or to affect its safety or effectiveness of that device or system.2Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintainand sustain human life. If they fail, it isreasonable to assume that the health of the user may be endangered.Page Protection Mode™ is a trademark of Siemens AG.I 2C BusPurchase of Siemens I 2C components conveys the license under the Philips I 2C patent to use the components in the I 2C system provided the system conforms to the I 2C specifications defined by Philips.SLx 24C32Revision History: Current Version: 1999-02-02Previous Version:02.98, 04.98, 07.98Page (in previous Version)Page (in current Version)Subjects (major changes since last revision)Changes in the complete document P-DIP-8-4 changed to P-DIP-8-3, P-DSO-8-3 changed to P-DSO-8-2.34Text changed to “Typical programming time 5ms for up to 32bytes”.45SLA 24C32-D-3, SLA 24C32-D-3/P, SLA 24C32-S-3 and SLA 24C32-S-3/P deleted.45Voltage changed from 4.5 V...5.5 V to 2.7 V...5.5 V.45Text “3V types with automotive temperature range (–40°C …+125°C)” deleted.45Package (TSSOP, die, wafer delivery) added.67Footnote added “Values are temperature ….”67Text changed to “The device with a voltage range of 2.7…5.5.V isavailable …”.11, 1213, 15The erase/write cycle is finished latest after 108ms.1415Text added “(see figure 10)”.1819Figure 13: “CSW” changed to “CSR”.2123The write or erase cycle is finished latest after 10 4ms.2223Figure 17: “ACK” deleted before “STOP”.2224Line “Supply voltage”: Text deleted.2324Supply current (write) 3 mA 1 mA.2324Line added “Supply current (read)”.2426The line “erase/write cycle” removed.2426Chapter 8.4 “Erase and Write Characteristics” added.32 Kbit (4096 × 8 bit) Serial CMOSEEPROMs, I 2C Synchronous 2-Wire BusSLx 24C321Overview 1.1Features•Data EEPROM internally organized as 4096 bytes and 128 pages × 32 bytes •Page Protection Mode for protecting the EEPROM against unintended data changes (SLx 24C32.../P types only)•Low power CMOS•V CC = 2.7 to 5.5 V operation•Two wire serial interface bus, I 2C-Bus compatible •Three chip select pins to address 8 devices •Filtered inputs for noise suppression with Schmitt trigger•Clock frequency up to 400 kHz •High programming flexibility –Internal programming voltage–Self timed programming cycle including erase –Byte-write and page-write programming, between 1 and 32 bytes–Typical programming time 5ms for up to 32bytes •High reliability–Endurance 106 cycles 1)–Data retention 40 years 1)–ESD protection 4000 V on all pins •8 pin DIP/DSO packages•Available for extended temperature ranges –Industrial:− 40 °C to + 85 °C –Automotive:− 40°C to + 125 °C1)Values are temperature dependent, for further information please refer to your Siemens sales office.Ordering Information Other types are available on request:–Temperature range (– 55 °C … + 150 °C)–Package (TSSOP, die, wafer delivery)1.2Pin ConfigurationFigure 1Pin Configuration (top view)TypeOrdering Code Package Temperature Voltage SLA 24C32-D SLA 24C32-D/P Q67100-H3746Q67100-H3752P-DIP-8-3– 40 °C … + 85 °C 2.7 V...5.5 V SLA 24C32-S SLA 24C32-S/P Q67100-H3748Q67100-H3753P-DSO-8-2– 40 °C … + 85 °C2.7 V...5.5 VSLE 24C32-D SLE 24C32-D/P Q67100-H3235Q67100-H3755P-DIP-8-3– 40°C … + 125 °C 2.7 V...5.5 V SLE 24C32-S SLE 24C32-S/PQ67100-H3236Q67100-H3756P-DSO-8-2– 40°C … + 125 °C 2.7 V...5.5 VPin Definitions and Functions Pin Description Serial Clock (SCL)The SCL input is used to clock data into the device on the rising edge and to clock data out of the device on the falling edge.Serial Data (SDA)SDA is a bidirectional pin used to transfer addresses, data or control information into the device or to transfer data out of the device. The output is open drain, performing a wired AND function with any number of other open drain or open collector devices. The SDA bus requires a pull-up resistor to V CC . Chip Select (CS0, CS1, CS2)The CS0, CS1 and CS2 pins are chip select inputs either hard wired or actively driven to V CC or V SS . These inputs allow the selection of one of eight possible devices sharing a common bus.Write Protection (WP)WP switched to V SS allows normal read/write operations.WP switched to V CC protects the EEPROM against changes (hardware write protection).Table 1Pin No.Symbol Function 1, 2, 3CS0, CS1, CS2Chip select inputs 4V SSGround5SDA Serial bidirectional data bus 6SCL Serial clock input 7WPWrite protection input 8V CCSupply voltage2DescriptionThe SLx 24C32 device is a serial electrically erasable and programmable read only memory (EEPROM), organized as 4096 × 8 bit. The data memory is divided into 128pages. The 32 bytes of a page can be programmed simultaneously.The device conforms to the specification of the 2-wire serial I2C-Bus. Three chip select pins allow the addressing of 8 devices on the I2C-Bus. Low voltage design permits operation down to 2.7 V with low active and standby currents. All devices have a minimum endurance of 106 erase/write cycles1).The device operates at 5.0V ± 10% with a maximum clock frequency of 400kHz and at 2.7 ... 5.5V with a maximum clock frequency of 100kHz. The device with a voltage range of 2.7…5.5.V is available in two temperature ranges for industrial and automotive applications. The EEPROMs are mounted in eight-pin DIP and DSO packages or are also supplied as chips.1)Values are temperature dependent, for further information please refer to your Siemens Sales office.Figure 2Block Diagram3I2C-Bus CharacteristicsAccess to the SLx 24C32 device is given via the I2C bus. This bidirectional bus consists of two wires SCL and SDA for clock and data. The protocol is master/slave oriented, where the serial EEPROM always takes the role of a slave.Figure 3Bus ConfigurationMaster Device that initiates the transfer of data and provides the clock for transmit and receive operations.Slave Device addressed by the master, capable of receiving and transmitting data.Transmitter The device using the SDA as output is defined as the transmitter. Due to the open drain characteristic of the SDA output the device applying a lowlevel wins.Receiver The device using the SDA as input is defined as the receiver.The conventions for the serial clock line and the bidirectional data line are shown in figure4.Figure 4I2C-Bus Timing Conventions for START Condition, STOP Condition, Data Validation and Transfer of Acknowledge ACKStandby Mode in which the bus is not busy (no serial transmission, noprogramming): both clock (SCL) and data line (SDA) are in highstate. The device enters the standby mode after a STOP conditionor after a programming cycle.START Condition High to low transition of SDA when SCL is high, preceding allcommands.STOP Condition Low to high transition of SDA when SCL is high, terminating allcommunications. A STOP condition after writing data initiates anEEPROM programming cycle. A STOP condition after readingdata from the EEPROM initiates the standby mode. Acknowledge A successful reception of eight data bits is indicated by thereceiver by pulling down the SDA line during the following clockcycle of SCL (ACK). The transmitter on the other hand has torelease the SDA line after the transmission of eight data bits.The EEPROM as the receiving device responds with anacknowledge, when addressed. The master, on the other side,acknowledges each data byte transmitted by the EEPROM andcan at any time end a read operation by releasing the SDA line (noACK) followed by a STOP condition.Data Transfer Data must change only during low SCL state, data remains validon the SDA bus during high SCL state. Nine clock pulses arerequired to transfer one data byte, the most significant bit (MSB)is transmitted first.4Device Addressing and EEPROM AddressingAfter a START condition, the master always transmits a command byte CSW or CSR. After the acknowledge of the EEPROM control bytes follow, their contents and the transmitter depend on the previous command byte. The description of the command and control bytes is shown in table 2.Command Byte Selects one of the 8 addressable slave devices: The chip select bits CS2, CS1 and CS0 (bit positions b3 to b1) are compared to theircorresponding hard wired input pins CS2, CS1 and CS0,respectively.Selects operation: the least significant bit b0 is low for a writeoperation (Chip Select Write Command Byte, CSW) or set high fora read operation (Chip Select Read Command Byte, CSR). Control Bytes Following CSW (b0 = 0): The address bytes AHI/ALO containing the address bits A0 to A11 are transmitted by the master.Following CSR (b0 = 1): The EEPROM transmits the read out data.EEPROM data are read as long as the master pulls down SDA aftereach byte in order to acknowledge the transfer. The read operationis stopped by the master by releasing SDA (no acknowledge isapplied) followed by a STOP condition.Table 2Command and Control Byte for I2C-Bus Addressing of Chip and EEPROM Command Definition Functionb7b6b5b4b3b2b1b0CSW1010CS2CS1CS00chip select for write CSR1010CS2CS1CS01chip select for read AHI0000A11A10A9A8high addressALO A7A6A5A4A3A2A1A0low addressDATA D7D6D5D4D3D2D1D0data byteThe device has an internal address counter which points to the current EEPROM address.The address counter is incremented–after a data byte to be written has been acknowledged, during entry of further data byte–during a byte read, thus the address counter points to the following address after reading a data byte.The timing conventions for read and write operations are described in figures5 and 6.Figure 5Timing of the Command Byte CSWFigure 6Timing of the Command Byte CSR5Write OperationsChanging of the EEPROM data is initiated by the master with the command byte CSW.Either one byte (Byte Write) or up to 32 byte (Page Write) are modified in one programming procedure. Setting the Write Protection pin WP to V CC activates the hardware write protection and therefore any programming is suppressed. For normal operation WP has to be set to V SS .5.1Byte WriteFigure 7Byte Write SequenceThe erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for speed enhancement in order to detect the end of the erase/write cycle. Please refer to chapter 5.3, Acknowledge Polling for further information.Address SettingAfter a START condition the master transmits the Chip Select Write byte CSW. The EEPROM acknowledges the CSW byte during the ninth clock cycle. The following two bytes AHI/ALO with the EEPROM address (A0 to A11) are loaded into the address counter of the EEPROM and acknowledged by the EEPROM.Transmission of Data Finally the master transmits the data byte which is also acknowledged by the EEPROM into the internal buffer.Programming CycleThen the master applies a STOP condition which starts the internal programming procedure. The data bytes are written in the memory location addressed in the bytes AHI (A8 to A11)and ALO (A0 to A7). The programming procedure consists of an internally timed erase/write cycle. In the first step, the selected byte is erased to “1”. With the next internal step, the addressed byte is written according to the contents of the buffer.5.2Page WriteAddress Setting The page write procedure is the same as the byte writeprocedure up to the first data byte. In a page write instructionhowever, entry of the EEPROM address bytes AHI/ALO arefollowed by a sequence of one to a maximum of 32 data byteswith the new data to be programmed. These bytes aretransferred to the internal page buffer of the EEPROM. Transmission of Data The first entered data byte will be stored according to theEEPROM address n given by AHI (A8 to A11) and ALO (A0 toA7). The internal address counter is incrementedautomatically after the entered data byte has beenacknowledged. The next data byte is then stored at the nexthigher EEPROM address. EEPROM addresses within thesame page have common page address bits A5 through A11.Only the respective five least significant address bits A0through A4 are incremented, as all data bytes to beprogrammed simultaneously have to be within the same page.Writing over the page border will cause the address counter toroll over to the first address of the page.Programming Cycle The master stops data entry by applying a STOP condition,which also starts the internally timed erase/write cycle. In thefirst step, all selected bytes are erased to “1”. With the nextinternal step, the addressed bytes are written according to thecontents of the page buffer.Those bytes of the page that have not been addressed are not included in the programming.Figure 8Page Write SequenceThe erase/write cycle is finished latest after 8 ms. Acknowledge polling can be used for speed enhancement in order to detect the end of the erase/write cycle. Please refer to chapter5.3, Acknowledge Polling for further information.5.3Acknowledge PollingDuring the erase/write cycle the EEPROM will not respond to a new command byte until the internal write procedure is completed. At the end of active programming the chip returns to the standby mode and the last entered EEPROM byte remains addressed by the address counter. To determine the end of the internal erase/write cycle acknowledge polling can be initiated by the master by sending a START condition followed by a command byte CSR or CSW (read with b0 = 1 or write with b0 = 0). If the internal erase/ write cycle is not completed, the device will not acknowledge the transmission. If the internal erase/write cycle is completed, the device acknowledges the received command byte and the protocol activities can continue (see figure10).Figure 9Flow Chart “Acknowledge Polling”Figure 10Principle of Acknowledge Polling6Read OperationsReading of the EEPROM data is initiated by the Master with the command byte CSR.6.1Random ReadRandom read operations allow the master to access any memory location.Figure 11Random ReadAddress SettingThe master generates a START condition followed by the command byte CSW. The receipt of the CSW-byte is acknowledged by the EEPROM with a low state on the SDA line. Now the master transmits the EEPROM address (AHI/ALO) to the EEPROM and the internal address counter is loaded with the desired address.Transmission of CSRAfter the acknowledge for the EEPROM address is received,the master generates a START condition, which terminates the initiated write operation. Then the master transmits the command byte CSR for read, which is acknowledged by the EEPROM.Transmission of EEPROM DataDuring the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter by one byte.STOP Condition from Master During the following clock cycle the masters releases the bus and then transmits the STOP condition.6.2Current Address ReadThe EEPROM content is read without setting an EEPROM address, in this case the current content of the address counter will be used (e.g. to continue a previous read operation after the Master has served an interrupt).Figure 12Current Address ReadTransmission of CSRFor a current address read the master generates a START condition, which is followed by the command byte CSR (Chip Select Read). The receipt of the CSR-byte is acknowledged by the EEPROM with a low on the SDA line.Transmission of EEPROM DataDuring the next eight clock pulses the EEPROM transmits the data byte and increments the internal address counter by one byte.STOP Condition from Master During the following clock cycle the masters releases the bus and then transmits the STOP condition.6.3Sequential ReadA sequential read is initiated in the same way as a current read or a random read except that the master acknowledges the data byte transmitted by the EEPROM. The EEPROM then continues the data transmission. The internal address counter is incremented by one during each data byte transmission.A sequential read allows the entire memory to be read during one read operation. After the highest addressable memory location is reached, the internal address pointer “rolls over” to the address 0 and the sequential read continues.The transmission is terminated by the master by releasing the SDA line (no acknowledge) and generating a STOP condition (see figure 13).Figure 13Sequential Read7Page Protection Mode TMThe page protection mode is supported by the SLx 24C32.../P types only. For example SLA 24C32-D/P has the same functionality as SLA 24C32-D enhanced by page protection mode.Each page (32 bytes) in the data memory can be protected against unintended data changes by an associated protection bit. The protection bit memory consists of an additional EEPROM of 128 bit (figure 14).Data in the data memory can be modified only if the assigned protection bit is erased (logical state “1”). After writing the data bytes to a page, the protection is achieved by writing the associated protection bit (logical state “0”). Further changes in the data in a protected page is possible only after erasing the protection bit.Figure 14Data Page and Assigned Protection MemoryA special procedure to write or erase a protection bit guarantees proper activation or deactivation of page protection. For protection bit write or erase all 32 data bytes of the respective page have to be entered for verification. The data then are compared internally with the data to be protected. In case of identity the protection bit is written or erased respectively.7.1Protection Bit HandlingThe bits of the protection memory can be addressed directly for reading or programming.A protection bit address corresponds to the lowest address within the respective page (A5to A11, A0 to A4 = zero). The status of each protection bit is sensed internally. A written state (“0”) prevents programming in the associated page. If an already protected memory page is accidentally addressed for programming, the programming procedure is suppressed.The conventional I2C-Bus protocol allows data bytes to be read and programmed only. Therefore an independent instruction sequence for addressing and manipulation of protection bits is implemented. For protection bit instructions the command byte CSW with its preceding START condition followed by the associated address bytes have to be entered twice (figures 15 through17). The first command byte CSW is followed by the address bytes AHI/ALO with the bit/page address A0 through A4 always at zero. The second CSW is required for entering a control byte CTx for protection bit manipulation. The three control bytes for read, write or erase of a protection bit are listed below (table3):Table 3Control Byte for Protection Bit ManipulationAddress NameDefinition Function b7b6b5b4b3b2b1b0CTR x x x x x x00Protection bit read CTW x x x x x x01Protection bit write CTE x x x x x x11Protection bit erase7.2Protection Bit Write and EraseFor writing or erasing a protection bit the data of the respective page have to be known by the master. The master has to present the page data as a reference for comparison by the EEPROM. A successful comparison is necessary in order to change the value of the protection bit.The data of the page are not affected by the write or erase procedure of the protection bit. The I 2C-Bus protocol is shown in figure 15 for protection bit write and figure 16 for protection bit erase.Figure 15Sequence for Protection Bit WriteFigure 16Sequence for Protection Bit EraseThe first command byte CSW followed by the address bytes AHI/ALO determines the page to be protected. The second command byte CSW (identical content of first CSW)is followed by the control byte CTW = 01H for protection bit write or CTE = 03H for protection bit erase. Depending on CTx, the addressed protection bit will be either written or erased.The control byte CTx is followed by 32 parameter bytes identical to the 32 data bytes of the page to be protected or unprotected. The data of the first entered byte must be identical to the data byte stored at the lowest address of the current page. The other31bytes have to be identical to the bytes stored in ascending address order within the same page.A successful verification of each byte is indicated by the EEPROM by pulling the SDA line to low (acknowledge ACK).The bit programming procedure is initiated by the STOP condition after verification of the last byte. Programming is started only if all 256 bits of a page have been verified successfully. If bit programming has taken place, the address counter points to the uppermost address of the respective page. The write or erase cycle is finished latest after 4ms. Acknowledge polling can be used for speed enhancement in order to detect the end of the write or erase cycle (refer to chapter5.3, Acknowledge Polling).7.3Protection Bit ReadThe byte sequence for random bit read is shown in figure 17.Figure 17Byte Sequence for Protection Bit ReadThe first command byte CSW followed by the address bytes AHI/ALO determine the protection bit to be read. The second command byte CSW is followed by the control byte00H for protection bit read. The first bit (MSB) of the transferred byte is the protection bitof the addressed page. The other 7 bits are not valid. The page protection status is indicated as follows:Protection Bit = 1: A normal write operation changes the data in the associated page Protection Bit = 0: The data in the associated page are protected against changes.If the master acknowledges a byte with a low state of the SDA line, the protection bit of the next page can be read as the first bit of the following byte. If the master releases the SDA line, a STOP condition has to complete the read procedure. Any number of bytes with a page protection status at the first bit position can be requested by the master. After the bit of the uppermost page has been addressed an overflow of the address counter occurs and the protection bit of the first page will be read next.8Electrical CharacteristicsThe listed characteristics are ensured over the operating range of the integrated circuit.Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at T A = 25°C and the given supplyvoltage.8.1Absolute Maximum RatingsStresses above those listed here may cause permanent damage to the device. This is astress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this data sheet is not implied.Exposure to absolute maximum ratings for extended periods may affect device reliability.ParameterLimit Values Units Operating temperature range 1 (industrial)range 2 (automotive)– 40 to + 85 – 40 to + 125 °C °C Storage temperature – 65 to + 150 °C Supply voltage– 0.3 to + 7.0 V All inputs and outputs with respect to ground – 0.3 to V CC +0.5V ESD protection (human body model)4000V8.2DC CharacteristicsParameterSymbolLimit ValuesUnits Test Conditionmin.typ.max.Supply voltageV CC2.75.5V Supply current 1) (write)I CC 1mA V CC =5V;f c =100kHz Supply current (read)I CC 0.5mA V CC =5V;f c =100kHzStandby current 2)I SB 1µA Inputs at V CC or V SSInput leakage currentI LI0.11µA V IN =V CC or V SS Output leakage currentI LO 0.11µAV OUT =V CC or V SSInput low voltage V IL– 0.30.3×V CC VInput high voltage V IH 0.7×V CCV CC +0.5VOutput low voltage V OL 0.4V I OL =3 mA; V CC =5VI OL =2.1 mA; V CC =3 V Input/output capacitance (SDA)C I/O83)pFV IN =0V;V CC =5VInputcapacitance (other pins)C IN63)pFV IN =0V;V CC =5V1)The values for I CCare maximum peak values2)Valid over the whole temperature range 3)This parameter is characterized only8.2DC Characteristics (cont’d)Parameter SymbolLimit ValuesUnits Test Conditionmin.typ.max.1)The minimum rise and fall times can be calculated as follows: (20 + (0.1/pF) × C b ) ns Example: C b = 100 pF → t R = (20 + 0.1 × 100) ns = 30 ns8.3AC CharacteristicsParameterSymbolLimit Values V CC = 2.7-5.5 V Limit Values V CC = 4.5-5.5 V Units min.max.min.max.SCL clock frequency f SCL 100400kHz Clock pulse width lowt low 4.7 1.2µs Clock pulse width hight high 4.00.6µsSDA and SCL rise timet R 10001)300ns SDA and SCL fall timet F 3001)300ns Start set-up timet SU.STA 4.70.6µs Start hold timet HD.STA 4.00.6µs Data in set-up timet SU.DAT 200100ns Data in hold timet HD.DAT 00µsSCL low to SDA data out validt AA 0.1 4.50.10.9µs Data out hold timet DH 10050ns Stop set-up timet SU.STO 4.00.6µs Time the bus must be free before a new transmission can start t BUF4.7 1.2µsSDA and SCL spike suppression time at constant inputst l 5010050100ns8.4Erase and Write CharacteristicsParameterSymbolLimit Values V CC = 2.7-5.5 V Limit Values V CC = 4.5-5.5 V Units typ.max.typ.max.Erase + write cycle (per page)t WR5858ms Erase page protection bit 2.54 2.54ms Write page protection bit2.542.54ms。

MC74ACT640Octal 3−State Inverting TranscieverThe MC74ACT640 octal bus transceiver is designed for asynchronous two-way communication between data buses. The device transmits data from bus A to bus B when T/R = HIGH, or from bus B to bus A when T/R = LOW. The enable input can be used to disable the device so the buses are effectively isolated.Features•Bidirectional Data Path•A and B Outputs Sink 24 mA/Source −24 mA•TTL Compatible Inputs•Pb−Free Packages are Available*V OE B B B B B B B BT/R A0A1A2A3A4A5A6A7GNDFigure 1. Pinout: 20−Lead Packages Conductors(Top View)PIN ASSIGNMENTPIN FUNCTIONA0−A7Side A Inputs or 3-State OutputsOE Output Enable InputT/R Transmit/Receive InputB0−B7Side B Inputs or 3-State OutputsTRUTH TABLEOE T/R AppliedInputsValidDirectionI/P→O/P OutputH X X X XL H H A to B LL H L A to B H L L H B to A LL L L B to A H H = HIGH Voltage LevelL = LOW Voltage LevelX = Immaterial*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.See general marking information in the device marking section on page 4 of this data sheet.DEVICE MARKING INFORMATIONMAXIMUM RATINGSSymbol Parameter Value Unit V CC DC Supply Voltage*0.5 to )7.0V V I DC Input Voltage*0.5 v V I v V CC)0.5V V O DC Output Voltage(Note 1)*0.5 v V O v V CC)0.5VI IK DC Input Diode Current$20mAI OK DC Output Diode Current$50mAI O DC Output Sink/Source Current$50mAI CC DC Supply Current per Output Pin$50mAI GND DC Ground Current per Output Pin$50mAT STG Storage Temperature Range*65 to )150_C T L Lead temperature, 1 mm from Case for 10 Seconds260_C T J Junction temperature under Bias)150_Cq JA Thermal resistance PDIPSOIC 6796_C/WP D Power Dissipation in Still Air at 85_C PDIPSOIC 750500mWMSL Moisture Sensitivity Level 1F R Flammability Rating Oxygen Index: 30% − 35%UL 94 V−0 @ 0.125 inV ESD ESD Withstand Voltage Human Body Model (Note 2)Machine Model (Note 3)Charged Device Model (Note 4)> 2000> 200> 1000VI Latchup Latchup Performance Above V CC and Below GND at 85_C (Note 5)$100mA Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.I O absolute maximum rating must be observed.2.Tested to EIA/JESD22−A114−A.3.Tested to EIA/JESD22−A115−A.4.Tested to JESD22−C101−A.5.Tested to EIA/JESD78.RECOMMENDED OPERATING CONDITIONSSymbol Parameter Min Typ Max Unit V CC DC Input Voltage (Referenced to GND) 4.5 5.5V V in, V out DC Input Voltage, Output Voltage (Referenced to GND)0V CC V T A Operating Temperature, All Package Types−4025+85°Ct r, t f Input Rise and Fall Time (Note 7)V CC = 4.5 VV CC = 5.5 V 0108.0108.0ns/VT J Junction Temperature (PDIP)140°CI OH Output Current − High−24mAI OL Output Current − Low24mA6.Unused Inputs may not be left open. All inputs must be tied to a high voltage level or low logic voltage level.7.V in from 0.8 V to 2.0 V; refer to individual Data Sheets for devices that differ from the typical input rise and fall times.DC CHARACTERISTICSSymbol Parameter V CC(V)T A = +255CT A = −405C to+855CUnit Conditions Typ Guaranteed LimitsV IH Minimum High Level Input Voltage 4.55.51.51.52.02.02.02.0VVV OUT = 0.1 VorV CC − 0.1 VV IL Maximum Low Level Input Voltage 4.55.51.51.50.80.80.80.8VVV OUT = 0.1 VorV CC − 0.1 VV OH Minimum High Level Output Voltage 4.55.54.495.494.45.44.45.4VVI OUT = −50 m A4.55.53.864.863.764.76VV*V IN = V IL or V IH−24 mAI OH−24 mAV OL Maximum Low Level Output Voltage 4.55.50.0010.0010.10.10.10.1VVI OUT = 50 m A4.55.50.360.360.440.44VV*V IN = V IL or V IH−24 mAI OH−24 mAI IN Maximum Input Leakage Current 5.5±0.1±1.0m A V I = V CC, GND D I CCT Additional Max. I CC/Input 5.50.6 1.5mA V I = V CC − 2.1 V I OZ Maximum 3−State Current 5.5±0.5±5.0m A V I (OE) = V IL, V IHV I = V CC, GNDV O = V CC, GNDI OLD I OHD †Minimum Dynamic Output Current 5.55.575−75mAmAV OLD = 1.65 V MaxI CC Maximum Quiescent Supply Current 5.58.080m A V IN = V CC or GND *All outputs loaded; thresholds on input associated with output under test.†Maximum test duration 2.0 ms, one output loaded at a time.AC CHARACTERISTICS t r = t f = 3.0 ns (For Figures and Waveforms, See Figures 2 and 3.)Symbol Parameter V CC*(V)T A = +255CC L = 50 pFT A = −405C to +855CC L = 50 pFUnit Min Max Min Maxt PLH Propagation Delay An to Bn or Bn to An 5.0 1.58.0 1.08.5ns t PHL Propagation Delay An to Bn or Bn to An 5.0 1.58.0 1.09.0ns t PZH Output Enable Time OE to An or Bn 5.0 1.510.0 1.011.0ns t PZL Output Enable Time OE to An or Bn 5.0 1.510.0 1.011.0ns t PHZ Output Disable Time T/R or OE to An or Bn 5.0 1.510.0 1.011.0ns t PLZ Output Disable Time T/R or OE to An or Bn 5.0 1.510.0 1.011.0ns *Voltage Range 5.0 V is 5.0 V ±0.5 VCAPACITANCESymbol Parameter Value Typ Unit Test ConditionsC IN Input Capacitance 4.5pF V CC = 5.0 VC I/O Input/Output Capacitance15pF V CC = 5.0 VC PD Power Dissipation Capacitance45pF V CC = 5.0 VSWITCHING WAVEFORMSFigure 2. Figure 3.*Includes all probe and jig capacitance50 W SCOPE TEST POINTFigure 4. Test CircuitINPUT3.0 VGNDINPUT A or BOUTPUT A or BGNDV OL V OHA OR BA OR BHIGHIMPEDANCE OEHIGHIMPEDANCE 3.0 V3.0 VGNDT/RMARKING DIAGRAMSPDIP−20SOIC−20WSOEIAJ−201A = Assembly Location WL = Wafer Lot YY, Y = YearWW = Work WeekG = Pb−Free PackagePACKAGE DIMENSIONSPDIP−20N SUFFIXPLASTIC DIP PACKAGECASE 738−03ISSUE ENOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLD FLASH.DIM MIN MAX MIN MAX MILLIMETERSINCHES A 25.6627.171.010 1.070B 6.10 6.600.2400.260C 3.81 4.570.1500.180D 0.390.550.0150.022G 2.54 BSC 0.100 BSC J 0.210.380.0080.015K 2.80 3.550.1100.140L 7.62 BSC 0.300 BSC M 0 15 0 15 N0.51 1.010.0200.040____E 1.27 1.770.0500.070F 1.27 BSC 0.050 BSC SOIC−20WDW SUFFIX CASE 751D−05ISSUE GPACKAGE DIMENSIONSSOEIAJ−20M SUFFIX CASE 967−01ISSUE ADIM MIN MAX MIN MAX INCHES−−− 2.05−−−0.081MILLIMETERS 0.050.200.0020.0080.350.500.0140.0200.150.250.0060.01012.3512.800.4860.5045.10 5.450.2010.2151.27 BSC 0.050 BSC 7.408.200.2910.3230.500.850.0200.0331.10 1.500.0430.0590 0.700.900.0280.035−−−0.81−−−0.032A 1H E Q 1L E _10 _0 _10 _NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS D AND E DO NOT INCLUDEMOLD FLASH OR PROTRUSIONS AND AREMEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15(0.006) PER SIDE.4.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.5.THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTHDIMENSION AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACEBETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).A b c D E e L M ZON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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