西北工业大学部分数电实验VHDL程序合集

3位二进制数比较器4选1数据选择器8421码转换为格雷码8421码转换为余三码

数码管译码器带异步复位的四位二进制减计数器带异步复位的8421码十进制计数器

分频器带异步复位的四位环形计数器数码管显示012345数码管滚动显示012345

数码管滚动显示012345，且用全灭的数码管填充右边，直至全灭彩灯控制电路

（1）3位二进制数比较器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY comp3 IS

PORT(A:IN STD_LOGIC_VECTOR(2 DOWNTO 0); B:IN STD_LOGIC_VECTOR(2 DOWNTO 0); YA,YB,YC:OUT STD_LOGIC); END comp3;

ARCHITECTURE behave OF comp3 IS BEGIN

PROCESS(A,B) BEGIN

IF(A>B)THEN

YA<='1';YB<='0';YC<='0'; ELSIF(A

YA<='0';YB<='1';YC<='0'; ELSE

YA<='0';YB<='0';YC<='1'; END IF;

END PROCESS; END behave;

（2）4选1数据选择器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY mux4 IS

PORT(A:IN STD_LOGIC_VECTOR(1 DOWNTO 0); D0,D1,D2,D3:IN STD_LOGIC; Y,YB:OUT STD_LOGIC); END mux4;

ARCHITECTURE behave OF mux4 IS BEGIN

PROCESS(A,D0,D1,D2,D3) BEGIN

CASE A IS

WHEN"00"=> Y<=D0;YB <= NOT D0; WHEN"01"=> Y<=D1;YB <= NOT D1; WHEN"10"=> Y<=D2;YB <= NOT D2; WHEN"11"=> Y<=D3;YB <= NOT D3; WHEN OTHERS=> Y<='Z';YB<='Z'; END CASE; END PROCESS; END behave;

（3）8421码转换为格雷码

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY trans1 IS

PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END trans1;

ARCHITECTURE trans_gray OF trans1 IS BEGIN

B(0)<=A(0)XOR A(1); B(1)<=A(1)XOR A(2); B(2)<=A(2)XOR A(3); B(3)<=A(3); END trans_gray;

（4）8421码转换为余三码

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY sunyu_trans2 IS

PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END sunyu_trans2;

ARCHITECTURE trans_ex3 OF sunyu_trans2 IS BEGIN

PROCESS(A) BEGIN CASE A IS

WHEN"0000"=> B<="0011"; WHEN"0001"=> B<="0100"; WHEN"0010"=> B<="0101"; WHEN"0011"=> B<="0110"; WHEN"0100"=> B<="0111"; WHEN"0101"=> B<="1000"; WHEN"0110"=> B<="1001"; WHEN"0111"=> B<="1010"; WHEN"1000"=> B<="1011"; WHEN"1001"=> B<="1100"; WHEN OTHERS=> B<="ZZZZ"; END CASE; END PROCESS; END trans_ex3;

（5）数码管译码器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY sunyu_encoder IS

PORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:OUT STD_LOGIC_VECTOR(6 DOWNTO 0);

C:OUT STD_LOGIC_VECTOR(5 DOWNTO 0)); END sunyu_encoder;

ARCHITECTURE encoder_arch OF sunyu_encoder IS BEGIN

PROCESS(A) BEGIN

C<="011111"; CASE A IS

WHEN"0000"=> B<="1111110";--0 WHEN"0001"=> B<="0110000";--1 WHEN"0010"=> B<="1101101";--2 WHEN"0011"=> B<="1111001";--3 WHEN"0100"=> B<="0110011";--4 WHEN"0101"=> B<="1011011";--5 WHEN"0110"=> B<="1011111";--6 WHEN"0111"=> B<="1110000";--7 WHEN"1000"=> B<="1111111";--8 WHEN"1001"=> B<="1111011";--9 WHEN OTHERS=> B<="ZZZZZZZ"; END CASE; END PROCESS; END encoder_arch;

（1）带异步复位的四位二进制减计数器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY count_1 IS PORT(

clk,reset:IN STD_LOGIC;

q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END count_1;

ARCHITECTURE a OF count_1 IS

SIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN

PROCESS(clk,reset)

BEGIN

IF reset='0' THEN q_temp <="1111";

ELSIF clk'EVENT AND clk='1' THEN q_temp <=q_temp-1; END IF;