KK74LV174D中文资料

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TECHNICAL DATA

KK74LV174

Hex D-type flip-flop with reset; positive edge-trigger

The 74LV174 is a low–voltage Si–gate CMOS device and is pin and

function compatible with the 74HC/HCT174.

The 74LV174 has six edge–triggered D–type flip–flops with individual D

inputs and Q outputs. The common clock (CP) and master reset (MR)

inputs load and reset (clear) all flip–flops simultaneously.

The register is fully edge–triggered. The state of each D input, one set–up

time prior to the LOW–to–HIGH clock transition, is transferred to the

corresponding output of the flip–flop.

A LOW level on the MR input forces all outputs LOW, independently of

clock or data inputs.

The device is useful for applications requiring true outputs only and clock

and master reset inputs that are common to all storage elements. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS

• Supply voltage range: 1.2 to 5.5 V

• Low input current: 1.0 µА; 0.1 µА at Т = 25 °С

• Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5 V

• High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION KK74LV174N Plastic

KK74LV174D SOIC

TA = -40° to 125° C for all packages

FUNCTION TABLE

Inputs Outputs

MR CP Dn Qn

L X X L

H H H

H L L

H L X no change

H X no change

H= high level

L = low level

X = don’t care LOGIC DIAGRAM

PIN 16=VCC

PIN 08 = GND CP

MR PIN ASSIGNMENT

8GND16

9VCCMR

Q2D5

CPQ5

1元器件交易网www.cecb2b.comKK74LV174

MAXIMUM RATINGS*

Symbol Parameter Value Unit

VCCDC supply voltage -0.5 to +5.0 V

IIK *1Input diode current ±20 mA

IOK *2Output diode current ±50 mA

IO *3Output source or sink current ±25 mA

ICCVCC current ±50 mA

IGNDGND current ±50 mA

PDPower dissipation per package: *4

Plastic DIP

750

500 mW

Tstg Storage Temperature -65 to +150 °C

TLLead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm

(SO Package) from Case for 4 Seconds 260 °C

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

*1 VI < -0.5 V or VI > VCC + 0.5 V

*2 VO < -0.5 V or VO > VCC + 0.5 V

*3 -0.5 V < VO < VCC + 0.5 V

*4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C

SO Package: : - 8 mW/°C from 70° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

VCCDC Supply Voltage 1.2 5.5 V

VINDC Input Voltage 0 VCCV

VOUTDC Output Voltage 0 VCCV

TAOperating Temperature, All Package Types -40 +125 °C

tr, tfInput Rise and Fall Time (Figure 1) 1.0 В ≤VCC <2.0 В

2.0 В ≤VCC <2.7 В

2.7 В ≤VCC <3.6 В

3.6 В ≤VCC ≤5.5 В 0

0 500

200

100

50 ns/V

This device contains protection circuitry to guard against damage due to high static voltages or electric fields.

However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this

high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or

VOUT)≤VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused

outputs must be left open.

2元器件交易网www.cecb2b.comKK74LV174

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Test VCCGuaranteed Limit

Symbol Parameter conditions V -40°C to 25°C85°C 125°C Unit

min maxmin max min max

VIHHIGH level input

voltage 1.2

2.0

2.7

3.0

3.6

4.5

5.50.9

1.4

2.0

3.15

3.85 -

- 0.9

1.4

2.0

3.15

3.85-

- 0.9

1.4

2.0

3.15

3.85 -

- V

VILLOW level input

voltage 1.2

2.0

2.7

3.0

3.6

4.5

5.5-

- 0.3

0.6

0.8

1.35

1.65-

- 0.3

0.6

0.8

1.35

1.65 -

- 0.3

0.6

0.8

1.35

1.65V

VOHHIGH level output

voltage VI = VIH or VILIO = -100 µА 1.2

2.0

2.7

3.0

3.6

4.5

5.51.05

1.85

2.55

2.85

3.45

4.35

5.35 -

- 1.0

1.8

2.5

2.8

3.4

4.3

5.3 -

- 1.0

1.8

2.5

2.8

3.4

4.3

5.3 -

- V

VI = VIH or VILIO = -6 mА 3.02.48 - 2.34- 2.20 - V

VI = VIH or VILIO = -12 mА 4.53.70 - 3.60- 3.50 - V

VOLLOW level output

voltage VI = VIH or VILIO = 100 µА 1.2

2.0

2.7

3.0

3.6

4.5

5.5-

- 0.15

0.15

0.15-

- 0.2

0.2

0.2 -

- 0.2

0.2

0.2 V

VI = VIH or VILIO = 6 mА 3.0- 0.33- 0.40 - 0.50V

VI = VIH or VILIO = 12 mА 4.5- 0.40- 0.55 - 0.65V

IIInput current VI = VCC or 0 V5.5- ±0.1- ±1.0 - ±1.0µА

ICCSupply current VI =VCC or 0 V

IO = 0 µА 5.5- 8.0 - 80 - 160µА

ICC1Additional

quiescent supply

current per input VI =VCC –

0.6 V 2.7

3.6- 0.2

0.2 - 0.5

0.5 - 0.85

0.85mA

3元器件交易网www.cecb2b.com

KK74HCT241ADW资料

TECHNICAL DATA KK74HCT241A

Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Performance Silicon-Gate CMOS

ORDERING INFORMATION KK74HCT241AN Plastic KK74HCT241ADW SOIC TA = -55° to 125° C for all packages The KK74HCT241A is identical in pinout to the LS/ALS241. The KK74HCT241A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This octal noninverting buffer/line driver/line receiver is designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has noninverting outputs and two output enables. Enable A is active-low and Enable B is active-high. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 4.5 to 5.5 V • Low Input Current: 1.0 µA

KK74LS164中文资料

TECHNICAL DATA

KK74LS164

8-Bit Serial-Input/Parallel-Output

Shift Register

ORDERING INFORMATION KK74LS164N Plastic KK74LS164D SOIC TA =0° to 70°C for all packages

This 8-bit shift register features gated serial inputs and an asynchronous reset. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip flop to the low level at the next clock pulse. A high level input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup requirements will be entered clocking occurs or the low-to-high level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects. • Gated (Enable/Disable) Serial Inputs • Fully Buffered Clock and Serial Inputs • Asynchronous Clear

KK74AC299DW资料

TECHNICAL DATA

KK74AC299

8-Bit Bidirectional Universal

Shift Register with Parallel I/O

High-Speed Silicon-Gate CMOS

ORDERING INFORMATION KK74AC299N Plastic KK74AC299DW SOIC TA = -40° to 85° C for all packages

The KK74AC299 is identical in pinout to the LS/ALS299, HC/HCT299. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. The KK74AC299 features a multiplexed parallel input/output data port to achieve full 8-bit handling in a 20 pin package. Due to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system. Two Mode-Select inputs and two Output Enable inputs are used to choose the mode of operation as listed in the Function Table. Synchronous parallel loading is accomplished by taking both Mode-Select lines, S1 and S2, high. This places the outputs in the high-impedance state, which permits data applied to the data port to be clocked into the register. Reading out of the register can be accomplished when the outputs are enabled. The active-low asynchronous Reset overrides all other inputs. • Outputs Directly Interface to CMOS, NMOS, and TTL

74LV245DB资料

元器件交易网

Philips SemiconductorsProduct specification

74LV245Octal bus transceiver (3-State)

21998 Apr 20853–1931 19258FEATURES

•

Wide operating voltage: 1.0 to 5.5 V

•

Optimized for low voltage applications: 1.0 to 3.6 V

•

Accepts TTL input levels between V

CC = 2.7 V and V

CC = 3.6 V

•

Typical V

OLP (output ground bounce) < 0.8 V at V

CC = 3.3 V,

amb = 25°C

•

Typical V

OHV (output V

OH undershoot) > 2 V at V

CC = 3.3 V,

amb = 25°C

•

Output capability: bus driver

•

CC category: MSIDESCRIPTION

The 74LV245 is a low-voltage Si-gate CMOS device and is pin and

function compatible with 74HC/HCT245.

The 74LV245 is an octal transceiver featuring non-inverting 3-State

bus compatible outputs in both send and receive directions. The

74LV245 features an output enable (OE) input for easy cascading

and a send/receive (DIR) input for direction control. OE controls the

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KK74LV174D中文资料

合集下载

KK74HCT241ADW资料

KK74LS164中文资料

KK74AC299DW资料

74LV245DB资料

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