FT-2000+64硬件设计指导手册

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FT-2000+硬件设计指导手册

2018年12月

版本号1.0版本历史

版本号作者参与者发布日期备注1.0目录

目录.....................................................................................................................................................31文档介绍.........................................................................................................................................4

2复用引脚说明.................................................................................................................................4

2.1引脚复用..............................................................................................................................4

2.2LPC功能说明........................................................................................................................7

2.2.1LPC复用关系与信号说明.........................................................................................7

2.2.2LPC建议接法............................................................................................................8

2.3软件关机、重启..................................................................................................................8

2.4配置引脚建议接法.............................................................................................................8

2.5I2C........................................................................................................................................11

2.5.1SPDI2C.....................................................................................................................11

2.5.2RTCI2C.....................................................................................................................12

3PCIE布线要求................................................................................................................................12

4内存布线要求...............................................................................................................................12

4.1阻抗要求............................................................................................................................12

4.2交换准则............................................................................................................................12

4.3布线要求............................................................................................................................13

4.3.1间距要求.................................................................................................................13

4.3.2等长要求.................................................................................................................14

4.3.3PCB叠层要求..........................................................................................................141文档介绍

本文档说明了FT-2000+平台在原理图设计、板级设计阶段需要遵循的基本规则,旨

在减少用户在设计阶段的疑惑以及不确定性,增加设计可靠性。

2复用引脚说明

在FT-2000+芯片设计中,部分功能模块引脚与普通GPIO口存在复用关系.设计阶段

需了解具体的复用关系、引脚的默认功能和特殊用途。

复用关系需通过对应寄存器来配置不同的功能,默认为func0功能。

2.1引脚复用表1引脚功能复用表

SigNamePINfunc0func1func2

CLK_REF_50MAR13clk_ref

RESET_NAN15reset_n

POR_NAP13por_n

CRU_SCAN_CLKAP15cru_scan_clk

CRU_CLK_SELAM15cru_clk_sel

CRU_CLK_STOPAN14cru_clk_stop

CRU_SEAM14cru_se

CRU_SIAR14cru_si

CRU_SOAN13cru_so

CRU_RST_OKAP14cru_rst_ok

CRU_I2C_SCLAM13cru_scl

CRU_I2C_SCLAM13cru_sda

TCKAJ15tck

SJTAG_TDIAL13sjtag_tdi

SJTAG_TMSAL14sjtag_tms

SJTAG_NTRSTAK14sjtag_ntrst

SJTAG_TDOAK15sjtag_tdo

SJTAG_TCKAJ13sjtag_tck

FORCE_MB_STARTAK13force_mb_start

LPC_IRQ_N/GPIO_B6BH43hdt_mb_done_statelpc_ext_irq_outenpeu1_linkup_0LPC_LAD_OUTEN/PEU1_LI

NKUP1AJ16hdt_mb_fail_statelpc_ext_lad_outenpeu1_linkup_1

INSTANCEID0N21instanceid_0

INSTANCEID1N20instanceid_1

SWJ_NTRSTP22ntrst_swj

SWJ_TDIN22tdi_swj

SWJ_SWDITMSP20swditms_swj

SWJ_SWDOP21swdo_swj

SWJ_TCKN19tck_swj

SWJ_TDOP19tdo_swj

UART0_CTS_N/GPIO_A0AM48cru_ckobv_sel_0gpio_porta_0uart_0_cts_n

UART0_DCD_N/GPIO_A1AM47cru_ckobv_sel_1gpio_porta_1uart_0_dcd_n

UART0_DSR_N/GPIO_A2AL48cru_ckobv_sel_2gpio_porta_2uart_0_dsr_n

UART0_RI_N/GPIO_A3AK47cru_ckobv_sel_3gpio_porta_3uart_0_ri_n

UART0_RTS_N/GPIO_A4AL46cru_ckobv_sel_4gpio_porta_4uart_0_rts_n

UART0_DTR_N/GPIO_A5/C

RU_CLK_OBVAL47cru_clk_obvgpio_porta_5uart_0_dtr_n

SPI_CSN2/GPIO_A6AK48spi_ext_csn2gpio_porta_6traceclk_out

SPI_CSN3/GPIO_A7AK46spi_ext_csn3gpio_porta_7tracectl_out

I2C0_SCL/GPIO_B0AH47i2c_0_sclgpio_portb_0tracedata_out_

0

I2C0_SDA/GPIO_B1AG47i2c_0_sdagpio_portb_1tracedata_out_

1

I2C1_SCL/GPIO_B2AF47i2c_1_sclgpio_portb_2tracedata_out_

2

I2C1_SDA/GPIO_B3AG46i2c_1_sdagpio_portb_3tracedata_out_

3

UART1_RXD/GPIO_B4BG44uart_1_rxdgpio_portb_4tracedata_out_

4

UART1_TXD/GPIO_B5BH44uart_1_txdgpio_portb_5tracedata_out_

5

LPC_IRQ_N/GPIO_B6BH43gpio_portb_6ext_lpc_irq_ntracedata_out_

6

LPC_LAD_0/GPIO_B7BG43gpio_portb_7ext_lpc_lad_0tracedata_out_

7

CRU_RST_FSM0/GPIO_C0BH42cru_rst_fsm_0gpio_portc_0tracedata_out_