SN74LV367ADGVR中文资料
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SN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3ĆSTATE OUTPUTS
SCLS398G − APRIL 1998 − REVISED APRIL 2005
1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265D2-V to 5.5-V VCC Operation
DMax tpd of 7 ns at 5 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DTypical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
DSupport Mixed-Mode Voltage Operation on
All Ports
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
The ’LV367A devices are hex buffers and line
drivers designed for 2-V to 5.5-V VCC operation.
These devices are designed specifically to
improve both the performance and density of
3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters.
The ’LV367A devices are organized as dual 4-line
and 2-line buffers/drivers with active-low
output-enable (1OE and 2OE) inputs. When OE is
low, the device passes noninverted data from the
A inputs to the Y outputs. When OE is high, the
outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBERTOP-SIDE
MARKING
Tube of 40SN74LV367ADSOIC − DReel of 2500SN74LV367ADRLV367A
SOP − NSReel of 2000SN74LV367ANSR74LV367A
°°SSOP − DBReel of 2000SN74LV367ADBRLV36A−40C to 85C
Reel of 2000SN74LV367APWRTSSOP − PWReel of 250SN74LV367APWTLV367A
TVSOP − DGVReel of 2000SN74LV367ADGVRLV367A
CDIP − JTube of 25SNJ54LV367AJSNJ54LV367AJ
°°CFP − WTube of 150SNJ54LV367AWSNJ54LV367AW−55C to 125C
LCCC − FKTube of 55SNJ54LV367AFKSNJ54LV367AFK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.3212019
9101112134
5
6
7
818
17
16
15
142A2
2Y2
NC
2A1
2Y11Y1
1A2
NC
1Y2
1A31A1
1OE
NC
1Y4
1A4V2OE
1Y3
GNDNCSN54LV367A...FK PACKAGE
(TOP VIEW)
CC
NC − No internal connection1
2
3
4
5
6
7
816
15
14
13
12
11
10
91OE
1A1
1Y1
1A2
1Y2
1A3
1Y3
GNDVCC
2OE
2A2
2Y2
2A1
2Y1
1A4
1Y4SN54LV367A...J OR W PACKAGE
SN74LV367A...D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
UNLESS OTHERWISE NOTED this document contains PRODUCTIONDATA information current as of publication date. Products conform tospecifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of allparameters.Copyright 2005, Texas Instruments IncorporatedPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.元器件交易网www.cecb2b.comSN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3ĆSTATE OUTPUTS
SCLS398G − APRIL 1998 − REVISED APRIL 2005
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265FUNCTION TABLE
(each buffer/driver)
INPUTSOUTPUT
OEAY
LHH
LLL
HXZ
logic diagram (positive logic)
1OE
To Three Other Channels1A11Y11
232OE
To One Other Channel2A12Y115
1211
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or
power-off state, VO (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range applied in the high or low state, VO (see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3):D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
