WP34SF4C中文资料

前言

本文件（EN13445-5：2002）由CEN/TC 54“非直接接触火焰压力容器”技术委员会制定，其秘书处由BSI负责运作。

本欧洲标准应视同国家标准，欧盟各成员国应于2002年11月之前通过背书或发行等效文本对其予以承认，与之相冲突的原国家标准应予废止。

本文件由欧盟委员会和欧洲自由贸易协会任命CEN制定，支持欧盟指令的主要要求。

本文件与欧盟指令的关系，可参考附录ZA，它也是本文件不可分割的一部分。

本标准中的附录A和B是标准的附录。

本欧洲标准包括以下部分：

第一部分：总论

第二部分：材料

第三部分：设计

第四部分：制造

第五部分：检测和试验

第六部分：球墨铸铁制压力容器及压力部件的设计和制造要求

第七部分：合格评定程序的指导

根据CEN/CENELEC的内部规章，下列国家的国家标准机构必须实施本欧洲标准，他们是：

奥地利，比利时，捷克，丹麦，芬兰，法国，德国，希腊，冰岛，爱尔兰，意大利，卢森堡，马尔他，荷兰，挪威，葡萄牙，西班牙，瑞典，瑞士，英国。

1 范围

本标准规详细说明了各个部件制造过程中的要求，即材料的制造和分包，加工过程中监测、加工公差、焊接要求、成形加工要求、产品试验、热处理、修理和最后完成的工序等。

2 引用标准

本欧洲标准包括注有日期或未标明日期的参考标准，以及其他标准的条款。这些参考标准引用在正文的适当位置，并且在此后列出。对标明日期的参考标准，其后的增补或修改，只有在本欧洲标准加以引用时才适用。对于未标明日期的参考标准，则使用最新版本。

下列标准或文件与本欧洲标准有冲突或差异时，应以本标准为准。

EN 287-1：1992焊工的鉴定考查——熔焊——第一部分：钢

EN 288-2：1992金属材料焊接程序的技术规范和鉴定——第2部分：电弧焊的焊接程序技术规范

EN 288-3：1992金属材料焊接程序的技术规范和鉴定——第3部分：钢材电弧焊的焊接程序试验

EN 288-6：1994金属材料焊接程序的技术规范和鉴定——第6部分：与经验有关的鉴定

C3430 FCXO Vectron International · v.2005-10-28 · page 1 of 6 Vectron International Headquarters 267 Lowell Road Hudson, New Hampshire 03051 +1-888-328-7661 tel +1-888-329-8328 fax Vectron International LLC. 100 Watts Street Mount Holly Springs, PA 17065 USA +1-717-486-3411 tel +1-717-486-5920 fax Vectron international GmbH & Co. KG Landstrasse D-74924 Neckarbischofsheim Germany +49-07268-801-0 tel +49-07268-801-281 fax Vectron Asia Pacific Sales Office 1F-2F, No 8 Workshop, No 308 Fenju Road, WaiGaoQiao Free Trade Zone, Pudong, Shanghai, P.R. China 200131 +86 21 5048 0777 tel. +86 21 5048 1881 fax Typical Applications Features Base Stations Surface Mount Package Reflow Process Compatible Low Phase Noise Build in PLL-Circuit Output Frequency range 10 MHz – 700 MHz Standard frequencies 52; 61.44;104, 122,88 MHz Reference Frequency Parameter Min Typ Max. Units Condition Ordering Code5 Input frequency Pin 2 1 160 MHz ± 2 ppm Standard input frequencies 10 MHz X106 13 MHz X136 26 MHz X266 32,768 MHz X326 Parameter Min Typ Max. Units Condition Reference Level Reference Input Impedance Harmonics 0.5 2 -30 Vpp kΩ dBc @ 2 kΩ Output Frequency Parameter Min Typ Max. Units Condition Ordering Code5 output frequency Pin 4 10 700 MHz Standard output frequencies 52 MHz X526 61.44 X616 Supply voltage (Vs) Parameter Min Typ Max. Units Condition Ordering Code5 Supply voltage [Standard] 3.135 3.3 3.465 VDC SV033 Current consumption 50 mA steady state @ +25°C & 3.3VDC RF output Parameter Min Typ Max. Units Condition Ordering Code5 Signal [Standard] HCMOS RFH Load 15 pF Signal Level (Vol) 0.3 VDC with Vs=3.3V and 15pF load Signal Level (Voh) 3.0 VDC with Vs=3.3V and 15pF load Rise and Fall time 5 ns Duty cycle 40 60 % @ (Voh-Vol)/2 Additional parameters Parameter Min Typ Max. Units Condition Phase Noise3 -80 dBc/Hz 10 Hz @ 61.44 MHz -110 dBc/Hz 100 Hz -135 dBc/Hz 1 kHz -150 dBc/Hz 10 kHz -155 dBc/Hz 100 kHz 元器件交易网 C3430 FCXO Vectron International · v.2005-10-28 · page 2 of 6 Vectron International Headquarters 267 Lowell Road Hudson, New Hampshire 03051 +1-888-328-7661 tel +1-888-329-8328 fax Vectron International LLC. 100 Watts Street Mount Holly Springs, PA 17065 USA +1-717-486-3411 tel +1-717-486-5920 fax Vectron international GmbH & Co. KG Landstrasse D-74924 Neckarbischofsheim Germany +49-07268-801-0 tel +49-07268-801-281 fax Vectron Asia Pacific Sales Office 1F-2F, No 8 Workshop, No 308 Fenju Road, WaiGaoQiao Free Trade Zone, Pudong, Shanghai, P.R. China 200131 +86 21 5048 0777 tel. +86 21 5048 1881 fax Additional parameters Parameter Min Typ Max. Units Condition VCXO Control PIN 7 0.5 2.5 V Weight 9 g Processing & Packing Handling & processing note Operating temperature range Operable temperature range -20 -30 +70 +85 °C Storage temperature range -55 +125 °C Enclosures Type G194 Package Codes: Code Height “H” Pin Length “L” A1 5.9 NA Dimensions: mm Pin Connections Description 1 VCXO Control Test output of the control voltage for the VCXO (0.5V to 2.8V) Only for modul test or observance 2 Lock Detector Output Test output signal for PLL lock detected. Low signal à PLL out of lock High signal à PLL in lock Only for modul test or observance 6;6;9 GND Ground connection. Keep traces physically short and connect immediately to ground plane for best performance 8 RF-OUT RF syncronised output. 13 Ref. Frequency in High stabel input frequency for syncronisation, This input is AC coupled, so an external blocking capacitor is not necessary. 14 Vs Power supply pin. External low frequency bypass capacitor should be connected Marking C3430A1-xxxx Frequency * VI AYYWW 元器件交易网 C3430 FCXO Vectron International · v.2005-10-28 · page 3 of 6 Vectron International Headquarters 267 Lowell Road Hudson, New Hampshire 03051 +1-888-328-7661 tel +1-888-329-8328 fax Vectron International LLC. 100 Watts Street Mount Holly Springs, PA 17065 USA +1-717-486-3411 tel +1-717-486-5920 fax Vectron international GmbH & Co. KG Landstrasse D-74924 Neckarbischofsheim Germany +49-07268-801-0 tel +49-07268-801-281 fax Vectron Asia Pacific Sales Office 1F-2F, No 8 Workshop, No 308 Fenju Road, WaiGaoQiao Free Trade Zone, Pudong, Shanghai, P.R. China 200131 +86 21 5048 0777 tel. +86 21 5048 1881 fax Absolute Maximum Ratings Parameter Min Typ Max. Units Condition Supply voltage (Vs) 6.0 V Maximum output load @ CMOS 40 pF Typical measurement data Phase Noise and Jitter C3530A1 with 32.768MHz in &52MHz out Frequency range [Hz] Sφ(f) [dB] Jitter [ps rms] 100 Hz to 1.5 MHz -61,86 1.616 ps 50 kHZ to 1.5MHz -62,07 1.578 ps Block Diagramm VS815408154VCXOPLLCircuitReferenceFrequencyVCXOLockDetectorVCXOControl0VCXOVSVS0Loop FilterVS 元器件交易网 C3430 FCXO Vectron International · v.2005-10-28 · page 4 of 6 Vectron International Headquarters 267 Lowell Road Hudson, New Hampshire 03051 +1-888-328-7661 tel +1-888-329-8328 fax Vectron International LLC. 100 Watts Street Mount Holly Springs, PA 17065 USA +1-717-486-3411 tel +1-717-486-5920 fax Vectron international GmbH & Co. KG Landstrasse D-74924 Neckarbischofsheim Germany +49-07268-801-0 tel +49-07268-801-281 fax Vectron Asia Pacific Sales Office 1F-2F, No 8 Workshop, No 308 Fenju Road, WaiGaoQiao Free Trade Zone, Pudong, Shanghai, P.R. China 200131 +86 21 5048 0777 tel. +86 21 5048 1881 fax Standard Shipping Method *bei W ≤ 24 mmnuruntere Lochreihe∗byW≤ 24 mm only lower hole lineGurtoberseiteTape upper sideGurtunterseiteTape buttom sideAbwickelrichtungUnwinding directionLage im GurtPosition in tapePin 1AXPBK Production tolerance complying DIN IEC 286-3 Enclosure Type Tape width W [mm] Quantity per meter Quantity per reel Dimension P G194B tbd tbd tbd tbd 元器件交易网

Stratix III Device Handbook, Volume 1The Stratix®III family provides one of the most architecturally advanced,

high-performance, low-power FPGAs in the marketplace.

StratixIII FPGAs lower power consumption through Altera’s innovative

Programmable Power Technology, which provides the ability to turn on the

performance where needed and turn down the power consumption for blocks not in

use. Selectable Core Voltage and the latest in silicon process optimizations are also

employed to deliver the industry’s lowest power, high-performance FPGAs.

Specifically designed for ease of use and rapid system integration, the StratixIII

FPGA family offers two variants optimized to meet different application needs:

■The StratixIII L family provides balanced logic, memory, and multiplier ratios for

mainstream applications.

Configurationmemory, and transmit this compressed bitstream to Stratix II GX FPGAs. During configuration, the Stratix II GX FPGA decompresses the bitstream in real time and programs its SRAM cells. Stratix II GX FPGAs support decompression in the FPP (when using a MAX II device or microprocessor and flash memory), AS, and PS configuration schemes. Decompression is not supported in the PPA configuration scheme nor in JTAG-based configuration.Remote System UpgradesShortened design cycles, evolving standards, and system deployments in remote locations are difficult challenges faced by system designers. Stratix II GX devices can help effectively deal with these challenges with their inherent re programmability and dedicated circuitry to perform remote system updates. Remote system updates help deliver feature enhancements and bug fixes without costly recalls, reducing time to market, and extending product life.Stratix II GX FPGAs feature dedicated remote system upgrade circuitry to facilitate remote system updates. Soft logic (Nios processor or user logic) implemented in the Stratix II GX device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. This dedicated remote system upgrade circuitry avoids system downtime and is the critical component for successful remote system upgrades.Remote system configuration is supported in the following Stratix II GX configuration schemes: FPP, AS, PS, and PPA. Remote system configuration can also be implemented in conjunction with Stratix II GX features such as real-time decompression of configuration data and design security using AES for secure and efficient field upgrades.fRefer to the Remote System Upgrades with Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device Handbook for more information about remote configuration in Stratix II GX devices.Configuring Stratix II GX FPGAs with JRunnerThe JRunner™ software driver configures Altera FPGAs, including Stratix II GX FPGAs, through the ByteBlaster II or ByteBlasterMV cables in JTAG mode. The programming input file supported is in Raw Binary File (.rbf) format. JRunner also requires a Chain Description File (.cdf) Operating Conditionsreconfig_clk clock frequency 2.5 -50 2.5 -50 2.5 -50MHzTransceiver block minimum power-down pulse width100--100--100--nsReceiverData rate600-6375600-5000600-4250MbpsAbsolute VMAX for a receiver pin (1)--2.0--2.0--2.0VAbsolute VMIN for a receiver pin-0.4---0.4---0.4--VMaximum peak-to-peak differential input voltage VID (diff p-p)VCM = 0.85V--3.3--3.3--3.3VMinimum peak-to-peak differential input voltage VID (diff p-p)VCM = 0.85VDC Gain = ≥3dB160--160--160--mVVICMVICM = 0.85 V setting850±10%850±10%850±10%mVVICM = 1.2V setting (11)1200±10%1200±10%1200±10%mVOn-chip termination resistors100Ω setting100±15%100±15%100±15%Ω120Ω setting120±15%120±15%120±15%Ω150Ω setting150±15%150±15%150±15%ΩBandwidth at 6.375 Gbps BW = Low-20-------MHzBW = Med-35-------MHzBW = High-45-------MHzTable4–6.Stratix II GX Transceiver Block AC Specification(Part 3 of6)Symbol / DescriptionConditions-3 Speed CommercialSpeed Grade-4 Speed Commercialand Industrial SpeedGrade-5 Speed CommercialSpeed GradeUnitMinTypMaxMinTypMaxMinTypMaxOperating ConditionsFibre Channel Transmit Jitter Generation (8), (17)Total jitter FC-1REFCLK = 106.25 MHzPattern = CRPATVOD = 800 mVNo Pre-emphasis--0.23--0.23--0.23UIDeterministic jitter FC-1REFCLK = 106.25 MHzPattern = CRPATVOD = 800 mVNo Pre-emphasis--0.11--0.11--0.11UITotal jitter FC-2REFCLK = 106.25 MHzPattern = CRPATVOD = 800 mVNo Pre-emphasis--0.33--0.33--0.33UIDeterministic jitter FC-2REFCLK = 106.25 MHzPattern = CRPATVOD = 800 mVNo Pre-emphasis--0.2--0.2--0.2UITotal jitter FC-4REFCLK = 106.25 MHzPattern = CRPATVOD = 800 mVNo Pre-emphasis--0.52--0.52--0.52UIDeterministic jitter FC-4REFCLK = 106.25 MHzPattern = CRPATVOD = 800 mVNo Pre-emphasis--0.33--0.33--0.33UIFibre Channel Receiver Jitter Tolerance (8), (18)Deterministic jitter FC-1Pattern = CJTPATNo EqualizationDC Gain = 0 dB>0.37>0.37>0.37UIRandom jitter FC-1Pattern = CJTPATNo EqualizationDC Gain = 0 dB>0.31>0.31>0.31UITable4–19.Stratix II GX Transceiver Block AC Specification Notes(1), (2), (3)(Part 3 of19)Symbol/DescriptionConditions-3 SpeedCommercial Speed Grade-4 SpeedCommercial and Industrial Speed Grade-5 SpeedCommercial Speed GradeUnitMinTypMaxMinTypMaxMinTypMaxDC and Switching Characteristics