Description
The A1140, A1141, A1142, and A1143 devices are sensitive,
two-wire, unipolar, Hall effect switches that are factory-
programmed at end-of-line to optimize magnetic switchpoint
accuracy. These devices use a patented high frequency chopper-
stabilization technique, produced using the Allegro advanced
BiCMOS wafer fabrication process, to achieve magnetic
stability and to eliminate offset inherent in single-element
devices exposed to harsh application environments.
Commonly found in a number of automotive applications,
these switches are utilized to sense seat track position,
seat belt buckle presence, hood/trunk latching, and shift
selector position. Two-wire unipolar switches, such as the
A1140/41/42/43 family, are particularly advantageous in
price-sensitive applications because they require one less
实用文档
文案大全
NO： 发 送 单 位 备 注
NO： 发 送 单 位 备 注
NO： 发 送 单 位 备 注
1 安装支援部 6 辽宁分公司 11
2 北京营销公司 7 江苏分公司 12
3 成都营销公司 8 培训部 13
4 华南工务科 9 工务品保部 14
5 华东工务科 10 15
安装技术文件
文件编号 IS-2208 试车
e'NT电梯调试作业资料
资料来源：工厂设计部
版次NO： 发行年月日 作 成 审 查 承 认
1.0 05.04.01 刘岳宝 包国强 吴金隆
作 成 技术文件 刘岳宝 05.03.20
审 查 技术文件 包国强 05.03.21
技术文件 吴金隆 05.03.21
承 认 工务处 张石清 05.03.25 实用文档
文案大全 上海永大电梯设备有限公司 安装维修分公司
e’NT调试试运转及调整要领目录
实用文档
文案大全 一、 e’NT与NT差异对照表
二、 e’NT系统构成图
三、 e’NT的概要
四、 各PC板安装及工事配线确认
五、 各接地线连接取付实况
六、 RE及MOTOR配线CHECK
七、 作业上的注意事项
八、 电梯低速运转前的作业事项
九、 绝缘测定、PC板电压设定及调整
十、 低速试运转
十一、高速运转前准备
十二、高速运转准备
十三、LINKLESS门机
十四、阶高测定
十五、高速确认
十六、平衡电流测试
十七、起动补偿调整
十八、着床平层调整
十九、电梯微速时间调整
二十、MICRO运转水平调整
二十一、乘场及车厢LED楼层显示器之点检
二十二、各楼层开关门时间调整
二十三、HALL LAN系统
二十四、ANN操作
DateVersionChanges
May 20132013.05.06•Moved all links to the Related Information section of respective topicsfor easy reference.
•Added link to the known document issues in the Knowledge Base.
•Updated the available options, maximum resource counts, and perpackage information for the Arria V SX and ST device variants.
•Updated the variable DSP multipliers counts for the Arria V SX andST device variants.
•Clarified that partial reconfiguration is an advanced feature. ContactAltera for support of the feature.
•Added footnote to clarify that MLAB 64 bits depth is available onlyfor Arria V GZ devices.
•Updated description about power-up sequence requirement for devicemigration to improve clarity.
January 20132013.01.11•Added the L optional suffix to the Arria V GZ ordering code for the –I3 speed grade.
•Added a note about the power-up sequence requirement if you plan tomigrate your design from the Arria V GX A5 and A7, and Arria V GTC7 devices to other Arria V devices.
1
xpga_04ispXPGA Family
March 2003Preliminary Data SheetTM
© 2003 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at /legal. All other brandor product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.■Non-volatile, Infinitely Reconfigurable •Instant-on - Powers up in microseconds via on-chip E2CMOS® based memory•No external configuration memory•Excellent design security, no bit stream to intercept•Reconfigure SRAM based logic in milliseconds
■High Logic Density for System-level Integration•139K to 1.25M system gates•160 to 496 I/O•1.8V, 2.5V, and 3.3V VCC operation•Up to 414Kb sysMEM™ embedded memory
■High Performance Programmable Function Unit (PFU)•Four LUT-4 per PFU supports wide and narrow functions•Dual flip-flops per LUT-4 for extensive pipelining•Dedicated logic for adders, multipliers, multiplex-ers, and counters
