OPB32PLB4中文资料

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Highlights
Performance Features
• OPB slave device and PLB master device.
• Ability to be mapped to any OPB address space.
• 128-bit PLB master interface supports quadword reads, and quadword,
doubleword, word, halfword, and byte writes.
• Support for 128-bit PLB slaves only.No conversion cycles for 64-bit or 32-bit slaves.
• Single-cycle response to OPB writes.• Data packing on writes, up to 2-quadwords.
• Prefetching for single reads, 1-quadword.
• Guarded reads, word, halfword, and byte.
• Fixed length burst prefetching for sequential reads, 2-quadwords.• Single-cycle response to OPB reads serviced by data buffer.
• Up to 166 MHz PLB clock frequency.• Up to 66 MHz OPB clock frequency.• Support for PLB at 2, 3, 4, or 5 times the frequency of the OPB.• IBM full scan DFT.
• Support for clock and power management.
The OPB to PLB bridge is a soft core which enables transfers of data between the OPB and PLB under the direction of OPB master devices.
The bridge is a slave on the OPB and a master on the PLB.It is necessary in any system implementation with OPB master devices, which must access system resources on the PLB.
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128-bit OPB to PLB Bridge Core
C27E501_OPB_PLB_128BR and OPB32PLB4
High performance core for highly integrated Core+ASIC systems
International Business Machines Corporation 2001, 2002
Printed in the United States of America 3/14/02
All Rights Reserved
The information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM’s product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties.All information contained in this document was obtained in specific
environments, and is presented as illustration.The results obtained in other operating environments may vary.
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Document No. SA14-2586-01
Addr
State Machine Control Logic
Frequency Synchronization Logic
OPB Data Out OPB Data In OPB Addr
OPB Ctrl
PLB-rdDBus M_wrDBus PLB_ABus PLB Transfer Qualifiers
On-chip Peripheral Bus
128-bit Data
Data Steering
Parameters
Increment
PLB I/F State Machine
PLB Ctrl
Processor Local Bus
Address and Transfer Qualifier
• The bridge contains latches which capture the 32-bit OPB address and transfer qualifiers. Addresses are incremented internally as necessary to drive the proper address on the PLB.
Clock and Power Management
•Power consumption within the OPB to PLB bridge is reduced by gating the clock to all latches internally.Minimum power is achieved when no active PLB requests are pending,the data buffer is empty, and the OPB is idle.
• In addition, a sleep request signal is provided to be used by a central
clock and power management unit in a system. This signal is asserted by the OPB to PLB bridge to indicate when it is permissible to shut off its clocks.
Internal Data Buffer Structure
• The OPB to PLB bridge core
contains a 32-byte data buffer, used for both read and write operations.During write operations, the buffer is organized as a 2-quadword FIFO.During read operations,the buffer is organized as a fully associative cache with a line size of one fullword.。