CMDZ7V5中文资料

1)Non-repetitive current pulse see curve I PPM = f (t r )Höchstzulässiger Spitzenwert eines einmaligen Strom-Impulses, siehe Kurve I PPM = f (t r )2)Valid, if leads are kept at ambient temperature at a distance of 10 mm from caseGültig, wenn die Anschlußdrähte in 10 mm Abstand von Gehäuse auf Umgebungstemperatur gehalten werden 3)Unidirectional diodes only – Nur für unidirektionale Dioden 107.01.2003Unidirectional and bidirectionalUnidirektionale und bidirektionaleTransient Voltage Suppressor DiodesSpannungs-Begrenzer-DiodenPeak pulse power dissipation 600 W Impuls-Verlustleistung Maximum stand-off voltage 5.8...376 VMaximale Sperrspannung Plastic case – Kunststoffgehäuse DO-15 (DO-204AC)Weight approx. – Gewicht ca.0.4 gPlastic material has UL classification 94V-0Gehäusematerial UL94V-0 klassifiziertDimensions / Maße in mmStandard packaging taped in ammo pack see page 16Standard Lieferform gegurtet in Ammo-Pack siehe Seite 16For bidirectional types (suffix “B”), electrical characteristics apply in both directions.Für bidirektionale Dioden (Suffix “B”) gelten die elektrischen Werte in beiden Richtungen.Maximum ratings and CharacteristicsKenn- und GrenzwertePeak pulse power dissipation (10/1000 :s waveform)T A = 25/C P PPM 600 W 1)Impuls-Verlustleistung (Strom-Impuls 10/1000 :s)Steady state power dissipation T A = 25/C P M(AV) 5 W 2)Verlustleistung im DauerbetriebPeak forward surge current, 60 Hz half sine-wave T A = 25/CI FSM 100 A 3)Stoßstrom für eine 60 Hz Sinus-HalbwelleOperating junction temperature – Sperrschichttemperatur T j – 50…+175/C Storage temperature – Lagerungstemperatur T S – 50…+175/CMax. instantaneous forward voltage I F = 50 AV BR # 200 V V F < 3.0 V 3)Augenblickswert der DurchlaßspannungV BR > 200 V V F < 6.5 V 3)Thermal resistance junction to ambient airR thA < 45 K/W 2)Wärmewiderstand Sperrschicht – umgebende Luft Thermal resistance junction to leadR thL< 15 K/WWärmewiderstand Sperrschicht – Anschlußdraht2F:\Data\Wp\DatBlatt\Einzelblätter\bzw06.wpdMaximum ratingsGrenzwerteType TypStand-off voltage Sperrspanng Max. rev. current Max. Sperrstrom at / bei V WM Breakdown voltage at I T = 1 mA Abbruch-Spannung bei I T = 1 mA *) at / bei I T = 10 mA Max. clamping voltage Max. Begrenzer-Spanng at / bei I PPM (10/1000:s) V WM [V]I D [:A] V BR min. [V]V BR max. [V]V C [V]I PPM [A]BZW 06-5V85.810006.8 ± 5% 6.45...7.14 *)10.557BZW 06-6V4 6.45007.5 ± 5%7.13...7.88 *)11.353BZW 06-7V07.022008.2 ± 5%7.79...8.61 *)12.150BZW 06-7V87.78509.1 ± 5%8.65...9.5513.445BZW 06-8V58.551010 ± 5%9.5...10.514.541BZW 06-9V49.4511 ± 5%10.5...11.615.638BZW 06-1010.2512 ± 5%11.4...12.616.736BZW 06-1111.1513 ± 5%12.4...13.718.233BZW 06-1312.8515 ± 5%14.3...15.821.228BZW 06-1413.6516 ± 5%15.2...16.822.527BZW 06-1515.3518 ± 5%17.1...18.925.224BZW 06-1717.1520 ± 5%19.0...21.027.722BZW 06-1918.8522 ± 5%20.9...23.130.620BZW 06-2020.5524 ± 5%22.8...25.233.218BZW 06-2323.1527 ± 5%25.7...28.437.516BZW 06-2625,6530 ± 5%28.5...31.541.514.5BZW 06-2828.2533 ± 5%31.4...34.745.713.1BZW 06-3130.8536 ± 5%34.2...37.849.912.0BZW 06-3333.3539 ± 5%37.1...41.053.911.1BZW 06-3736.8543 ± 5%40.9...45.259.310.1BZW 06-4040.2547 ± 5%44.7...49.464.89.3BZW 06-4443.6551 ± 5%48.5...53.670.18.6BZW 06-4847.8556 ± 5%53.2...58.877.07.8BZW 06-5353.0562 ± 5%58.9...65.185.07.1BZW 06-5858.1568 ± 5%64.6...71.492.0 6.5BZW 06-6464.1575 ± 5%71.3...78.8103 5.8BZW 06-7070.1582 ± 5%77.9...86.1113 5.3BZW 06-7877.8591 ± 5%86.5...95.5125 4.8BZW 06-8585.85100 ± 5%95.0...105137 4.4BZW 06-9494.05110 ± 5%105...116152 3.9BZW 06-1021025120 ± 5%114...126165 3.6BZW 06-1111115130 ± 5%124...137179 3.4BZW 06-1281285150 ± 5%143...158207 2.9BZW 06-1361365160 ± 5%152...168219 2.7BZW 06-1451455170 ± 5%162...179234 2.6BZW 06-1541545180 ± 5%171...189246 2.4BZW 06-1711715200 ± 5%190...210274 2.2BZW 06-1881885220 ± 5%209...231301 2.0BZW 06-2132135250 ± 5%237...263344 1.8BZW 06-2392395280 ± 5%266...294384 1.7BZW 06-2562565300 ± 5%285...315414 1.6BZW 06-2732735320 ± 5%304...336438 1.6BZW 06-2992995350 ± 5%332...368482 1.6BZW 06-3423425400 ± 5%380...420548 1.3BZW 06-3763765440 ± 5%418 (462)6031.31)Valid, if leads are kept at ambient temperature at a distance of 10 mm from caseGültig, wenn die Anschlußdrähte in 10 mm Abstand von Gehäuse auf Umgebungstemperatur gehalten werden 307.01.2003For bidirectional types (suffix “B”), electrical characteristics apply in both directions.Für bidirektionale Dioden (Suffix “B”) gelten die elektrischen Werte in beiden Richtungen.The standard tolerance of the breakdown voltage for each type is ± 5%.Die Toleranz der Arbeitsspannung jeder Diode beträgt in der Standardausführung ± 5%.e.g.:BZW 06-171B = bidirectional diode V WM $ 171 V at I D = 5 :A, V BR = 200 V (± 5%)BZW 06-6.4 = unidirectional diode, V WM $ 6.4 V at I D = 500 :A, V BR = 7.5 V (± 5%)。

注意:
当您安装 CPU 时，请确认所有的电源接口都已拔除。
1. 在您购买本主板之后，请确认在 LGA775 插座上附有一个即插即用的保 护盖，并且插座接点没有弯曲变形。若是保护盖已经毁损或是没有保护盖， 或者是插座接点已经弯曲，请立即与您的经销商联络。2. 在安装完主板之 后，请将即插即用的保护盖保留下来。
描述 24 引脚 8 引脚 6 引脚母头/4 引脚 4 引脚/RJ-45 连接器 6 孔小三芯插孔连接器 34 引脚 40 引脚 一芯插孔 火线接口(firewire) 7 引脚 4 引脚连接器
5
简介
连接头
连接头
名称
FPANEL1/SPEAK1 前面板开关和指示灯
FUSB1/2/3
可扩展 接口
SFAN2/3/4
风扇引脚头
CFAN
CPU 风扇引脚头
F_AUDIO1
扬声器,麦克风连接头
JCOM1
串行 COM 连接头
JSPDIF1
SPDIF 连接头
J1394
IEEE1394 连接头
描述 13PIN 插头 9PIN 扩展接头 3 引脚 4 引脚 9 引脚 9 引脚 5 引脚 9 引脚
扩展槽
插座/插槽 LGA 775 DIMM1-4 PCIE1/4 PCIE2/3 PCI1/2
连接器
连接器 ATXPWR PWR2 USBPS2 CN1/2 AUDIO1 FDD IDE1 SPDIF_In/Out IEEE1394 SATA1-3 ESATA
名称 ATX 电源连接器 ATX12V 电源连接器 PS/2 键盘连接器/ USB 端口连接器 USB 端口连接器/千兆网络 8 声道音频连接器 软盘驱动器数据连接器 IDE 数据连接器 SPDIF 同轴输入/光纤输出接口 IEEE1394 接口 串行 ATA2 端口数据连接器 eSATA 接口

Cathode Mark
.152 (3.85) .140 (3.55) .112 (2.85) .100 (2.55)
Top View
max. .004 (0.1)
max. .053 (1.35)
min. .010 (0.25)
max. .006 (0.15)
.067 (1.70) .055 (1.40)
50 25 15 10 5.0 5.0 5.0 5.0 5.0 5.0 3.0 3.0 3.0 3.0 3.0 3.0 2.0 1.0 0.5 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1
1.0 1.0 1.0 1.0 1.0 2.0 2.0 3.0 3.5 4.0 5.0 6.0 6.5 6.5 7.0 8.0 8.4 9.1 9.9 10 11 12 13 14 14 15 17 18 19 21 21 23 25 27 30 33 36 39 43 46 47 52 56
NOTES: (1) The Zener Impedance is derived from the 1kHz AC voltage which results when an AC current having an RMS value equal to 10% of the Zener current (IZT or IZK) is superimposed on IZT or IZK. Zener Impedance is measured at two points to insure a sharp knee on the breakdown curve and to eliminate unstable units. (2) Measured with device junction in thermal equilibrium.

HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM16.5mW (Max) CMOS lnput level MH1M365CXJ/CNXJ- 5 2.67W (Max) MH1M365CXJ/CNXJ- 6 2.20W (Max) MH1M365CXJ/CNXJ- 7 1.90W (Max)Hyper-page mode , RAS-only refresh , CAS before RAS refresh, Hidden refresh capabilities1024 refresh cycles every 16.4ms (A 0 ~ A 9)MH1M365CXJ Gold platingMH1M365CNXJ Nickel+solder platingDESCRIPTIONAPPLICATIONMain memory unit for computers, Microcomputer memory,Refresh memory for CRTThe MH1M365CXJ/CNXJ is 1048576-word x 36-bits dynamic RAM. This consists of two industry standard 1M x 16 dynamic RAMs in SOJ and one industry 1M x 4 dyanmic RAMs in SOJ. The mounting of SOJ on a single in-line package provides any application where high densities and large quantities of memory are required. This is a socket-type memory module,suitable for easy interchange or addition of modules.HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM FUNCTIONin addition to normal read, write, a number of otherThe input conditions for each are shown in Table 1.functions, e.g., hyper page mode, RAS only refresh,Table 1 Input conditions for each modeNote : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid,APD : applied, OPN : openHYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM(Ta=0 ~ 70 °C, unless otherwise noted) (Note 1)Note 1 : All voltage values are with respect to VssELECTRICAL CHARACTERISTICS(Ta=0 ~ 70°C, Vcc=5.0V ± 10%, Vss=0V, unless otherwise noted) (Note 2)Symbol V OH V OL I OZ I II CC1 (AV)I CC2I CC3 (AV)I CC4(AV)I CC6(AV)High-level output voltage ParameterLimitsMin Max Unit TypTest conditionsLow-level output voltage Off-state output current Input currentAverage supply current from Vcc operating(Note 3,4,5)(Note 3,5)(Note 3,4,5)Supply current from Vcc , stand-by Average supply current from Vcc refreshingAverage supply current from VccHyper-Page-ModeAverage supply current from VccCAS before RAS refresh mode MH1M365C -5MH1M365C -6MH1M365C -7I OH =-5.0mA I OL =4.2mAQ floating 0V ≤ V OUT ≤ 5.5V 0V ≤ V IN ≤ 6 V, Other inputs pins=0VRAS, CAS cycling t RC =t WC =min.output openRAS= CAS =V IH, output open RAS= CAS ≥ Vcc - 0.2 V RAS cycling, CAS= V IH t RC =min.output openRAS=V IL, CAS cyclingt PC =min.output openCAS before RAS refresh cycling t RC =min.output openV V µA µAmA mA mA mA mA Vcc 0.4 1030 634653853352.4 0-10-30Note 2: Current flowing into an IC is positive, out is negative.3: Icc1 (AV), Icc3 (AV) and Icc4 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate. 4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open. 5: Column Address can be changed once or less while RAS=V IL and CAS=V IH .485400345(Note 6)485400345455360305MH1M365C -5MH1M365C -6MH1M365C -7MH1M365C -5MH1M365C -6MH1M365C -7MH1M365C -5MH1M365C -6MH1M365C -7(Note 3)HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAMSWITCHING CHARACTERISTICS(Ta=0 ~ 70 °C, Vcc = 5V ± 10%, Vss=0V, unless otherwise noted , see notes 6,14,15)ParameterAccess time from CAS Access time from RAS Column address access time Symbolns ns ns ns 1530356013253050Access time from CAS precharge (Note 7,8)(Note 7,9)(Note 7,10)(Note 7,11)LimitsUnitMinMax MH1M365C -5MinMax 20354070MinMax 55ns Output disable time after WE high Output disable time after CAS high Output disable time after RAS high131313151515ns ns ns(Note 12)(Note 12,13)(Note 12,13)Output low impedance time from CAS low (Note 7)5202020Note 6: An initial pause of 500µs is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS clock such as RAS-Only refresh).(greater than 16.4 ms) of RAS inactivity before proper device operation is achieved.7: Measured with a load circuit equivalent to VOH=2.4V(IOH=-5mA) / VOL=0.4V(IOL=-4.2mA) load 100pF. The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL). 8: Assumes that t RCD ≥ t RCD(max) and t ASC ≥ t ASC(max) and t CP ≥t CP(max).9: Assumes that t RCD ≤ t RCD(max) and t RAD ≤ t RAD(max). If t RCD or t RAD is greater than the maximum recommended value shown in this table,t RAC will increase by amount that t RCD exceeds the value shown. 10: Assumes that t RAD ≥ t RAD(max) and t ASC ≤ t ASC(max).11: Assumes that t CP ≤ t CP(max) and t ASC ≥ t ASC(max).12: t WEZ(max) ,t OFF(max) and t REZ(max)defines the time at which the output achieves the high impedance state ( I OUT ≤ I ± 10 µA I)and is not reference to V OH(min) or V OL(max).13: Output is disabled after both RAS and CAS go to high.ns 55Output hold time from CAS5ns 55Output hold time from RAS5(Note 13)t CACt RAC t AA t CPA t OHC t OHR t CLZ t WEZ t OFF t REZMH1M365C -6MH1M365C -7HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAMTIMING REQUIREMENTS (For Read, Write, Refresh, and Hyper-Page Mode Cycles)(Ta=0 ~ 70°C, Vcc = 5V ± 10%, Vss=0V, unless otherwise noted See notes 14,15)Note 14: The timing requirements are assumed t T =3ns.15: V IH(min) and V IL(max) are reference levels for measuring timing of input signals.16: t RCD(max) is specified as a reference point only. If t RCD is less than t RCD(max), access time is t RAC. If t RCD is greater than t RCD(max), accesstime is controlled exclusively by t CAC or t AA.17: t RAD(max) is specified as a reference point only. If t RAD ≤ t RAD(max) and t ASC ≤ t ASC(max), access time is controlled exclusively by t AA. 18: t ASC(max) is specified as a reference point only. If t RCD ≥ t RCD(max) and t ASC ≥ t ASC(max), access time is controlled exclusively by t CAC. 19: t DZC must be satisfied.20: Either t RDD or t CDD or t ODD must be satisfied. 21: t T is measured between V IH(min) and V IL(max).Read and Refresh CyclesNote 22: Either t RCH or t RRH must be satisfied for a read cycle.ParameterRefresh cycle time RAS high pulse widthDelay time, RAS low to CAS low Symbol Delay time, CAS high to RAS low Delay time, RAS high to CAS low CAS high pulse width(Note21)(Note16)(Note17)(Note18)16.4453004013502051015101000116.43725030105018 5 813 8 8001Column address delay time from RAS lowRow address setup time before RAS lowColumn address setup time before CAS lowRow address hold time after RAS low Column address hold time after CAS low Transition time(Note19)(Note20)Delay time, data to CAS low Delay time, CAS high to data 001513(Note20)Delay time, RAS high to data 1513ms ns ns ns ns ns ns LimitsUnit MinMax Min Max ns ns ns MinMax 16.4503505013502051015101000102020ns ns ns ns nst REF t RP t RCD t CRP t RPC t CPN t RAD t ASR t ASC t RAH t CAH t DZC t RDD t CDD t TMH1M365C -5MH1M365C -6MH1M365C -7HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAMWrite Cycle (Early Write)ParameterWrite cycle time RAS low pulse width CAS low pulse width Symbol8CAS hold time after RAS low Write setup time before CAS low Write hold time after CAS low 0RAS hold time after CAS low 10000100001000010000 90 50 840138 0100110 60 1048 1510 0810Data setup time before CAS low or W low Data hold time after CAS low or W lowWrite pulse widthnsns ns ns ns ns ns LimitsUnitMinMax Min Maxns ns Min Max100001000013013070 1355 2013 013nst WC t RAS t CAS t CSH t RSH t WCS t WCH t WP t DS t DHMH1M365C -5MH1M365C -6MH1M365C -7Note 26: Eight or more CAS before RAS cycles instead of eight RAS cycles are necessary for proper operation of CAS before RAS refresh mode.CAS before RAS Refresh Cycle (Note 26)LimitsMin MaxParameterCAS setup time before RAS low Symbol t CSR UnitMin MaxMin Maxns ns t CHR510CAS hold time after RAS low510515Hyper page Mode Cycle (Read, Early Write, Hi-Z control by W) (Note 25)Note 23: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle. 24: t RAS(min) 25: t CP(max) is specified as a reference point only.ParameterHyper page mode read/write cycle time RAS low pulse width for read write cycle CAS high pulse widthSymbol RAS hold time after CAS precharge(Note24)(Note25)Hold time to maintain the data Hi-Z until CAS access W Pulse Width (Hi-Z control)Output hold time from CAS low30 2065810000035 2577101000001316 7 7 77ns ns ns ns ns LimitsUnit MinMaxMin MaxnsMin Max4030921310000016 77ns 555t HPC t DOH t RAS t CP t CPRH t CHOL t WPEMH1M365C -5MH1M365C -6MH1M365C -7MH1M365C -5MH1M365C -6MH1M365C -7HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAMTiming Diagrams (Note 27)Read CycleDQ(INPUTS)VV V V V V V V V V V V Note 27Indicates the don't care input.V IH(min) ≤ V IN ≤ V IH(max) or V IL(min) ≤ V IN ≤ V IL(max)Indicates the invalid output.RASWDQ(OUTPUTS)CASA0~A9HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAMEarly Write CycleVV V V V V V V V V V V RASWA0~A9DQ(INPUTS)DQ(OUTPUTS)CASHYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAMHyper Page Mode Read CycleVV V V V V V V V V V V DQ(INPUTS)RASWDQ(OUTPUTS)CASA0~A9HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAMHyper Page Mode Early Write CycleVV V V V V V V V V V OHV OLDQ(INPUTS)RASWDQ(OUTPUTS)CASA0~A9HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAMHyper Page Mode Read Cycle ( Hi-Z control by W )VV ILV V ILV V ILV V ILV V ILV V DQ(INPUTS)RASWDQ(OUTPUTS)CASA0~A9HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAMRAS-only Refresh CycleVV ILV V ILV V ILV V ILV V ILV V DQ(INPUT)RASWDQ(OUTPUT)CASA0~A9HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAMCAS before RAS Refresh CycleVV V V V V V V V V V V DQ(INPOUT)RASWDQ(OUTPUT)CASA0~A9HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAMHidden Refresh Cycle (Read) (Note 28)Note 28: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle. Timing requirements and output state are the same as that of each cycle shown above.VV V V V V V V V V V V DQ(INOUT)RASWDQ(OUTPUT)CASA0~A9HYPER PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM 72pin DRAM Module Outline。