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LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY counter6 IS
PORT(clk:IN STD_LOGIC;
reset:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
c:OUT STD_LOGIC);
END counter6;
ARCHITECTURE dianzizhong OF counter6 IS
SIGNAL count:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
dout<=count;
PROCESS(clk,reset,din)
BEGIN
IF reset='0'
THEN count<=din; c<='0';
ELSIF rising_edge(clk) THEN IF count="101" THEN count<="000"; c<='1'; ELSE
count<=count+1; c<='0'; END IF; END IF; END PROCESS;
END dianzizhong;
